1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_wa.h" 7 8 #include <drm/drm_managed.h> 9 #include <kunit/visibility.h> 10 #include <linux/compiler_types.h> 11 #include <linux/fault-inject.h> 12 13 #include <generated/xe_device_wa_oob.h> 14 #include <generated/xe_wa_oob.h> 15 16 #include "regs/xe_engine_regs.h" 17 #include "regs/xe_gt_regs.h" 18 #include "regs/xe_regs.h" 19 #include "xe_device_types.h" 20 #include "xe_force_wake.h" 21 #include "xe_gt.h" 22 #include "xe_hw_engine_types.h" 23 #include "xe_mmio.h" 24 #include "xe_platform_types.h" 25 #include "xe_rtp.h" 26 #include "xe_sriov.h" 27 #include "xe_step.h" 28 29 /** 30 * DOC: Hardware workarounds 31 * 32 * Hardware workarounds are register programming documented to be executed in 33 * the driver that fall outside of the normal programming sequences for a 34 * platform. There are some basic categories of workarounds, depending on 35 * how/when they are applied: 36 * 37 * - LRC workarounds: workarounds that touch registers that are 38 * saved/restored to/from the HW context image. The list is emitted (via Load 39 * Register Immediate commands) once when initializing the device and saved in 40 * the default context. That default context is then used on every context 41 * creation to have a "primed golden context", i.e. a context image that 42 * already contains the changes needed to all the registers. 43 * 44 * - Engine workarounds: the list of these WAs is applied whenever the specific 45 * engine is reset. It's also possible that a set of engine classes share a 46 * common power domain and they are reset together. This happens on some 47 * platforms with render and compute engines. In this case (at least) one of 48 * them need to keeep the workaround programming: the approach taken in the 49 * driver is to tie those workarounds to the first compute/render engine that 50 * is registered. When executing with GuC submission, engine resets are 51 * outside of kernel driver control, hence the list of registers involved in 52 * written once, on engine initialization, and then passed to GuC, that 53 * saves/restores their values before/after the reset takes place. See 54 * ``drivers/gpu/drm/xe/xe_guc_ads.c`` for reference. 55 * 56 * - GT workarounds: the list of these WAs is applied whenever these registers 57 * revert to their default values: on GPU reset, suspend/resume [1]_, etc. 58 * 59 * - Register whitelist: some workarounds need to be implemented in userspace, 60 * but need to touch privileged registers. The whitelist in the kernel 61 * instructs the hardware to allow the access to happen. From the kernel side, 62 * this is just a special case of a MMIO workaround (as we write the list of 63 * these to/be-whitelisted registers to some special HW registers). 64 * 65 * - Workaround batchbuffers: buffers that get executed automatically by the 66 * hardware on every HW context restore. These buffers are created and 67 * programmed in the default context so the hardware always go through those 68 * programming sequences when switching contexts. The support for workaround 69 * batchbuffers is enabled these hardware mechanisms: 70 * 71 * #. INDIRECT_CTX: A batchbuffer and an offset are provided in the default 72 * context, pointing the hardware to jump to that location when that offset 73 * is reached in the context restore. Workaround batchbuffer in the driver 74 * currently uses this mechanism for all platforms. 75 * 76 * #. BB_PER_CTX_PTR: A batchbuffer is provided in the default context, 77 * pointing the hardware to a buffer to continue executing after the 78 * engine registers are restored in a context restore sequence. This is 79 * currently not used in the driver. 80 * 81 * - Other/OOB: There are WAs that, due to their nature, cannot be applied from 82 * a central place. Those are peppered around the rest of the code, as needed. 83 * Workarounds related to the display IP are the main example. 84 * 85 * .. [1] Technically, some registers are powercontext saved & restored, so they 86 * survive a suspend/resume. In practice, writing them again is not too 87 * costly and simplifies things, so it's the approach taken in the driver. 88 * 89 * .. note:: 90 * Hardware workarounds in xe work the same way as in i915, with the 91 * difference of how they are maintained in the code. In xe it uses the 92 * xe_rtp infrastructure so the workarounds can be kept in tables, following 93 * a more declarative approach rather than procedural. 94 */ 95 96 #undef XE_REG_MCR 97 #define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1) 98 99 __diag_push(); 100 __diag_ignore_all("-Woverride-init", "Allow field overrides in table"); 101 102 static const struct xe_rtp_entry_sr gt_was[] = { 103 { XE_RTP_NAME("14011060649"), 104 XE_RTP_RULES(MEDIA_VERSION_RANGE(1200, 1255), 105 ENGINE_CLASS(VIDEO_DECODE), 106 FUNC(xe_rtp_match_even_instance)), 107 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 108 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 109 }, 110 { XE_RTP_NAME("14011059788"), 111 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), 112 XE_RTP_ACTIONS(SET(DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE)) 113 }, 114 { XE_RTP_NAME("14015795083"), 115 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1260)), 116 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE)) 117 }, 118 119 /* DG1 */ 120 121 { XE_RTP_NAME("1409420604"), 122 XE_RTP_RULES(PLATFORM(DG1)), 123 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE2, CPSSUNIT_CLKGATE_DIS)) 124 }, 125 { XE_RTP_NAME("1408615072"), 126 XE_RTP_RULES(PLATFORM(DG1)), 127 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE2_DIS)) 128 }, 129 130 /* DG2 */ 131 132 { XE_RTP_NAME("22010523718"), 133 XE_RTP_RULES(SUBPLATFORM(DG2, G10)), 134 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE, CG3DDISCFEG_CLKGATE_DIS)) 135 }, 136 { XE_RTP_NAME("14011006942"), 137 XE_RTP_RULES(SUBPLATFORM(DG2, G10)), 138 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE, DSS_ROUTER_CLKGATE_DIS)) 139 }, 140 { XE_RTP_NAME("14014830051"), 141 XE_RTP_RULES(PLATFORM(DG2)), 142 XE_RTP_ACTIONS(CLR(SARB_CHICKEN1, COMP_CKN_IN)) 143 }, 144 { XE_RTP_NAME("18018781329"), 145 XE_RTP_RULES(PLATFORM(DG2)), 146 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB), 147 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB), 148 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB), 149 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB)) 150 }, 151 { XE_RTP_NAME("1509235366"), 152 XE_RTP_RULES(PLATFORM(DG2)), 153 XE_RTP_ACTIONS(SET(XEHP_GAMCNTRL_CTRL, 154 INVALIDATION_BROADCAST_MODE_DIS | 155 GLOBAL_INVALIDATION_MODE)) 156 }, 157 158 /* PVC */ 159 160 { XE_RTP_NAME("18018781329"), 161 XE_RTP_RULES(PLATFORM(PVC)), 162 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB), 163 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB), 164 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB), 165 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB)) 166 }, 167 { XE_RTP_NAME("16016694945"), 168 XE_RTP_RULES(PLATFORM(PVC)), 169 XE_RTP_ACTIONS(SET(XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC)) 170 }, 171 172 /* Xe_LPG */ 173 174 { XE_RTP_NAME("14015795083"), 175 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), GRAPHICS_STEP(A0, B0)), 176 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE)) 177 }, 178 { XE_RTP_NAME("14018575942"), 179 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)), 180 XE_RTP_ACTIONS(SET(COMP_MOD_CTRL, FORCE_MISS_FTLB)) 181 }, 182 { XE_RTP_NAME("22016670082"), 183 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)), 184 XE_RTP_ACTIONS(SET(SQCNT1, ENFORCE_RAR)) 185 }, 186 187 /* Xe_LPM+ */ 188 189 { XE_RTP_NAME("16021867713"), 190 XE_RTP_RULES(MEDIA_VERSION(1300), 191 ENGINE_CLASS(VIDEO_DECODE)), 192 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 193 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 194 }, 195 { XE_RTP_NAME("22016670082"), 196 XE_RTP_RULES(MEDIA_VERSION(1300)), 197 XE_RTP_ACTIONS(SET(XELPMP_SQCNT1, ENFORCE_RAR)) 198 }, 199 200 /* Xe2_LPG */ 201 202 { XE_RTP_NAME("16020975621"), 203 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)), 204 XE_RTP_ACTIONS(SET(XEHP_SLICE_UNIT_LEVEL_CLKGATE, SBEUNIT_CLKGATE_DIS)) 205 }, 206 { XE_RTP_NAME("14018157293"), 207 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)), 208 XE_RTP_ACTIONS(SET(XEHPC_L3CLOS_MASK(0), ~0), 209 SET(XEHPC_L3CLOS_MASK(1), ~0), 210 SET(XEHPC_L3CLOS_MASK(2), ~0), 211 SET(XEHPC_L3CLOS_MASK(3), ~0)) 212 }, 213 214 /* Xe2_LPM */ 215 216 { XE_RTP_NAME("14017421178"), 217 XE_RTP_RULES(MEDIA_VERSION(2000), 218 ENGINE_CLASS(VIDEO_DECODE)), 219 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 220 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 221 }, 222 { XE_RTP_NAME("16021867713"), 223 XE_RTP_RULES(MEDIA_VERSION(2000), 224 ENGINE_CLASS(VIDEO_DECODE)), 225 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 226 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 227 }, 228 { XE_RTP_NAME("14019449301"), 229 XE_RTP_RULES(MEDIA_VERSION(2000), ENGINE_CLASS(VIDEO_DECODE)), 230 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)), 231 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 232 }, 233 234 /* Xe2_HPG */ 235 236 { XE_RTP_NAME("16025250150"), 237 XE_RTP_RULES(GRAPHICS_VERSION(2001)), 238 XE_RTP_ACTIONS(SET(LSN_VC_REG2, 239 LSN_LNI_WGT(1) | 240 LSN_LNE_WGT(1) | 241 LSN_DIM_X_WGT(1) | 242 LSN_DIM_Y_WGT(1) | 243 LSN_DIM_Z_WGT(1))) 244 }, 245 246 /* Xe2_HPM */ 247 248 { XE_RTP_NAME("16021867713"), 249 XE_RTP_RULES(MEDIA_VERSION(1301), 250 ENGINE_CLASS(VIDEO_DECODE)), 251 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 252 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 253 }, 254 { XE_RTP_NAME("14020316580"), 255 XE_RTP_RULES(MEDIA_VERSION(1301)), 256 XE_RTP_ACTIONS(CLR(POWERGATE_ENABLE, 257 VDN_HCP_POWERGATE_ENABLE(0) | 258 VDN_MFXVDENC_POWERGATE_ENABLE(0) | 259 VDN_HCP_POWERGATE_ENABLE(2) | 260 VDN_MFXVDENC_POWERGATE_ENABLE(2))), 261 }, 262 { XE_RTP_NAME("14019449301"), 263 XE_RTP_RULES(MEDIA_VERSION(1301), ENGINE_CLASS(VIDEO_DECODE)), 264 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)), 265 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 266 }, 267 268 /* Xe3_LPG */ 269 270 { XE_RTP_NAME("14021871409"), 271 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0)), 272 XE_RTP_ACTIONS(SET(UNSLCGCTL9454, LSCFE_CLKGATE_DIS)) 273 }, 274 275 /* Xe3_LPM */ 276 277 { XE_RTP_NAME("16021867713"), 278 XE_RTP_RULES(MEDIA_VERSION(3000), 279 ENGINE_CLASS(VIDEO_DECODE)), 280 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 281 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 282 }, 283 { XE_RTP_NAME("16021865536"), 284 XE_RTP_RULES(MEDIA_VERSION(3000), 285 ENGINE_CLASS(VIDEO_DECODE)), 286 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 287 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 288 }, 289 { XE_RTP_NAME("16021865536"), 290 XE_RTP_RULES(MEDIA_VERSION(3002), 291 ENGINE_CLASS(VIDEO_DECODE)), 292 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 293 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 294 }, 295 { XE_RTP_NAME("16021867713"), 296 XE_RTP_RULES(MEDIA_VERSION(3002), 297 ENGINE_CLASS(VIDEO_DECODE)), 298 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 299 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 300 }, 301 { XE_RTP_NAME("14021486841"), 302 XE_RTP_RULES(MEDIA_VERSION(3000), MEDIA_STEP(A0, B0), 303 ENGINE_CLASS(VIDEO_DECODE)), 304 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), RAMDFTUNIT_CLKGATE_DIS)), 305 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 306 }, 307 }; 308 309 static const struct xe_rtp_entry_sr engine_was[] = { 310 { XE_RTP_NAME("22010931296, 18011464164, 14010919138"), 311 XE_RTP_RULES(GRAPHICS_VERSION(1200), ENGINE_CLASS(RENDER)), 312 XE_RTP_ACTIONS(SET(FF_THREAD_MODE(RENDER_RING_BASE), 313 FF_TESSELATION_DOP_GATE_DISABLE)) 314 }, 315 { XE_RTP_NAME("1409804808"), 316 XE_RTP_RULES(GRAPHICS_VERSION(1200), 317 ENGINE_CLASS(RENDER), 318 IS_INTEGRATED), 319 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, PUSH_CONST_DEREF_HOLD_DIS)) 320 }, 321 { XE_RTP_NAME("14010229206, 1409085225"), 322 XE_RTP_RULES(GRAPHICS_VERSION(1200), 323 ENGINE_CLASS(RENDER), 324 IS_INTEGRATED), 325 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH)) 326 }, 327 { XE_RTP_NAME("1606931601"), 328 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 329 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_EARLY_READ)) 330 }, 331 { XE_RTP_NAME("14010826681, 1606700617, 22010271021, 18019627453"), 332 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1255), ENGINE_CLASS(RENDER)), 333 XE_RTP_ACTIONS(SET(CS_DEBUG_MODE1(RENDER_RING_BASE), 334 FF_DOP_CLOCK_GATE_DISABLE)) 335 }, 336 { XE_RTP_NAME("1406941453"), 337 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 338 XE_RTP_ACTIONS(SET(SAMPLER_MODE, ENABLE_SMALLPL)) 339 }, 340 { XE_RTP_NAME("FtrPerCtxtPreemptionGranularityControl"), 341 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1250), ENGINE_CLASS(RENDER)), 342 XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN1(RENDER_RING_BASE), 343 FFSC_PERCTX_PREEMPT_CTRL)) 344 }, 345 346 /* TGL */ 347 348 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"), 349 XE_RTP_RULES(PLATFORM(TIGERLAKE), ENGINE_CLASS(RENDER)), 350 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE), 351 WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 352 RC_SEMA_IDLE_MSG_DISABLE)) 353 }, 354 355 /* RKL */ 356 357 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"), 358 XE_RTP_RULES(PLATFORM(ROCKETLAKE), ENGINE_CLASS(RENDER)), 359 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE), 360 WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 361 RC_SEMA_IDLE_MSG_DISABLE)) 362 }, 363 364 /* ADL-P */ 365 366 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"), 367 XE_RTP_RULES(PLATFORM(ALDERLAKE_P), ENGINE_CLASS(RENDER)), 368 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE), 369 WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 370 RC_SEMA_IDLE_MSG_DISABLE)) 371 }, 372 373 /* DG2 */ 374 375 { XE_RTP_NAME("22013037850"), 376 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 377 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, 378 DISABLE_128B_EVICTION_COMMAND_UDW)) 379 }, 380 { XE_RTP_NAME("22014226127"), 381 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 382 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE)) 383 }, 384 { XE_RTP_NAME("18017747507"), 385 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 386 XE_RTP_ACTIONS(SET(VFG_PREEMPTION_CHICKEN, 387 POLYGON_TRIFAN_LINELOOP_DISABLE)) 388 }, 389 { XE_RTP_NAME("22012826095, 22013059131"), 390 XE_RTP_RULES(SUBPLATFORM(DG2, G11), 391 FUNC(xe_rtp_match_first_render_or_compute)), 392 XE_RTP_ACTIONS(FIELD_SET(LSC_CHICKEN_BIT_0_UDW, 393 MAXREQS_PER_BANK, 394 REG_FIELD_PREP(MAXREQS_PER_BANK, 2))) 395 }, 396 { XE_RTP_NAME("22013059131"), 397 XE_RTP_RULES(SUBPLATFORM(DG2, G11), 398 FUNC(xe_rtp_match_first_render_or_compute)), 399 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, FORCE_1_SUB_MESSAGE_PER_FRAGMENT)) 400 }, 401 { XE_RTP_NAME("14015227452"), 402 XE_RTP_RULES(PLATFORM(DG2), 403 FUNC(xe_rtp_match_first_render_or_compute)), 404 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE)) 405 }, 406 { XE_RTP_NAME("18028616096"), 407 XE_RTP_RULES(PLATFORM(DG2), 408 FUNC(xe_rtp_match_first_render_or_compute)), 409 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3)) 410 }, 411 { XE_RTP_NAME("22015475538"), 412 XE_RTP_RULES(PLATFORM(DG2), 413 FUNC(xe_rtp_match_first_render_or_compute)), 414 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8)) 415 }, 416 { XE_RTP_NAME("22012654132"), 417 XE_RTP_RULES(SUBPLATFORM(DG2, G11), 418 FUNC(xe_rtp_match_first_render_or_compute)), 419 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, ENABLE_PREFETCH_INTO_IC, 420 /* 421 * Register can't be read back for verification on 422 * DG2 due to Wa_14012342262 423 */ 424 .read_mask = 0)) 425 }, 426 { XE_RTP_NAME("1509727124"), 427 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 428 XE_RTP_ACTIONS(SET(SAMPLER_MODE, SC_DISABLE_POWER_OPTIMIZATION_EBB)) 429 }, 430 { XE_RTP_NAME("22012856258"), 431 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 432 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_READ_SUPPRESSION)) 433 }, 434 { XE_RTP_NAME("22010960976, 14013347512"), 435 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 436 XE_RTP_ACTIONS(CLR(XEHP_HDC_CHICKEN0, 437 LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK)) 438 }, 439 { XE_RTP_NAME("14015150844"), 440 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 441 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES, 442 XE_RTP_NOCHECK)) 443 }, 444 445 /* PVC */ 446 447 { XE_RTP_NAME("22014226127"), 448 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)), 449 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE)) 450 }, 451 { XE_RTP_NAME("14015227452"), 452 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)), 453 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE)) 454 }, 455 { XE_RTP_NAME("18020744125"), 456 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute), 457 ENGINE_CLASS(COMPUTE)), 458 XE_RTP_ACTIONS(SET(RING_HWSTAM(RENDER_RING_BASE), ~0)) 459 }, 460 { XE_RTP_NAME("14014999345"), 461 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COMPUTE), 462 GRAPHICS_STEP(B0, C0)), 463 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, DISABLE_ECC)) 464 }, 465 466 /* Xe_LPG */ 467 468 { XE_RTP_NAME("14017856879"), 469 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), 470 FUNC(xe_rtp_match_first_render_or_compute)), 471 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, DIS_FIX_EOT1_FLUSH)) 472 }, 473 { XE_RTP_NAME("14015150844"), 474 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), 475 FUNC(xe_rtp_match_first_render_or_compute)), 476 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES, 477 XE_RTP_NOCHECK)) 478 }, 479 { XE_RTP_NAME("14020495402"), 480 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), 481 FUNC(xe_rtp_match_first_render_or_compute)), 482 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_TDL_SVHS_GATING)) 483 }, 484 485 /* Xe2_LPG */ 486 487 { XE_RTP_NAME("18032247524"), 488 XE_RTP_RULES(GRAPHICS_VERSION(2004), 489 FUNC(xe_rtp_match_first_render_or_compute)), 490 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE)) 491 }, 492 { XE_RTP_NAME("16018712365"), 493 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 494 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS)) 495 }, 496 { XE_RTP_NAME("14018957109"), 497 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 498 FUNC(xe_rtp_match_first_render_or_compute)), 499 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN5, DISABLE_SAMPLE_G_PERFORMANCE)) 500 }, 501 { XE_RTP_NAME("14020338487"), 502 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 503 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS)) 504 }, 505 { XE_RTP_NAME("18034896535, 16021540221"), /* 16021540221: GRAPHICS_STEP(A0, B0) */ 506 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), 507 FUNC(xe_rtp_match_first_render_or_compute)), 508 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH)) 509 }, 510 { XE_RTP_NAME("14019322943"), 511 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 512 FUNC(xe_rtp_match_first_render_or_compute)), 513 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, TGM_WRITE_EOM_FORCE)) 514 }, 515 { XE_RTP_NAME("14018471104"), 516 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 517 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL)) 518 }, 519 /* 520 * These two workarounds are the same, just applying to different 521 * engines. Although Wa_18032095049 (for the RCS) isn't required on 522 * all steppings, disabling these reports has no impact for our 523 * driver or the GuC, so we go ahead and treat it the same as 524 * Wa_16021639441 which does apply to all steppings. 525 */ 526 { XE_RTP_NAME("18032095049, 16021639441"), 527 XE_RTP_RULES(GRAPHICS_VERSION(2004)), 528 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), 529 GHWSP_CSB_REPORT_DIS | 530 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, 531 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 532 }, 533 { XE_RTP_NAME("16018610683"), 534 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 535 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, SLM_WMTP_RESTORE)) 536 }, 537 { XE_RTP_NAME("14021402888"), 538 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 539 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE)) 540 }, 541 { XE_RTP_NAME("13012615864"), 542 XE_RTP_RULES(GRAPHICS_VERSION(2004), 543 FUNC(xe_rtp_match_first_render_or_compute)), 544 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS)) 545 }, 546 547 /* Xe2_HPG */ 548 549 { XE_RTP_NAME("16018712365"), 550 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 551 FUNC(xe_rtp_match_first_render_or_compute)), 552 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS)) 553 }, 554 { XE_RTP_NAME("16018737384"), 555 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED), 556 FUNC(xe_rtp_match_first_render_or_compute)), 557 XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS)) 558 }, 559 { XE_RTP_NAME("14019988906"), 560 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 561 FUNC(xe_rtp_match_first_render_or_compute)), 562 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD)) 563 }, 564 { XE_RTP_NAME("14019877138"), 565 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 566 FUNC(xe_rtp_match_first_render_or_compute)), 567 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 568 }, 569 { XE_RTP_NAME("14020338487"), 570 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 571 FUNC(xe_rtp_match_first_render_or_compute)), 572 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS)) 573 }, 574 { XE_RTP_NAME("18032247524"), 575 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 576 FUNC(xe_rtp_match_first_render_or_compute)), 577 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE)) 578 }, 579 { XE_RTP_NAME("14018471104"), 580 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 581 FUNC(xe_rtp_match_first_render_or_compute)), 582 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL)) 583 }, 584 /* 585 * Although this workaround isn't required for the RCS, disabling these 586 * reports has no impact for our driver or the GuC, so we go ahead and 587 * apply this to all engines for simplicity. 588 */ 589 { XE_RTP_NAME("16021639441"), 590 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002)), 591 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), 592 GHWSP_CSB_REPORT_DIS | 593 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, 594 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 595 }, 596 { XE_RTP_NAME("14019811474"), 597 XE_RTP_RULES(GRAPHICS_VERSION(2001), 598 FUNC(xe_rtp_match_first_render_or_compute)), 599 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, WR_REQ_CHAINING_DIS)) 600 }, 601 { XE_RTP_NAME("14021402888"), 602 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), 603 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE)) 604 }, 605 { XE_RTP_NAME("14021821874, 14022954250"), 606 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 607 FUNC(xe_rtp_match_first_render_or_compute)), 608 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, STK_ID_RESTRICT)) 609 }, 610 { XE_RTP_NAME("13012615864"), 611 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 612 FUNC(xe_rtp_match_first_render_or_compute)), 613 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS)) 614 }, 615 616 /* Xe2_LPM */ 617 618 { XE_RTP_NAME("16021639441"), 619 XE_RTP_RULES(MEDIA_VERSION(2000)), 620 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), 621 GHWSP_CSB_REPORT_DIS | 622 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, 623 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 624 }, 625 626 /* Xe2_HPM */ 627 628 { XE_RTP_NAME("16021639441"), 629 XE_RTP_RULES(MEDIA_VERSION(1301)), 630 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), 631 GHWSP_CSB_REPORT_DIS | 632 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, 633 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 634 }, 635 636 /* Xe3_LPG */ 637 638 { XE_RTP_NAME("14021402888"), 639 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), 640 FUNC(xe_rtp_match_first_render_or_compute)), 641 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE)) 642 }, 643 { XE_RTP_NAME("18034896535"), 644 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0), 645 FUNC(xe_rtp_match_first_render_or_compute)), 646 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH)) 647 }, 648 { XE_RTP_NAME("16024792527"), 649 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0), 650 FUNC(xe_rtp_match_first_render_or_compute)), 651 XE_RTP_ACTIONS(FIELD_SET(SAMPLER_MODE, SMP_WAIT_FETCH_MERGING_COUNTER, 652 SMP_FORCE_128B_OVERFETCH)) 653 }, 654 { XE_RTP_NAME("14023061436"), 655 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), 656 FUNC(xe_rtp_match_first_render_or_compute)), 657 XE_RTP_ACTIONS(SET(TDL_CHICKEN, QID_WAIT_FOR_THREAD_NOT_RUN_DISABLE)) 658 }, 659 { XE_RTP_NAME("13012615864"), 660 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), OR, 661 GRAPHICS_VERSION(3003), 662 FUNC(xe_rtp_match_first_render_or_compute)), 663 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS)) 664 }, 665 { XE_RTP_NAME("16023105232"), 666 XE_RTP_RULES(MEDIA_VERSION_RANGE(1301, 3000), OR, 667 GRAPHICS_VERSION_RANGE(2001, 3001)), 668 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(0), RC_SEMA_IDLE_MSG_DISABLE, 669 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 670 }, 671 { XE_RTP_NAME("14021402888"), 672 XE_RTP_RULES(GRAPHICS_VERSION(3003), FUNC(xe_rtp_match_first_render_or_compute)), 673 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE)) 674 }, 675 }; 676 677 static const struct xe_rtp_entry_sr lrc_was[] = { 678 { XE_RTP_NAME("16011163337"), 679 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 680 /* read verification is ignored due to 1608008084. */ 681 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2, 682 FF_MODE2_GS_TIMER_MASK, 683 FF_MODE2_GS_TIMER_224)) 684 }, 685 { XE_RTP_NAME("1604555607"), 686 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 687 /* read verification is ignored due to 1608008084. */ 688 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2, 689 FF_MODE2_TDS_TIMER_MASK, 690 FF_MODE2_TDS_TIMER_128)) 691 }, 692 { XE_RTP_NAME("1409342910, 14010698770, 14010443199, 1408979724, 1409178076, 1409207793, 1409217633, 1409252684, 1409347922, 1409142259"), 693 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), 694 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN3, 695 DISABLE_CPS_AWARE_COLOR_PIPE)) 696 }, 697 { XE_RTP_NAME("WaDisableGPGPUMidThreadPreemption"), 698 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), 699 XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(RENDER_RING_BASE), 700 PREEMPT_GPGPU_LEVEL_MASK, 701 PREEMPT_GPGPU_THREAD_GROUP_LEVEL)) 702 }, 703 { XE_RTP_NAME("1806527549"), 704 XE_RTP_RULES(GRAPHICS_VERSION(1200)), 705 XE_RTP_ACTIONS(SET(HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE)) 706 }, 707 { XE_RTP_NAME("1606376872"), 708 XE_RTP_RULES(GRAPHICS_VERSION(1200)), 709 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC)) 710 }, 711 712 /* DG1 */ 713 714 { XE_RTP_NAME("1409044764"), 715 XE_RTP_RULES(PLATFORM(DG1)), 716 XE_RTP_ACTIONS(CLR(COMMON_SLICE_CHICKEN3, 717 DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN)) 718 }, 719 { XE_RTP_NAME("22010493298"), 720 XE_RTP_RULES(PLATFORM(DG1)), 721 XE_RTP_ACTIONS(SET(HIZ_CHICKEN, 722 DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE)) 723 }, 724 725 /* DG2 */ 726 727 { XE_RTP_NAME("16013271637"), 728 XE_RTP_RULES(PLATFORM(DG2)), 729 XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1, 730 MSC_MSAA_REODER_BUF_BYPASS_DISABLE)) 731 }, 732 { XE_RTP_NAME("14014947963"), 733 XE_RTP_RULES(PLATFORM(DG2)), 734 XE_RTP_ACTIONS(FIELD_SET(VF_PREEMPTION, 735 PREEMPTION_VERTEX_COUNT, 736 0x4000)) 737 }, 738 { XE_RTP_NAME("18018764978"), 739 XE_RTP_RULES(PLATFORM(DG2)), 740 XE_RTP_ACTIONS(SET(XEHP_PSS_MODE2, 741 SCOREBOARD_STALL_FLUSH_CONTROL)) 742 }, 743 { XE_RTP_NAME("18019271663"), 744 XE_RTP_RULES(PLATFORM(DG2)), 745 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE)) 746 }, 747 { XE_RTP_NAME("14019877138"), 748 XE_RTP_RULES(PLATFORM(DG2)), 749 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 750 }, 751 752 /* PVC */ 753 754 { XE_RTP_NAME("16017236439"), 755 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COPY), 756 FUNC(xe_rtp_match_even_instance)), 757 XE_RTP_ACTIONS(SET(BCS_SWCTRL(0), 758 BCS_SWCTRL_DISABLE_256B, 759 XE_RTP_ACTION_FLAG(ENGINE_BASE))), 760 }, 761 762 /* Xe_LPG */ 763 764 { XE_RTP_NAME("18019271663"), 765 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)), 766 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE)) 767 }, 768 { XE_RTP_NAME("14019877138"), 769 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), ENGINE_CLASS(RENDER)), 770 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 771 }, 772 773 /* Xe2_LPG */ 774 775 { XE_RTP_NAME("16020518922"), 776 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 777 ENGINE_CLASS(RENDER)), 778 XE_RTP_ACTIONS(SET(FF_MODE, 779 DIS_TE_AUTOSTRIP | 780 DIS_MESH_PARTIAL_AUTOSTRIP | 781 DIS_MESH_AUTOSTRIP), 782 SET(VFLSKPD, 783 DIS_PARTIAL_AUTOSTRIP | 784 DIS_AUTOSTRIP)) 785 }, 786 { XE_RTP_NAME("14019386621"), 787 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 788 XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE)) 789 }, 790 { XE_RTP_NAME("14019877138"), 791 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 792 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 793 }, 794 { XE_RTP_NAME("14020013138"), 795 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 796 ENGINE_CLASS(RENDER)), 797 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS)) 798 }, 799 { XE_RTP_NAME("14019988906"), 800 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 801 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD)) 802 }, 803 { XE_RTP_NAME("16020183090"), 804 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 805 ENGINE_CLASS(RENDER)), 806 XE_RTP_ACTIONS(SET(INSTPM(RENDER_RING_BASE), ENABLE_SEMAPHORE_POLL_BIT)) 807 }, 808 { XE_RTP_NAME("18033852989"), 809 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 810 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST)) 811 }, 812 { XE_RTP_NAME("14021567978"), 813 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED), 814 ENGINE_CLASS(RENDER)), 815 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_2, TBIMR_FAST_CLIP)) 816 }, 817 { XE_RTP_NAME("14020756599"), 818 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER), OR, 819 MEDIA_VERSION_ANY_GT(2000), ENGINE_CLASS(RENDER)), 820 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS)) 821 }, 822 { XE_RTP_NAME("14021490052"), 823 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 824 XE_RTP_ACTIONS(SET(FF_MODE, 825 DIS_MESH_PARTIAL_AUTOSTRIP | 826 DIS_MESH_AUTOSTRIP), 827 SET(VFLSKPD, 828 DIS_PARTIAL_AUTOSTRIP | 829 DIS_AUTOSTRIP)) 830 }, 831 { XE_RTP_NAME("15016589081"), 832 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 833 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX)) 834 }, 835 836 /* Xe2_HPG */ 837 { XE_RTP_NAME("15010599737"), 838 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 839 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN)) 840 }, 841 { XE_RTP_NAME("14019386621"), 842 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), 843 XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE)) 844 }, 845 { XE_RTP_NAME("14020756599"), 846 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 847 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS)) 848 }, 849 { XE_RTP_NAME("14021490052"), 850 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 851 XE_RTP_ACTIONS(SET(FF_MODE, 852 DIS_MESH_PARTIAL_AUTOSTRIP | 853 DIS_MESH_AUTOSTRIP), 854 SET(VFLSKPD, 855 DIS_PARTIAL_AUTOSTRIP | 856 DIS_AUTOSTRIP)) 857 }, 858 { XE_RTP_NAME("15016589081"), 859 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), 860 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX)) 861 }, 862 { XE_RTP_NAME("22021007897"), 863 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), 864 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE)) 865 }, 866 { XE_RTP_NAME("18033852989"), 867 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 868 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST)) 869 }, 870 871 /* Xe3_LPG */ 872 { XE_RTP_NAME("14021490052"), 873 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0), 874 ENGINE_CLASS(RENDER)), 875 XE_RTP_ACTIONS(SET(FF_MODE, 876 DIS_MESH_PARTIAL_AUTOSTRIP | 877 DIS_MESH_AUTOSTRIP), 878 SET(VFLSKPD, 879 DIS_PARTIAL_AUTOSTRIP | 880 DIS_AUTOSTRIP)) 881 }, 882 }; 883 884 static __maybe_unused const struct xe_rtp_entry oob_was[] = { 885 #include <generated/xe_wa_oob.c> 886 {} 887 }; 888 889 static_assert(ARRAY_SIZE(oob_was) - 1 == _XE_WA_OOB_COUNT); 890 891 static __maybe_unused const struct xe_rtp_entry device_oob_was[] = { 892 #include <generated/xe_device_wa_oob.c> 893 {} 894 }; 895 896 static_assert(ARRAY_SIZE(device_oob_was) - 1 == _XE_DEVICE_WA_OOB_COUNT); 897 898 __diag_pop(); 899 900 /** 901 * xe_wa_process_device_oob - process OOB workaround table 902 * @xe: device instance to process workarounds for 903 * 904 * process OOB workaround table for this device, marking in @xe the 905 * workarounds that are active. 906 */ 907 908 void xe_wa_process_device_oob(struct xe_device *xe) 909 { 910 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(xe); 911 912 xe_rtp_process_ctx_enable_active_tracking(&ctx, xe->wa_active.oob, ARRAY_SIZE(device_oob_was)); 913 914 xe->wa_active.oob_initialized = true; 915 xe_rtp_process(&ctx, device_oob_was); 916 } 917 918 /** 919 * xe_wa_process_gt_oob - process GT OOB workaround table 920 * @gt: GT instance to process workarounds for 921 * 922 * Process OOB workaround table for this platform, marking in @gt the 923 * workarounds that are active. 924 */ 925 void xe_wa_process_gt_oob(struct xe_gt *gt) 926 { 927 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt); 928 929 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.oob, 930 ARRAY_SIZE(oob_was)); 931 gt->wa_active.oob_initialized = true; 932 xe_rtp_process(&ctx, oob_was); 933 } 934 935 /** 936 * xe_wa_process_gt - process GT workaround table 937 * @gt: GT instance to process workarounds for 938 * 939 * Process GT workaround table for this platform, saving in @gt all the 940 * workarounds that need to be applied at the GT level. 941 */ 942 void xe_wa_process_gt(struct xe_gt *gt) 943 { 944 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt); 945 946 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.gt, 947 ARRAY_SIZE(gt_was)); 948 xe_rtp_process_to_sr(&ctx, gt_was, ARRAY_SIZE(gt_was), >->reg_sr); 949 } 950 EXPORT_SYMBOL_IF_KUNIT(xe_wa_process_gt); 951 952 /** 953 * xe_wa_process_engine - process engine workaround table 954 * @hwe: engine instance to process workarounds for 955 * 956 * Process engine workaround table for this platform, saving in @hwe all the 957 * workarounds that need to be applied at the engine level that match this 958 * engine. 959 */ 960 void xe_wa_process_engine(struct xe_hw_engine *hwe) 961 { 962 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); 963 964 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.engine, 965 ARRAY_SIZE(engine_was)); 966 xe_rtp_process_to_sr(&ctx, engine_was, ARRAY_SIZE(engine_was), &hwe->reg_sr); 967 } 968 969 /** 970 * xe_wa_process_lrc - process context workaround table 971 * @hwe: engine instance to process workarounds for 972 * 973 * Process context workaround table for this platform, saving in @hwe all the 974 * workarounds that need to be applied on context restore. These are workarounds 975 * touching registers that are part of the HW context image. 976 */ 977 void xe_wa_process_lrc(struct xe_hw_engine *hwe) 978 { 979 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); 980 981 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.lrc, 982 ARRAY_SIZE(lrc_was)); 983 xe_rtp_process_to_sr(&ctx, lrc_was, ARRAY_SIZE(lrc_was), &hwe->reg_lrc); 984 } 985 986 /** 987 * xe_wa_device_init - initialize device with workaround oob bookkeeping 988 * @xe: Xe device instance to initialize 989 * 990 * Returns 0 for success, negative with error code otherwise 991 */ 992 int xe_wa_device_init(struct xe_device *xe) 993 { 994 unsigned long *p; 995 996 p = drmm_kzalloc(&xe->drm, 997 sizeof(*p) * BITS_TO_LONGS(ARRAY_SIZE(device_oob_was)), 998 GFP_KERNEL); 999 1000 if (!p) 1001 return -ENOMEM; 1002 1003 xe->wa_active.oob = p; 1004 1005 return 0; 1006 } 1007 1008 /** 1009 * xe_wa_gt_init - initialize gt with workaround bookkeeping 1010 * @gt: GT instance to initialize 1011 * 1012 * Returns 0 for success, negative error code otherwise. 1013 */ 1014 int xe_wa_gt_init(struct xe_gt *gt) 1015 { 1016 struct xe_device *xe = gt_to_xe(gt); 1017 size_t n_oob, n_lrc, n_engine, n_gt, total; 1018 unsigned long *p; 1019 1020 n_gt = BITS_TO_LONGS(ARRAY_SIZE(gt_was)); 1021 n_engine = BITS_TO_LONGS(ARRAY_SIZE(engine_was)); 1022 n_lrc = BITS_TO_LONGS(ARRAY_SIZE(lrc_was)); 1023 n_oob = BITS_TO_LONGS(ARRAY_SIZE(oob_was)); 1024 total = n_gt + n_engine + n_lrc + n_oob; 1025 1026 p = drmm_kzalloc(&xe->drm, sizeof(*p) * total, GFP_KERNEL); 1027 if (!p) 1028 return -ENOMEM; 1029 1030 gt->wa_active.gt = p; 1031 p += n_gt; 1032 gt->wa_active.engine = p; 1033 p += n_engine; 1034 gt->wa_active.lrc = p; 1035 p += n_lrc; 1036 gt->wa_active.oob = p; 1037 1038 return 0; 1039 } 1040 ALLOW_ERROR_INJECTION(xe_wa_gt_init, ERRNO); /* See xe_pci_probe() */ 1041 1042 void xe_wa_device_dump(struct xe_device *xe, struct drm_printer *p) 1043 { 1044 size_t idx; 1045 1046 drm_printf(p, "Device OOB Workarounds\n"); 1047 for_each_set_bit(idx, xe->wa_active.oob, ARRAY_SIZE(device_oob_was)) 1048 if (device_oob_was[idx].name) 1049 drm_printf_indent(p, 1, "%s\n", device_oob_was[idx].name); 1050 } 1051 1052 void xe_wa_dump(struct xe_gt *gt, struct drm_printer *p) 1053 { 1054 size_t idx; 1055 1056 drm_printf(p, "GT Workarounds\n"); 1057 for_each_set_bit(idx, gt->wa_active.gt, ARRAY_SIZE(gt_was)) 1058 drm_printf_indent(p, 1, "%s\n", gt_was[idx].name); 1059 1060 drm_printf(p, "\nEngine Workarounds\n"); 1061 for_each_set_bit(idx, gt->wa_active.engine, ARRAY_SIZE(engine_was)) 1062 drm_printf_indent(p, 1, "%s\n", engine_was[idx].name); 1063 1064 drm_printf(p, "\nLRC Workarounds\n"); 1065 for_each_set_bit(idx, gt->wa_active.lrc, ARRAY_SIZE(lrc_was)) 1066 drm_printf_indent(p, 1, "%s\n", lrc_was[idx].name); 1067 1068 drm_printf(p, "\nOOB Workarounds\n"); 1069 for_each_set_bit(idx, gt->wa_active.oob, ARRAY_SIZE(oob_was)) 1070 if (oob_was[idx].name) 1071 drm_printf_indent(p, 1, "%s\n", oob_was[idx].name); 1072 } 1073 1074 /* 1075 * Apply tile (non-GT, non-display) workarounds. Think very carefully before 1076 * adding anything to this function; most workarounds should be implemented 1077 * elsewhere. The programming here is primarily for sgunit/soc workarounds, 1078 * which are relatively rare. Since the registers these workarounds target are 1079 * outside the GT, they should only need to be applied once at device 1080 * probe/resume; they will not lose their values on any kind of GT or engine 1081 * reset. 1082 * 1083 * TODO: We may want to move this over to xe_rtp in the future once we have 1084 * enough workarounds to justify the work. 1085 */ 1086 void xe_wa_apply_tile_workarounds(struct xe_tile *tile) 1087 { 1088 struct xe_mmio *mmio = &tile->mmio; 1089 1090 if (IS_SRIOV_VF(tile->xe)) 1091 return; 1092 1093 if (XE_GT_WA(tile->primary_gt, 22010954014)) 1094 xe_mmio_rmw32(mmio, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS); 1095 } 1096