1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_wa.h" 7 8 #include <drm/drm_managed.h> 9 #include <kunit/visibility.h> 10 #include <linux/compiler_types.h> 11 #include <linux/fault-inject.h> 12 13 #include <generated/xe_wa_oob.h> 14 15 #include "regs/xe_engine_regs.h" 16 #include "regs/xe_gt_regs.h" 17 #include "regs/xe_regs.h" 18 #include "xe_device_types.h" 19 #include "xe_force_wake.h" 20 #include "xe_gt.h" 21 #include "xe_hw_engine_types.h" 22 #include "xe_mmio.h" 23 #include "xe_platform_types.h" 24 #include "xe_rtp.h" 25 #include "xe_sriov.h" 26 #include "xe_step.h" 27 28 /** 29 * DOC: Hardware workarounds 30 * 31 * Hardware workarounds are register programming documented to be executed in 32 * the driver that fall outside of the normal programming sequences for a 33 * platform. There are some basic categories of workarounds, depending on 34 * how/when they are applied: 35 * 36 * - LRC workarounds: workarounds that touch registers that are 37 * saved/restored to/from the HW context image. The list is emitted (via Load 38 * Register Immediate commands) once when initializing the device and saved in 39 * the default context. That default context is then used on every context 40 * creation to have a "primed golden context", i.e. a context image that 41 * already contains the changes needed to all the registers. 42 * 43 * - Engine workarounds: the list of these WAs is applied whenever the specific 44 * engine is reset. It's also possible that a set of engine classes share a 45 * common power domain and they are reset together. This happens on some 46 * platforms with render and compute engines. In this case (at least) one of 47 * them need to keeep the workaround programming: the approach taken in the 48 * driver is to tie those workarounds to the first compute/render engine that 49 * is registered. When executing with GuC submission, engine resets are 50 * outside of kernel driver control, hence the list of registers involved in 51 * written once, on engine initialization, and then passed to GuC, that 52 * saves/restores their values before/after the reset takes place. See 53 * ``drivers/gpu/drm/xe/xe_guc_ads.c`` for reference. 54 * 55 * - GT workarounds: the list of these WAs is applied whenever these registers 56 * revert to their default values: on GPU reset, suspend/resume [1]_, etc. 57 * 58 * - Register whitelist: some workarounds need to be implemented in userspace, 59 * but need to touch privileged registers. The whitelist in the kernel 60 * instructs the hardware to allow the access to happen. From the kernel side, 61 * this is just a special case of a MMIO workaround (as we write the list of 62 * these to/be-whitelisted registers to some special HW registers). 63 * 64 * - Workaround batchbuffers: buffers that get executed automatically by the 65 * hardware on every HW context restore. These buffers are created and 66 * programmed in the default context so the hardware always go through those 67 * programming sequences when switching contexts. The support for workaround 68 * batchbuffers is enabled these hardware mechanisms: 69 * 70 * #. INDIRECT_CTX: A batchbuffer and an offset are provided in the default 71 * context, pointing the hardware to jump to that location when that offset 72 * is reached in the context restore. Workaround batchbuffer in the driver 73 * currently uses this mechanism for all platforms. 74 * 75 * #. BB_PER_CTX_PTR: A batchbuffer is provided in the default context, 76 * pointing the hardware to a buffer to continue executing after the 77 * engine registers are restored in a context restore sequence. This is 78 * currently not used in the driver. 79 * 80 * - Other/OOB: There are WAs that, due to their nature, cannot be applied from 81 * a central place. Those are peppered around the rest of the code, as needed. 82 * Workarounds related to the display IP are the main example. 83 * 84 * .. [1] Technically, some registers are powercontext saved & restored, so they 85 * survive a suspend/resume. In practice, writing them again is not too 86 * costly and simplifies things, so it's the approach taken in the driver. 87 * 88 * .. note:: 89 * Hardware workarounds in xe work the same way as in i915, with the 90 * difference of how they are maintained in the code. In xe it uses the 91 * xe_rtp infrastructure so the workarounds can be kept in tables, following 92 * a more declarative approach rather than procedural. 93 */ 94 95 #undef XE_REG_MCR 96 #define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1) 97 98 __diag_push(); 99 __diag_ignore_all("-Woverride-init", "Allow field overrides in table"); 100 101 static const struct xe_rtp_entry_sr gt_was[] = { 102 { XE_RTP_NAME("14011060649"), 103 XE_RTP_RULES(MEDIA_VERSION_RANGE(1200, 1255), 104 ENGINE_CLASS(VIDEO_DECODE), 105 FUNC(xe_rtp_match_even_instance)), 106 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 107 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 108 }, 109 { XE_RTP_NAME("14011059788"), 110 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), 111 XE_RTP_ACTIONS(SET(DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE)) 112 }, 113 { XE_RTP_NAME("14015795083"), 114 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1260)), 115 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE)) 116 }, 117 118 /* DG1 */ 119 120 { XE_RTP_NAME("1409420604"), 121 XE_RTP_RULES(PLATFORM(DG1)), 122 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE2, CPSSUNIT_CLKGATE_DIS)) 123 }, 124 { XE_RTP_NAME("1408615072"), 125 XE_RTP_RULES(PLATFORM(DG1)), 126 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE2_DIS)) 127 }, 128 129 /* DG2 */ 130 131 { XE_RTP_NAME("22010523718"), 132 XE_RTP_RULES(SUBPLATFORM(DG2, G10)), 133 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE, CG3DDISCFEG_CLKGATE_DIS)) 134 }, 135 { XE_RTP_NAME("14011006942"), 136 XE_RTP_RULES(SUBPLATFORM(DG2, G10)), 137 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE, DSS_ROUTER_CLKGATE_DIS)) 138 }, 139 { XE_RTP_NAME("14014830051"), 140 XE_RTP_RULES(PLATFORM(DG2)), 141 XE_RTP_ACTIONS(CLR(SARB_CHICKEN1, COMP_CKN_IN)) 142 }, 143 { XE_RTP_NAME("18018781329"), 144 XE_RTP_RULES(PLATFORM(DG2)), 145 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB), 146 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB), 147 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB), 148 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB)) 149 }, 150 { XE_RTP_NAME("1509235366"), 151 XE_RTP_RULES(PLATFORM(DG2)), 152 XE_RTP_ACTIONS(SET(XEHP_GAMCNTRL_CTRL, 153 INVALIDATION_BROADCAST_MODE_DIS | 154 GLOBAL_INVALIDATION_MODE)) 155 }, 156 157 /* PVC */ 158 159 { XE_RTP_NAME("18018781329"), 160 XE_RTP_RULES(PLATFORM(PVC)), 161 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB), 162 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB), 163 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB), 164 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB)) 165 }, 166 { XE_RTP_NAME("16016694945"), 167 XE_RTP_RULES(PLATFORM(PVC)), 168 XE_RTP_ACTIONS(SET(XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC)) 169 }, 170 171 /* Xe_LPG */ 172 173 { XE_RTP_NAME("14015795083"), 174 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), GRAPHICS_STEP(A0, B0)), 175 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE)) 176 }, 177 { XE_RTP_NAME("14018575942"), 178 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)), 179 XE_RTP_ACTIONS(SET(COMP_MOD_CTRL, FORCE_MISS_FTLB)) 180 }, 181 { XE_RTP_NAME("22016670082"), 182 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)), 183 XE_RTP_ACTIONS(SET(SQCNT1, ENFORCE_RAR)) 184 }, 185 186 /* Xe_LPM+ */ 187 188 { XE_RTP_NAME("16021867713"), 189 XE_RTP_RULES(MEDIA_VERSION(1300), 190 ENGINE_CLASS(VIDEO_DECODE)), 191 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 192 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 193 }, 194 { XE_RTP_NAME("22016670082"), 195 XE_RTP_RULES(MEDIA_VERSION(1300)), 196 XE_RTP_ACTIONS(SET(XELPMP_SQCNT1, ENFORCE_RAR)) 197 }, 198 199 /* Xe2_LPG */ 200 201 { XE_RTP_NAME("16020975621"), 202 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)), 203 XE_RTP_ACTIONS(SET(XEHP_SLICE_UNIT_LEVEL_CLKGATE, SBEUNIT_CLKGATE_DIS)) 204 }, 205 { XE_RTP_NAME("14018157293"), 206 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)), 207 XE_RTP_ACTIONS(SET(XEHPC_L3CLOS_MASK(0), ~0), 208 SET(XEHPC_L3CLOS_MASK(1), ~0), 209 SET(XEHPC_L3CLOS_MASK(2), ~0), 210 SET(XEHPC_L3CLOS_MASK(3), ~0)) 211 }, 212 213 /* Xe2_LPM */ 214 215 { XE_RTP_NAME("14017421178"), 216 XE_RTP_RULES(MEDIA_VERSION(2000), 217 ENGINE_CLASS(VIDEO_DECODE)), 218 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 219 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 220 }, 221 { XE_RTP_NAME("16021867713"), 222 XE_RTP_RULES(MEDIA_VERSION(2000), 223 ENGINE_CLASS(VIDEO_DECODE)), 224 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 225 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 226 }, 227 { XE_RTP_NAME("14019449301"), 228 XE_RTP_RULES(MEDIA_VERSION(2000), ENGINE_CLASS(VIDEO_DECODE)), 229 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)), 230 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 231 }, 232 233 /* Xe2_HPG */ 234 235 { XE_RTP_NAME("16025250150"), 236 XE_RTP_RULES(GRAPHICS_VERSION(2001)), 237 XE_RTP_ACTIONS(SET(LSN_VC_REG2, 238 LSN_LNI_WGT(1) | 239 LSN_LNE_WGT(1) | 240 LSN_DIM_X_WGT(1) | 241 LSN_DIM_Y_WGT(1) | 242 LSN_DIM_Z_WGT(1))) 243 }, 244 245 /* Xe2_HPM */ 246 247 { XE_RTP_NAME("16021867713"), 248 XE_RTP_RULES(MEDIA_VERSION(1301), 249 ENGINE_CLASS(VIDEO_DECODE)), 250 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 251 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 252 }, 253 { XE_RTP_NAME("14020316580"), 254 XE_RTP_RULES(MEDIA_VERSION(1301)), 255 XE_RTP_ACTIONS(CLR(POWERGATE_ENABLE, 256 VDN_HCP_POWERGATE_ENABLE(0) | 257 VDN_MFXVDENC_POWERGATE_ENABLE(0) | 258 VDN_HCP_POWERGATE_ENABLE(2) | 259 VDN_MFXVDENC_POWERGATE_ENABLE(2))), 260 }, 261 { XE_RTP_NAME("14019449301"), 262 XE_RTP_RULES(MEDIA_VERSION(1301), ENGINE_CLASS(VIDEO_DECODE)), 263 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)), 264 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 265 }, 266 267 /* Xe3_LPG */ 268 269 { XE_RTP_NAME("14021871409"), 270 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0)), 271 XE_RTP_ACTIONS(SET(UNSLCGCTL9454, LSCFE_CLKGATE_DIS)) 272 }, 273 274 /* Xe3_LPM */ 275 276 { XE_RTP_NAME("16021867713"), 277 XE_RTP_RULES(MEDIA_VERSION(3000), 278 ENGINE_CLASS(VIDEO_DECODE)), 279 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 280 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 281 }, 282 { XE_RTP_NAME("16021865536"), 283 XE_RTP_RULES(MEDIA_VERSION(3000), 284 ENGINE_CLASS(VIDEO_DECODE)), 285 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 286 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 287 }, 288 { XE_RTP_NAME("14021486841"), 289 XE_RTP_RULES(MEDIA_VERSION(3000), MEDIA_STEP(A0, B0), 290 ENGINE_CLASS(VIDEO_DECODE)), 291 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), RAMDFTUNIT_CLKGATE_DIS)), 292 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 293 }, 294 }; 295 296 static const struct xe_rtp_entry_sr engine_was[] = { 297 { XE_RTP_NAME("22010931296, 18011464164, 14010919138"), 298 XE_RTP_RULES(GRAPHICS_VERSION(1200), ENGINE_CLASS(RENDER)), 299 XE_RTP_ACTIONS(SET(FF_THREAD_MODE(RENDER_RING_BASE), 300 FF_TESSELATION_DOP_GATE_DISABLE)) 301 }, 302 { XE_RTP_NAME("1409804808"), 303 XE_RTP_RULES(GRAPHICS_VERSION(1200), 304 ENGINE_CLASS(RENDER), 305 IS_INTEGRATED), 306 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, PUSH_CONST_DEREF_HOLD_DIS)) 307 }, 308 { XE_RTP_NAME("14010229206, 1409085225"), 309 XE_RTP_RULES(GRAPHICS_VERSION(1200), 310 ENGINE_CLASS(RENDER), 311 IS_INTEGRATED), 312 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH)) 313 }, 314 { XE_RTP_NAME("1606931601"), 315 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 316 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_EARLY_READ)) 317 }, 318 { XE_RTP_NAME("14010826681, 1606700617, 22010271021, 18019627453"), 319 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1255), ENGINE_CLASS(RENDER)), 320 XE_RTP_ACTIONS(SET(CS_DEBUG_MODE1(RENDER_RING_BASE), 321 FF_DOP_CLOCK_GATE_DISABLE)) 322 }, 323 { XE_RTP_NAME("1406941453"), 324 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 325 XE_RTP_ACTIONS(SET(SAMPLER_MODE, ENABLE_SMALLPL)) 326 }, 327 { XE_RTP_NAME("FtrPerCtxtPreemptionGranularityControl"), 328 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1250), ENGINE_CLASS(RENDER)), 329 XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN1(RENDER_RING_BASE), 330 FFSC_PERCTX_PREEMPT_CTRL)) 331 }, 332 333 /* TGL */ 334 335 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"), 336 XE_RTP_RULES(PLATFORM(TIGERLAKE), ENGINE_CLASS(RENDER)), 337 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE), 338 WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 339 RC_SEMA_IDLE_MSG_DISABLE)) 340 }, 341 342 /* RKL */ 343 344 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"), 345 XE_RTP_RULES(PLATFORM(ROCKETLAKE), ENGINE_CLASS(RENDER)), 346 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE), 347 WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 348 RC_SEMA_IDLE_MSG_DISABLE)) 349 }, 350 351 /* ADL-P */ 352 353 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"), 354 XE_RTP_RULES(PLATFORM(ALDERLAKE_P), ENGINE_CLASS(RENDER)), 355 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE), 356 WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 357 RC_SEMA_IDLE_MSG_DISABLE)) 358 }, 359 360 /* DG2 */ 361 362 { XE_RTP_NAME("22013037850"), 363 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 364 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, 365 DISABLE_128B_EVICTION_COMMAND_UDW)) 366 }, 367 { XE_RTP_NAME("22014226127"), 368 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 369 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE)) 370 }, 371 { XE_RTP_NAME("18017747507"), 372 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 373 XE_RTP_ACTIONS(SET(VFG_PREEMPTION_CHICKEN, 374 POLYGON_TRIFAN_LINELOOP_DISABLE)) 375 }, 376 { XE_RTP_NAME("22012826095, 22013059131"), 377 XE_RTP_RULES(SUBPLATFORM(DG2, G11), 378 FUNC(xe_rtp_match_first_render_or_compute)), 379 XE_RTP_ACTIONS(FIELD_SET(LSC_CHICKEN_BIT_0_UDW, 380 MAXREQS_PER_BANK, 381 REG_FIELD_PREP(MAXREQS_PER_BANK, 2))) 382 }, 383 { XE_RTP_NAME("22013059131"), 384 XE_RTP_RULES(SUBPLATFORM(DG2, G11), 385 FUNC(xe_rtp_match_first_render_or_compute)), 386 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, FORCE_1_SUB_MESSAGE_PER_FRAGMENT)) 387 }, 388 { XE_RTP_NAME("14015227452"), 389 XE_RTP_RULES(PLATFORM(DG2), 390 FUNC(xe_rtp_match_first_render_or_compute)), 391 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE)) 392 }, 393 { XE_RTP_NAME("18028616096"), 394 XE_RTP_RULES(PLATFORM(DG2), 395 FUNC(xe_rtp_match_first_render_or_compute)), 396 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3)) 397 }, 398 { XE_RTP_NAME("22015475538"), 399 XE_RTP_RULES(PLATFORM(DG2), 400 FUNC(xe_rtp_match_first_render_or_compute)), 401 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8)) 402 }, 403 { XE_RTP_NAME("22012654132"), 404 XE_RTP_RULES(SUBPLATFORM(DG2, G11), 405 FUNC(xe_rtp_match_first_render_or_compute)), 406 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, ENABLE_PREFETCH_INTO_IC, 407 /* 408 * Register can't be read back for verification on 409 * DG2 due to Wa_14012342262 410 */ 411 .read_mask = 0)) 412 }, 413 { XE_RTP_NAME("1509727124"), 414 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 415 XE_RTP_ACTIONS(SET(SAMPLER_MODE, SC_DISABLE_POWER_OPTIMIZATION_EBB)) 416 }, 417 { XE_RTP_NAME("22012856258"), 418 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 419 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_READ_SUPPRESSION)) 420 }, 421 { XE_RTP_NAME("22010960976, 14013347512"), 422 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 423 XE_RTP_ACTIONS(CLR(XEHP_HDC_CHICKEN0, 424 LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK)) 425 }, 426 { XE_RTP_NAME("14015150844"), 427 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 428 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES, 429 XE_RTP_NOCHECK)) 430 }, 431 432 /* PVC */ 433 434 { XE_RTP_NAME("22014226127"), 435 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)), 436 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE)) 437 }, 438 { XE_RTP_NAME("14015227452"), 439 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)), 440 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE)) 441 }, 442 { XE_RTP_NAME("18020744125"), 443 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute), 444 ENGINE_CLASS(COMPUTE)), 445 XE_RTP_ACTIONS(SET(RING_HWSTAM(RENDER_RING_BASE), ~0)) 446 }, 447 { XE_RTP_NAME("14014999345"), 448 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COMPUTE), 449 GRAPHICS_STEP(B0, C0)), 450 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, DISABLE_ECC)) 451 }, 452 453 /* Xe_LPG */ 454 455 { XE_RTP_NAME("14017856879"), 456 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), 457 FUNC(xe_rtp_match_first_render_or_compute)), 458 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, DIS_FIX_EOT1_FLUSH)) 459 }, 460 { XE_RTP_NAME("14015150844"), 461 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), 462 FUNC(xe_rtp_match_first_render_or_compute)), 463 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES, 464 XE_RTP_NOCHECK)) 465 }, 466 { XE_RTP_NAME("14020495402"), 467 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), 468 FUNC(xe_rtp_match_first_render_or_compute)), 469 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_TDL_SVHS_GATING)) 470 }, 471 472 /* Xe2_LPG */ 473 474 { XE_RTP_NAME("18032247524"), 475 XE_RTP_RULES(GRAPHICS_VERSION(2004), 476 FUNC(xe_rtp_match_first_render_or_compute)), 477 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE)) 478 }, 479 { XE_RTP_NAME("16018712365"), 480 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 481 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS)) 482 }, 483 { XE_RTP_NAME("14018957109"), 484 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 485 FUNC(xe_rtp_match_first_render_or_compute)), 486 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN5, DISABLE_SAMPLE_G_PERFORMANCE)) 487 }, 488 { XE_RTP_NAME("14020338487"), 489 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 490 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS)) 491 }, 492 { XE_RTP_NAME("18034896535, 16021540221"), /* 16021540221: GRAPHICS_STEP(A0, B0) */ 493 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), 494 FUNC(xe_rtp_match_first_render_or_compute)), 495 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH)) 496 }, 497 { XE_RTP_NAME("14019322943"), 498 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 499 FUNC(xe_rtp_match_first_render_or_compute)), 500 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, TGM_WRITE_EOM_FORCE)) 501 }, 502 { XE_RTP_NAME("14018471104"), 503 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 504 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL)) 505 }, 506 /* 507 * These two workarounds are the same, just applying to different 508 * engines. Although Wa_18032095049 (for the RCS) isn't required on 509 * all steppings, disabling these reports has no impact for our 510 * driver or the GuC, so we go ahead and treat it the same as 511 * Wa_16021639441 which does apply to all steppings. 512 */ 513 { XE_RTP_NAME("18032095049, 16021639441"), 514 XE_RTP_RULES(GRAPHICS_VERSION(2004)), 515 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), 516 GHWSP_CSB_REPORT_DIS | 517 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, 518 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 519 }, 520 { XE_RTP_NAME("16018610683"), 521 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 522 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, SLM_WMTP_RESTORE)) 523 }, 524 { XE_RTP_NAME("14021402888"), 525 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 526 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE)) 527 }, 528 529 /* Xe2_HPG */ 530 531 { XE_RTP_NAME("16018712365"), 532 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 533 FUNC(xe_rtp_match_first_render_or_compute)), 534 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS)) 535 }, 536 { XE_RTP_NAME("16018737384"), 537 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED), 538 FUNC(xe_rtp_match_first_render_or_compute)), 539 XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS)) 540 }, 541 { XE_RTP_NAME("14019988906"), 542 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 543 FUNC(xe_rtp_match_first_render_or_compute)), 544 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD)) 545 }, 546 { XE_RTP_NAME("14019877138"), 547 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 548 FUNC(xe_rtp_match_first_render_or_compute)), 549 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 550 }, 551 { XE_RTP_NAME("14020338487"), 552 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 553 FUNC(xe_rtp_match_first_render_or_compute)), 554 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS)) 555 }, 556 { XE_RTP_NAME("18032247524"), 557 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 558 FUNC(xe_rtp_match_first_render_or_compute)), 559 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE)) 560 }, 561 { XE_RTP_NAME("14018471104"), 562 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 563 FUNC(xe_rtp_match_first_render_or_compute)), 564 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL)) 565 }, 566 /* 567 * Although this workaround isn't required for the RCS, disabling these 568 * reports has no impact for our driver or the GuC, so we go ahead and 569 * apply this to all engines for simplicity. 570 */ 571 { XE_RTP_NAME("16021639441"), 572 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002)), 573 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), 574 GHWSP_CSB_REPORT_DIS | 575 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, 576 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 577 }, 578 { XE_RTP_NAME("14019811474"), 579 XE_RTP_RULES(GRAPHICS_VERSION(2001), 580 FUNC(xe_rtp_match_first_render_or_compute)), 581 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, WR_REQ_CHAINING_DIS)) 582 }, 583 { XE_RTP_NAME("14021402888"), 584 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), 585 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE)) 586 }, 587 { XE_RTP_NAME("14021821874, 14022954250"), 588 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 589 FUNC(xe_rtp_match_first_render_or_compute)), 590 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, STK_ID_RESTRICT)) 591 }, 592 593 /* Xe2_LPM */ 594 595 { XE_RTP_NAME("16021639441"), 596 XE_RTP_RULES(MEDIA_VERSION(2000)), 597 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), 598 GHWSP_CSB_REPORT_DIS | 599 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, 600 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 601 }, 602 603 /* Xe2_HPM */ 604 605 { XE_RTP_NAME("16021639441"), 606 XE_RTP_RULES(MEDIA_VERSION(1301)), 607 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), 608 GHWSP_CSB_REPORT_DIS | 609 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, 610 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 611 }, 612 613 /* Xe3_LPG */ 614 615 { XE_RTP_NAME("14021402888"), 616 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), 617 FUNC(xe_rtp_match_first_render_or_compute)), 618 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE)) 619 }, 620 { XE_RTP_NAME("18034896535"), 621 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0), 622 FUNC(xe_rtp_match_first_render_or_compute)), 623 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH)) 624 }, 625 { XE_RTP_NAME("16024792527"), 626 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0), 627 FUNC(xe_rtp_match_first_render_or_compute)), 628 XE_RTP_ACTIONS(FIELD_SET(SAMPLER_MODE, SMP_WAIT_FETCH_MERGING_COUNTER, 629 SMP_FORCE_128B_OVERFETCH)) 630 }, 631 { XE_RTP_NAME("14023061436"), 632 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), 633 FUNC(xe_rtp_match_first_render_or_compute)), 634 XE_RTP_ACTIONS(SET(TDL_CHICKEN, QID_WAIT_FOR_THREAD_NOT_RUN_DISABLE)) 635 }, 636 { XE_RTP_NAME("13012615864"), 637 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), 638 FUNC(xe_rtp_match_first_render_or_compute)), 639 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS)) 640 }, 641 { XE_RTP_NAME("16023105232"), 642 XE_RTP_RULES(MEDIA_VERSION_RANGE(1301, 3000), OR, 643 GRAPHICS_VERSION_RANGE(2001, 3001)), 644 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(0), RC_SEMA_IDLE_MSG_DISABLE, 645 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 646 }, 647 }; 648 649 static const struct xe_rtp_entry_sr lrc_was[] = { 650 { XE_RTP_NAME("16011163337"), 651 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 652 /* read verification is ignored due to 1608008084. */ 653 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2, 654 FF_MODE2_GS_TIMER_MASK, 655 FF_MODE2_GS_TIMER_224)) 656 }, 657 { XE_RTP_NAME("1604555607"), 658 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 659 /* read verification is ignored due to 1608008084. */ 660 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2, 661 FF_MODE2_TDS_TIMER_MASK, 662 FF_MODE2_TDS_TIMER_128)) 663 }, 664 { XE_RTP_NAME("1409342910, 14010698770, 14010443199, 1408979724, 1409178076, 1409207793, 1409217633, 1409252684, 1409347922, 1409142259"), 665 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), 666 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN3, 667 DISABLE_CPS_AWARE_COLOR_PIPE)) 668 }, 669 { XE_RTP_NAME("WaDisableGPGPUMidThreadPreemption"), 670 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), 671 XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(RENDER_RING_BASE), 672 PREEMPT_GPGPU_LEVEL_MASK, 673 PREEMPT_GPGPU_THREAD_GROUP_LEVEL)) 674 }, 675 { XE_RTP_NAME("1806527549"), 676 XE_RTP_RULES(GRAPHICS_VERSION(1200)), 677 XE_RTP_ACTIONS(SET(HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE)) 678 }, 679 { XE_RTP_NAME("1606376872"), 680 XE_RTP_RULES(GRAPHICS_VERSION(1200)), 681 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC)) 682 }, 683 684 /* DG1 */ 685 686 { XE_RTP_NAME("1409044764"), 687 XE_RTP_RULES(PLATFORM(DG1)), 688 XE_RTP_ACTIONS(CLR(COMMON_SLICE_CHICKEN3, 689 DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN)) 690 }, 691 { XE_RTP_NAME("22010493298"), 692 XE_RTP_RULES(PLATFORM(DG1)), 693 XE_RTP_ACTIONS(SET(HIZ_CHICKEN, 694 DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE)) 695 }, 696 697 /* DG2 */ 698 699 { XE_RTP_NAME("16013271637"), 700 XE_RTP_RULES(PLATFORM(DG2)), 701 XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1, 702 MSC_MSAA_REODER_BUF_BYPASS_DISABLE)) 703 }, 704 { XE_RTP_NAME("14014947963"), 705 XE_RTP_RULES(PLATFORM(DG2)), 706 XE_RTP_ACTIONS(FIELD_SET(VF_PREEMPTION, 707 PREEMPTION_VERTEX_COUNT, 708 0x4000)) 709 }, 710 { XE_RTP_NAME("18018764978"), 711 XE_RTP_RULES(PLATFORM(DG2)), 712 XE_RTP_ACTIONS(SET(XEHP_PSS_MODE2, 713 SCOREBOARD_STALL_FLUSH_CONTROL)) 714 }, 715 { XE_RTP_NAME("18019271663"), 716 XE_RTP_RULES(PLATFORM(DG2)), 717 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE)) 718 }, 719 { XE_RTP_NAME("14019877138"), 720 XE_RTP_RULES(PLATFORM(DG2)), 721 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 722 }, 723 724 /* PVC */ 725 726 { XE_RTP_NAME("16017236439"), 727 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COPY), 728 FUNC(xe_rtp_match_even_instance)), 729 XE_RTP_ACTIONS(SET(BCS_SWCTRL(0), 730 BCS_SWCTRL_DISABLE_256B, 731 XE_RTP_ACTION_FLAG(ENGINE_BASE))), 732 }, 733 734 /* Xe_LPG */ 735 736 { XE_RTP_NAME("18019271663"), 737 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)), 738 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE)) 739 }, 740 { XE_RTP_NAME("14019877138"), 741 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), ENGINE_CLASS(RENDER)), 742 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 743 }, 744 745 /* Xe2_LPG */ 746 747 { XE_RTP_NAME("16020518922"), 748 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 749 ENGINE_CLASS(RENDER)), 750 XE_RTP_ACTIONS(SET(FF_MODE, 751 DIS_TE_AUTOSTRIP | 752 DIS_MESH_PARTIAL_AUTOSTRIP | 753 DIS_MESH_AUTOSTRIP), 754 SET(VFLSKPD, 755 DIS_PARTIAL_AUTOSTRIP | 756 DIS_AUTOSTRIP)) 757 }, 758 { XE_RTP_NAME("14019386621"), 759 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 760 XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE)) 761 }, 762 { XE_RTP_NAME("14019877138"), 763 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 764 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 765 }, 766 { XE_RTP_NAME("14020013138"), 767 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 768 ENGINE_CLASS(RENDER)), 769 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS)) 770 }, 771 { XE_RTP_NAME("14019988906"), 772 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 773 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD)) 774 }, 775 { XE_RTP_NAME("16020183090"), 776 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 777 ENGINE_CLASS(RENDER)), 778 XE_RTP_ACTIONS(SET(INSTPM(RENDER_RING_BASE), ENABLE_SEMAPHORE_POLL_BIT)) 779 }, 780 { XE_RTP_NAME("18033852989"), 781 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 782 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST)) 783 }, 784 { XE_RTP_NAME("14021567978"), 785 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED), 786 ENGINE_CLASS(RENDER)), 787 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_2, TBIMR_FAST_CLIP)) 788 }, 789 { XE_RTP_NAME("14020756599"), 790 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER), OR, 791 MEDIA_VERSION_ANY_GT(2000), ENGINE_CLASS(RENDER)), 792 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS)) 793 }, 794 { XE_RTP_NAME("14021490052"), 795 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 796 XE_RTP_ACTIONS(SET(FF_MODE, 797 DIS_MESH_PARTIAL_AUTOSTRIP | 798 DIS_MESH_AUTOSTRIP), 799 SET(VFLSKPD, 800 DIS_PARTIAL_AUTOSTRIP | 801 DIS_AUTOSTRIP)) 802 }, 803 { XE_RTP_NAME("15016589081"), 804 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 805 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX)) 806 }, 807 808 /* Xe2_HPG */ 809 { XE_RTP_NAME("15010599737"), 810 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 811 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN)) 812 }, 813 { XE_RTP_NAME("14019386621"), 814 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), 815 XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE)) 816 }, 817 { XE_RTP_NAME("14020756599"), 818 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 819 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS)) 820 }, 821 { XE_RTP_NAME("14021490052"), 822 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 823 XE_RTP_ACTIONS(SET(FF_MODE, 824 DIS_MESH_PARTIAL_AUTOSTRIP | 825 DIS_MESH_AUTOSTRIP), 826 SET(VFLSKPD, 827 DIS_PARTIAL_AUTOSTRIP | 828 DIS_AUTOSTRIP)) 829 }, 830 { XE_RTP_NAME("15016589081"), 831 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), 832 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX)) 833 }, 834 { XE_RTP_NAME("22021007897"), 835 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), 836 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE)) 837 }, 838 { XE_RTP_NAME("18033852989"), 839 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 840 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST)) 841 }, 842 843 /* Xe3_LPG */ 844 { XE_RTP_NAME("14021490052"), 845 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0), 846 ENGINE_CLASS(RENDER)), 847 XE_RTP_ACTIONS(SET(FF_MODE, 848 DIS_MESH_PARTIAL_AUTOSTRIP | 849 DIS_MESH_AUTOSTRIP), 850 SET(VFLSKPD, 851 DIS_PARTIAL_AUTOSTRIP | 852 DIS_AUTOSTRIP)) 853 }, 854 }; 855 856 static __maybe_unused const struct xe_rtp_entry oob_was[] = { 857 #include <generated/xe_wa_oob.c> 858 {} 859 }; 860 861 static_assert(ARRAY_SIZE(oob_was) - 1 == _XE_WA_OOB_COUNT); 862 863 __diag_pop(); 864 865 /** 866 * xe_wa_process_oob - process OOB workaround table 867 * @gt: GT instance to process workarounds for 868 * 869 * Process OOB workaround table for this platform, marking in @gt the 870 * workarounds that are active. 871 */ 872 void xe_wa_process_oob(struct xe_gt *gt) 873 { 874 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt); 875 876 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.oob, 877 ARRAY_SIZE(oob_was)); 878 gt->wa_active.oob_initialized = true; 879 xe_rtp_process(&ctx, oob_was); 880 } 881 882 /** 883 * xe_wa_process_gt - process GT workaround table 884 * @gt: GT instance to process workarounds for 885 * 886 * Process GT workaround table for this platform, saving in @gt all the 887 * workarounds that need to be applied at the GT level. 888 */ 889 void xe_wa_process_gt(struct xe_gt *gt) 890 { 891 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt); 892 893 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.gt, 894 ARRAY_SIZE(gt_was)); 895 xe_rtp_process_to_sr(&ctx, gt_was, ARRAY_SIZE(gt_was), >->reg_sr); 896 } 897 EXPORT_SYMBOL_IF_KUNIT(xe_wa_process_gt); 898 899 /** 900 * xe_wa_process_engine - process engine workaround table 901 * @hwe: engine instance to process workarounds for 902 * 903 * Process engine workaround table for this platform, saving in @hwe all the 904 * workarounds that need to be applied at the engine level that match this 905 * engine. 906 */ 907 void xe_wa_process_engine(struct xe_hw_engine *hwe) 908 { 909 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); 910 911 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.engine, 912 ARRAY_SIZE(engine_was)); 913 xe_rtp_process_to_sr(&ctx, engine_was, ARRAY_SIZE(engine_was), &hwe->reg_sr); 914 } 915 916 /** 917 * xe_wa_process_lrc - process context workaround table 918 * @hwe: engine instance to process workarounds for 919 * 920 * Process context workaround table for this platform, saving in @hwe all the 921 * workarounds that need to be applied on context restore. These are workarounds 922 * touching registers that are part of the HW context image. 923 */ 924 void xe_wa_process_lrc(struct xe_hw_engine *hwe) 925 { 926 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); 927 928 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.lrc, 929 ARRAY_SIZE(lrc_was)); 930 xe_rtp_process_to_sr(&ctx, lrc_was, ARRAY_SIZE(lrc_was), &hwe->reg_lrc); 931 } 932 933 /** 934 * xe_wa_init - initialize gt with workaround bookkeeping 935 * @gt: GT instance to initialize 936 * 937 * Returns 0 for success, negative error code otherwise. 938 */ 939 int xe_wa_init(struct xe_gt *gt) 940 { 941 struct xe_device *xe = gt_to_xe(gt); 942 size_t n_oob, n_lrc, n_engine, n_gt, total; 943 unsigned long *p; 944 945 n_gt = BITS_TO_LONGS(ARRAY_SIZE(gt_was)); 946 n_engine = BITS_TO_LONGS(ARRAY_SIZE(engine_was)); 947 n_lrc = BITS_TO_LONGS(ARRAY_SIZE(lrc_was)); 948 n_oob = BITS_TO_LONGS(ARRAY_SIZE(oob_was)); 949 total = n_gt + n_engine + n_lrc + n_oob; 950 951 p = drmm_kzalloc(&xe->drm, sizeof(*p) * total, GFP_KERNEL); 952 if (!p) 953 return -ENOMEM; 954 955 gt->wa_active.gt = p; 956 p += n_gt; 957 gt->wa_active.engine = p; 958 p += n_engine; 959 gt->wa_active.lrc = p; 960 p += n_lrc; 961 gt->wa_active.oob = p; 962 963 return 0; 964 } 965 ALLOW_ERROR_INJECTION(xe_wa_init, ERRNO); /* See xe_pci_probe() */ 966 967 void xe_wa_dump(struct xe_gt *gt, struct drm_printer *p) 968 { 969 size_t idx; 970 971 drm_printf(p, "GT Workarounds\n"); 972 for_each_set_bit(idx, gt->wa_active.gt, ARRAY_SIZE(gt_was)) 973 drm_printf_indent(p, 1, "%s\n", gt_was[idx].name); 974 975 drm_printf(p, "\nEngine Workarounds\n"); 976 for_each_set_bit(idx, gt->wa_active.engine, ARRAY_SIZE(engine_was)) 977 drm_printf_indent(p, 1, "%s\n", engine_was[idx].name); 978 979 drm_printf(p, "\nLRC Workarounds\n"); 980 for_each_set_bit(idx, gt->wa_active.lrc, ARRAY_SIZE(lrc_was)) 981 drm_printf_indent(p, 1, "%s\n", lrc_was[idx].name); 982 983 drm_printf(p, "\nOOB Workarounds\n"); 984 for_each_set_bit(idx, gt->wa_active.oob, ARRAY_SIZE(oob_was)) 985 if (oob_was[idx].name) 986 drm_printf_indent(p, 1, "%s\n", oob_was[idx].name); 987 } 988 989 /* 990 * Apply tile (non-GT, non-display) workarounds. Think very carefully before 991 * adding anything to this function; most workarounds should be implemented 992 * elsewhere. The programming here is primarily for sgunit/soc workarounds, 993 * which are relatively rare. Since the registers these workarounds target are 994 * outside the GT, they should only need to be applied once at device 995 * probe/resume; they will not lose their values on any kind of GT or engine 996 * reset. 997 * 998 * TODO: We may want to move this over to xe_rtp in the future once we have 999 * enough workarounds to justify the work. 1000 */ 1001 void xe_wa_apply_tile_workarounds(struct xe_tile *tile) 1002 { 1003 struct xe_mmio *mmio = &tile->mmio; 1004 1005 if (IS_SRIOV_VF(tile->xe)) 1006 return; 1007 1008 if (XE_WA(tile->primary_gt, 22010954014)) 1009 xe_mmio_rmw32(mmio, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS); 1010 } 1011