1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_wa.h" 7 8 #include <drm/drm_managed.h> 9 #include <kunit/visibility.h> 10 #include <linux/compiler_types.h> 11 #include <linux/fault-inject.h> 12 13 #include <generated/xe_device_wa_oob.h> 14 #include <generated/xe_wa_oob.h> 15 16 #include "regs/xe_engine_regs.h" 17 #include "regs/xe_gt_regs.h" 18 #include "regs/xe_guc_regs.h" 19 #include "regs/xe_regs.h" 20 #include "xe_device_types.h" 21 #include "xe_force_wake.h" 22 #include "xe_gt_types.h" 23 #include "xe_hw_engine_types.h" 24 #include "xe_mmio.h" 25 #include "xe_platform_types.h" 26 #include "xe_rtp.h" 27 #include "xe_sriov.h" 28 #include "xe_step.h" 29 30 /** 31 * DOC: Hardware workarounds 32 * 33 * Hardware workarounds are register programming documented to be executed in 34 * the driver that fall outside of the normal programming sequences for a 35 * platform. There are some basic categories of workarounds, depending on 36 * how/when they are applied: 37 * 38 * - LRC workarounds: workarounds that touch registers that are 39 * saved/restored to/from the HW context image. The list is emitted (via Load 40 * Register Immediate commands) once when initializing the device and saved in 41 * the default context. That default context is then used on every context 42 * creation to have a "primed golden context", i.e. a context image that 43 * already contains the changes needed to all the registers. See 44 * drivers/gpu/drm/xe/xe_lrc.c for default context handling. 45 * 46 * - Engine workarounds: the list of these WAs is applied whenever the specific 47 * engine is reset. It's also possible that a set of engine classes share a 48 * common power domain and they are reset together. This happens on some 49 * platforms with render and compute engines. In this case (at least) one of 50 * them need to keeep the workaround programming: the approach taken in the 51 * driver is to tie those workarounds to the first compute/render engine that 52 * is registered. When executing with GuC submission, engine resets are 53 * outside of kernel driver control, hence the list of registers involved is 54 * written once, on engine initialization, and then passed to GuC, that 55 * saves/restores their values before/after the reset takes place. See 56 * drivers/gpu/drm/xe/xe_guc_ads.c for reference. 57 * 58 * - GT workarounds: the list of these WAs is applied whenever these registers 59 * revert to their default values: on GPU reset, suspend/resume [1]_, etc. 60 * 61 * - Register whitelist: some workarounds need to be implemented in userspace, 62 * but need to touch privileged registers. The whitelist in the kernel 63 * instructs the hardware to allow the access to happen. From the kernel side, 64 * this is just a special case of a MMIO workaround (as we write the list of 65 * these to/be-whitelisted registers to some special HW registers). 66 * 67 * - Workaround batchbuffers: buffers that get executed automatically by the 68 * hardware on every HW context restore. These buffers are created and 69 * programmed in the default context so the hardware always go through those 70 * programming sequences when switching contexts. The support for workaround 71 * batchbuffers is enabled via these hardware mechanisms: 72 * 73 * #. INDIRECT_CTX (also known as **mid context restore bb**): A batchbuffer 74 * and an offset are provided in the default context, pointing the hardware 75 * to jump to that location when that offset is reached in the context 76 * restore. When a context is being restored, this is executed after the 77 * ring context, in the middle (or beginning) of the engine context image. 78 * 79 * #. BB_PER_CTX_PTR (also known as **post context restore bb**): A 80 * batchbuffer is provided in the default context, pointing the hardware to 81 * a buffer to continue executing after the engine registers are restored 82 * in a context restore sequence. 83 * 84 * Below is the timeline for a context restore sequence: 85 * 86 * .. code:: 87 * 88 * INDIRECT_CTX_OFFSET 89 * |----------->| 90 * .------------.------------.-------------.------------.--------------.-----------. 91 * |Ring | Engine | Mid-context | Engine | Post-context | Ring | 92 * |Restore | Restore (1)| BB Restore | Restore (2)| BB Restore | Execution | 93 * `------------'------------'-------------'------------'--------------'-----------' 94 * 95 * - Other/OOB: There are WAs that, due to their nature, cannot be applied from 96 * a central place. Those are peppered around the rest of the code, as needed. 97 * There's a central place to control which workarounds are enabled: 98 * drivers/gpu/drm/xe/xe_wa_oob.rules for GT workarounds and 99 * drivers/gpu/drm/xe/xe_device_wa_oob.rules for device/SoC workarounds. 100 * These files only record which workarounds are enabled: during early device 101 * initialization those rules are evaluated and recorded by the driver. Then 102 * later the driver checks with ``XE_GT_WA()`` and ``XE_DEVICE_WA()`` to 103 * implement them. 104 * 105 * .. [1] Technically, some registers are powercontext saved & restored, so they 106 * survive a suspend/resume. In practice, writing them again is not too 107 * costly and simplifies things, so it's the approach taken in the driver. 108 * 109 * .. note:: 110 * Hardware workarounds in xe work the same way as in i915, with the 111 * difference of how they are maintained in the code. In xe it uses the 112 * xe_rtp infrastructure so the workarounds can be kept in tables, following 113 * a more declarative approach rather than procedural. 114 */ 115 116 #undef XE_REG_MCR 117 #define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1) 118 119 __diag_push(); 120 __diag_ignore_all("-Woverride-init", "Allow field overrides in table"); 121 122 static const struct xe_rtp_entry_sr gt_was[] = { 123 { XE_RTP_NAME("14011060649"), 124 XE_RTP_RULES(MEDIA_VERSION_RANGE(1200, 1255), 125 ENGINE_CLASS(VIDEO_DECODE), 126 FUNC(xe_rtp_match_even_instance)), 127 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 128 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 129 }, 130 { XE_RTP_NAME("14011059788"), 131 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), 132 XE_RTP_ACTIONS(SET(DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE)) 133 }, 134 { XE_RTP_NAME("14015795083"), 135 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1260)), 136 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE)) 137 }, 138 139 /* DG1 */ 140 141 { XE_RTP_NAME("1409420604"), 142 XE_RTP_RULES(PLATFORM(DG1)), 143 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE2, CPSSUNIT_CLKGATE_DIS)) 144 }, 145 { XE_RTP_NAME("1408615072"), 146 XE_RTP_RULES(PLATFORM(DG1)), 147 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE2_DIS)) 148 }, 149 150 /* DG2 */ 151 152 { XE_RTP_NAME("22010523718"), 153 XE_RTP_RULES(SUBPLATFORM(DG2, G10)), 154 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE, CG3DDISCFEG_CLKGATE_DIS)) 155 }, 156 { XE_RTP_NAME("14011006942"), 157 XE_RTP_RULES(SUBPLATFORM(DG2, G10)), 158 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE, DSS_ROUTER_CLKGATE_DIS)) 159 }, 160 { XE_RTP_NAME("14014830051"), 161 XE_RTP_RULES(PLATFORM(DG2)), 162 XE_RTP_ACTIONS(CLR(SARB_CHICKEN1, COMP_CKN_IN)) 163 }, 164 { XE_RTP_NAME("18018781329"), 165 XE_RTP_RULES(PLATFORM(DG2)), 166 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB), 167 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB), 168 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB), 169 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB)) 170 }, 171 { XE_RTP_NAME("1509235366"), 172 XE_RTP_RULES(PLATFORM(DG2)), 173 XE_RTP_ACTIONS(SET(XEHP_GAMCNTRL_CTRL, 174 INVALIDATION_BROADCAST_MODE_DIS | 175 GLOBAL_INVALIDATION_MODE)) 176 }, 177 178 /* PVC */ 179 180 { XE_RTP_NAME("18018781329"), 181 XE_RTP_RULES(PLATFORM(PVC)), 182 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB), 183 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB), 184 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB), 185 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB)) 186 }, 187 { XE_RTP_NAME("16016694945"), 188 XE_RTP_RULES(PLATFORM(PVC)), 189 XE_RTP_ACTIONS(SET(XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC)) 190 }, 191 192 /* Xe_LPG */ 193 194 { XE_RTP_NAME("14015795083"), 195 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), GRAPHICS_STEP(A0, B0)), 196 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE)) 197 }, 198 { XE_RTP_NAME("14018575942"), 199 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)), 200 XE_RTP_ACTIONS(SET(COMP_MOD_CTRL, FORCE_MISS_FTLB)) 201 }, 202 { XE_RTP_NAME("22016670082"), 203 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)), 204 XE_RTP_ACTIONS(SET(SQCNT1, ENFORCE_RAR)) 205 }, 206 207 /* Xe_LPM+ */ 208 209 { XE_RTP_NAME("16021867713"), 210 XE_RTP_RULES(MEDIA_VERSION(1300), 211 ENGINE_CLASS(VIDEO_DECODE)), 212 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 213 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 214 }, 215 { XE_RTP_NAME("22016670082"), 216 XE_RTP_RULES(MEDIA_VERSION(1300)), 217 XE_RTP_ACTIONS(SET(XELPMP_SQCNT1, ENFORCE_RAR)) 218 }, 219 220 /* Xe2_LPM */ 221 222 { XE_RTP_NAME("14017421178"), 223 XE_RTP_RULES(MEDIA_VERSION(2000), 224 ENGINE_CLASS(VIDEO_DECODE)), 225 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 226 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 227 }, 228 { XE_RTP_NAME("16021867713"), 229 XE_RTP_RULES(MEDIA_VERSION(2000), 230 ENGINE_CLASS(VIDEO_DECODE)), 231 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 232 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 233 }, 234 { XE_RTP_NAME("14019449301"), 235 XE_RTP_RULES(MEDIA_VERSION(2000), ENGINE_CLASS(VIDEO_DECODE)), 236 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)), 237 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 238 }, 239 240 /* Xe2_HPG */ 241 242 { XE_RTP_NAME("16025250150"), 243 XE_RTP_RULES(GRAPHICS_VERSION(2001)), 244 XE_RTP_ACTIONS(FIELD_SET(LSN_VC_REG2, 245 LSN_LNI_WGT_MASK | LSN_LNE_WGT_MASK | 246 LSN_DIM_X_WGT_MASK | LSN_DIM_Y_WGT_MASK | 247 LSN_DIM_Z_WGT_MASK, 248 LSN_LNI_WGT(1) | LSN_LNE_WGT(1) | 249 LSN_DIM_X_WGT(1) | LSN_DIM_Y_WGT(1) | 250 LSN_DIM_Z_WGT(1))) 251 }, 252 253 /* Xe2_HPM */ 254 255 { XE_RTP_NAME("16021867713"), 256 XE_RTP_RULES(MEDIA_VERSION(1301), 257 ENGINE_CLASS(VIDEO_DECODE)), 258 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 259 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 260 }, 261 { XE_RTP_NAME("14019449301"), 262 XE_RTP_RULES(MEDIA_VERSION(1301), ENGINE_CLASS(VIDEO_DECODE)), 263 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)), 264 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 265 }, 266 267 /* Xe3_LPG */ 268 269 { XE_RTP_NAME("14021871409"), 270 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0)), 271 XE_RTP_ACTIONS(SET(UNSLCGCTL9454, LSCFE_CLKGATE_DIS)) 272 }, 273 274 /* Xe3_LPM */ 275 276 { XE_RTP_NAME("16021867713"), 277 XE_RTP_RULES(MEDIA_VERSION(3000), 278 ENGINE_CLASS(VIDEO_DECODE)), 279 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 280 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 281 }, 282 { XE_RTP_NAME("16021865536"), 283 XE_RTP_RULES(MEDIA_VERSION(3000), 284 ENGINE_CLASS(VIDEO_DECODE)), 285 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 286 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 287 }, 288 { XE_RTP_NAME("16021865536"), 289 XE_RTP_RULES(MEDIA_VERSION(3002), 290 ENGINE_CLASS(VIDEO_DECODE)), 291 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 292 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 293 }, 294 { XE_RTP_NAME("16021867713"), 295 XE_RTP_RULES(MEDIA_VERSION(3002), 296 ENGINE_CLASS(VIDEO_DECODE)), 297 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 298 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 299 }, 300 { XE_RTP_NAME("14021486841"), 301 XE_RTP_RULES(MEDIA_VERSION(3000), MEDIA_STEP(A0, B0), 302 ENGINE_CLASS(VIDEO_DECODE)), 303 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), RAMDFTUNIT_CLKGATE_DIS)), 304 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 305 }, 306 { XE_RTP_NAME("16028005424"), 307 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005)), 308 XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES)) 309 }, 310 }; 311 312 static const struct xe_rtp_entry_sr engine_was[] = { 313 { XE_RTP_NAME("22010931296, 18011464164, 14010919138"), 314 XE_RTP_RULES(GRAPHICS_VERSION(1200), ENGINE_CLASS(RENDER)), 315 XE_RTP_ACTIONS(SET(FF_THREAD_MODE(RENDER_RING_BASE), 316 FF_TESSELATION_DOP_GATE_DISABLE)) 317 }, 318 { XE_RTP_NAME("1409804808"), 319 XE_RTP_RULES(GRAPHICS_VERSION(1200), 320 ENGINE_CLASS(RENDER), 321 IS_INTEGRATED), 322 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, PUSH_CONST_DEREF_HOLD_DIS)) 323 }, 324 { XE_RTP_NAME("14010229206, 1409085225"), 325 XE_RTP_RULES(GRAPHICS_VERSION(1200), 326 ENGINE_CLASS(RENDER), 327 IS_INTEGRATED), 328 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH)) 329 }, 330 { XE_RTP_NAME("1606931601"), 331 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 332 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_EARLY_READ)) 333 }, 334 { XE_RTP_NAME("14010826681, 1606700617, 22010271021, 18019627453"), 335 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1255), ENGINE_CLASS(RENDER)), 336 XE_RTP_ACTIONS(SET(CS_DEBUG_MODE1(RENDER_RING_BASE), 337 FF_DOP_CLOCK_GATE_DISABLE)) 338 }, 339 { XE_RTP_NAME("1406941453"), 340 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 341 XE_RTP_ACTIONS(SET(SAMPLER_MODE, ENABLE_SMALLPL)) 342 }, 343 { XE_RTP_NAME("FtrPerCtxtPreemptionGranularityControl"), 344 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1250), ENGINE_CLASS(RENDER)), 345 XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN1(RENDER_RING_BASE), 346 FFSC_PERCTX_PREEMPT_CTRL)) 347 }, 348 349 /* TGL */ 350 351 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"), 352 XE_RTP_RULES(PLATFORM(TIGERLAKE), ENGINE_CLASS(RENDER)), 353 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE), 354 WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 355 RC_SEMA_IDLE_MSG_DISABLE)) 356 }, 357 358 /* RKL */ 359 360 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"), 361 XE_RTP_RULES(PLATFORM(ROCKETLAKE), ENGINE_CLASS(RENDER)), 362 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE), 363 WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 364 RC_SEMA_IDLE_MSG_DISABLE)) 365 }, 366 367 /* ADL-P */ 368 369 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"), 370 XE_RTP_RULES(PLATFORM(ALDERLAKE_P), ENGINE_CLASS(RENDER)), 371 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE), 372 WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 373 RC_SEMA_IDLE_MSG_DISABLE)) 374 }, 375 376 /* DG2 */ 377 378 { XE_RTP_NAME("22013037850"), 379 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 380 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, 381 DISABLE_128B_EVICTION_COMMAND_UDW)) 382 }, 383 { XE_RTP_NAME("22014226127"), 384 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 385 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE)) 386 }, 387 { XE_RTP_NAME("18017747507"), 388 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 389 XE_RTP_ACTIONS(SET(VFG_PREEMPTION_CHICKEN, 390 POLYGON_TRIFAN_LINELOOP_DISABLE)) 391 }, 392 { XE_RTP_NAME("22012826095, 22013059131"), 393 XE_RTP_RULES(SUBPLATFORM(DG2, G11), 394 FUNC(xe_rtp_match_first_render_or_compute)), 395 XE_RTP_ACTIONS(FIELD_SET(LSC_CHICKEN_BIT_0_UDW, 396 MAXREQS_PER_BANK, 397 REG_FIELD_PREP(MAXREQS_PER_BANK, 2))) 398 }, 399 { XE_RTP_NAME("22013059131"), 400 XE_RTP_RULES(SUBPLATFORM(DG2, G11), 401 FUNC(xe_rtp_match_first_render_or_compute)), 402 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, FORCE_1_SUB_MESSAGE_PER_FRAGMENT)) 403 }, 404 { XE_RTP_NAME("14015227452"), 405 XE_RTP_RULES(PLATFORM(DG2), 406 FUNC(xe_rtp_match_first_render_or_compute)), 407 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE)) 408 }, 409 { XE_RTP_NAME("18028616096"), 410 XE_RTP_RULES(PLATFORM(DG2), 411 FUNC(xe_rtp_match_first_render_or_compute)), 412 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3)) 413 }, 414 { XE_RTP_NAME("22015475538"), 415 XE_RTP_RULES(PLATFORM(DG2), 416 FUNC(xe_rtp_match_first_render_or_compute)), 417 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8)) 418 }, 419 { XE_RTP_NAME("22012654132"), 420 XE_RTP_RULES(SUBPLATFORM(DG2, G11), 421 FUNC(xe_rtp_match_first_render_or_compute)), 422 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, ENABLE_PREFETCH_INTO_IC, 423 /* 424 * Register can't be read back for verification on 425 * DG2 due to Wa_14012342262 426 */ 427 .read_mask = 0)) 428 }, 429 { XE_RTP_NAME("1509727124"), 430 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 431 XE_RTP_ACTIONS(SET(SAMPLER_MODE, SC_DISABLE_POWER_OPTIMIZATION_EBB)) 432 }, 433 { XE_RTP_NAME("22012856258"), 434 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 435 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_READ_SUPPRESSION)) 436 }, 437 { XE_RTP_NAME("22010960976, 14013347512"), 438 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 439 XE_RTP_ACTIONS(CLR(XEHP_HDC_CHICKEN0, 440 LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK)) 441 }, 442 { XE_RTP_NAME("14015150844"), 443 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 444 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES, 445 XE_RTP_NOCHECK)) 446 }, 447 448 /* PVC */ 449 450 { XE_RTP_NAME("22014226127"), 451 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)), 452 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE)) 453 }, 454 { XE_RTP_NAME("14015227452"), 455 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)), 456 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE)) 457 }, 458 { XE_RTP_NAME("18020744125"), 459 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute), 460 ENGINE_CLASS(COMPUTE)), 461 XE_RTP_ACTIONS(SET(RING_HWSTAM(RENDER_RING_BASE), ~0)) 462 }, 463 { XE_RTP_NAME("14014999345"), 464 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COMPUTE), 465 GRAPHICS_STEP(B0, C0)), 466 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, DISABLE_ECC)) 467 }, 468 469 /* Xe_LPG */ 470 471 { XE_RTP_NAME("14017856879"), 472 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), 473 FUNC(xe_rtp_match_first_render_or_compute)), 474 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, DIS_FIX_EOT1_FLUSH)) 475 }, 476 { XE_RTP_NAME("14015150844"), 477 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), 478 FUNC(xe_rtp_match_first_render_or_compute)), 479 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES, 480 XE_RTP_NOCHECK)) 481 }, 482 { XE_RTP_NAME("14020495402"), 483 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), 484 FUNC(xe_rtp_match_first_render_or_compute)), 485 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_TDL_SVHS_GATING)) 486 }, 487 488 /* Xe2_LPG */ 489 490 { XE_RTP_NAME("18032247524"), 491 XE_RTP_RULES(GRAPHICS_VERSION(2004), 492 FUNC(xe_rtp_match_first_render_or_compute)), 493 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE)) 494 }, 495 { XE_RTP_NAME("16018712365"), 496 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 497 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS)) 498 }, 499 { XE_RTP_NAME("14020338487"), 500 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 501 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS)) 502 }, 503 { XE_RTP_NAME("18034896535, 16021540221"), /* 16021540221: GRAPHICS_STEP(A0, B0) */ 504 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), 505 FUNC(xe_rtp_match_first_render_or_compute)), 506 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH)) 507 }, 508 { XE_RTP_NAME("14018471104"), 509 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 510 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL)) 511 }, 512 /* 513 * These two workarounds are the same, just applying to different 514 * engines. Although Wa_18032095049 (for the RCS) isn't required on 515 * all steppings, disabling these reports has no impact for our 516 * driver or the GuC, so we go ahead and treat it the same as 517 * Wa_16021639441 which does apply to all steppings. 518 */ 519 { XE_RTP_NAME("18032095049, 16021639441"), 520 XE_RTP_RULES(GRAPHICS_VERSION(2004)), 521 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), 522 GHWSP_CSB_REPORT_DIS | 523 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, 524 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 525 }, 526 { XE_RTP_NAME("16018610683"), 527 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 528 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, SLM_WMTP_RESTORE)) 529 }, 530 { XE_RTP_NAME("14021402888"), 531 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 532 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE)) 533 }, 534 { XE_RTP_NAME("13012615864"), 535 XE_RTP_RULES(GRAPHICS_VERSION(2004), 536 FUNC(xe_rtp_match_first_render_or_compute)), 537 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS)) 538 }, 539 540 /* Xe2_HPG */ 541 542 { XE_RTP_NAME("16018712365"), 543 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 544 FUNC(xe_rtp_match_first_render_or_compute)), 545 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS)) 546 }, 547 { XE_RTP_NAME("16018737384"), 548 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED), 549 FUNC(xe_rtp_match_first_render_or_compute)), 550 XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS)) 551 }, 552 { XE_RTP_NAME("14020338487"), 553 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 554 FUNC(xe_rtp_match_first_render_or_compute)), 555 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS)) 556 }, 557 { XE_RTP_NAME("18032247524"), 558 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 559 FUNC(xe_rtp_match_first_render_or_compute)), 560 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE)) 561 }, 562 { XE_RTP_NAME("14018471104"), 563 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 564 FUNC(xe_rtp_match_first_render_or_compute)), 565 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL)) 566 }, 567 /* 568 * Although this workaround isn't required for the RCS, disabling these 569 * reports has no impact for our driver or the GuC, so we go ahead and 570 * apply this to all engines for simplicity. 571 */ 572 { XE_RTP_NAME("16021639441"), 573 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002)), 574 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), 575 GHWSP_CSB_REPORT_DIS | 576 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, 577 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 578 }, 579 { XE_RTP_NAME("14019811474"), 580 XE_RTP_RULES(GRAPHICS_VERSION(2001), 581 FUNC(xe_rtp_match_first_render_or_compute)), 582 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, WR_REQ_CHAINING_DIS)) 583 }, 584 { XE_RTP_NAME("14021402888"), 585 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), 586 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE)) 587 }, 588 { XE_RTP_NAME("14021821874, 14022954250"), 589 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 590 FUNC(xe_rtp_match_first_render_or_compute)), 591 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, STK_ID_RESTRICT)) 592 }, 593 { XE_RTP_NAME("13012615864"), 594 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 595 FUNC(xe_rtp_match_first_render_or_compute)), 596 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS)) 597 }, 598 { XE_RTP_NAME("18041344222"), 599 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 600 FUNC(xe_rtp_match_first_render_or_compute), 601 FUNC(xe_rtp_match_not_sriov_vf), 602 FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)), 603 XE_RTP_ACTIONS(SET(TDL_CHICKEN, EUSTALL_PERF_SAMPLING_DISABLE)) 604 }, 605 606 /* Xe2_LPM */ 607 608 { XE_RTP_NAME("16021639441"), 609 XE_RTP_RULES(MEDIA_VERSION(2000)), 610 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), 611 GHWSP_CSB_REPORT_DIS | 612 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, 613 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 614 }, 615 616 /* Xe2_HPM */ 617 618 { XE_RTP_NAME("16021639441"), 619 XE_RTP_RULES(MEDIA_VERSION(1301)), 620 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), 621 GHWSP_CSB_REPORT_DIS | 622 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, 623 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 624 }, 625 626 /* Xe3_LPG */ 627 628 { XE_RTP_NAME("14021402888"), 629 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), 630 FUNC(xe_rtp_match_first_render_or_compute)), 631 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE)) 632 }, 633 { XE_RTP_NAME("18034896535"), 634 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0), 635 FUNC(xe_rtp_match_first_render_or_compute)), 636 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH)) 637 }, 638 { XE_RTP_NAME("16024792527"), 639 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0), 640 FUNC(xe_rtp_match_first_render_or_compute)), 641 XE_RTP_ACTIONS(FIELD_SET(SAMPLER_MODE, SMP_WAIT_FETCH_MERGING_COUNTER, 642 SMP_FORCE_128B_OVERFETCH)) 643 }, 644 { XE_RTP_NAME("14023061436"), 645 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), 646 FUNC(xe_rtp_match_first_render_or_compute), OR, 647 GRAPHICS_VERSION_RANGE(3003, 3005), 648 FUNC(xe_rtp_match_first_render_or_compute)), 649 XE_RTP_ACTIONS(SET(TDL_CHICKEN, QID_WAIT_FOR_THREAD_NOT_RUN_DISABLE)) 650 }, 651 { XE_RTP_NAME("13012615864"), 652 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), OR, 653 GRAPHICS_VERSION_RANGE(3003, 3005), 654 FUNC(xe_rtp_match_first_render_or_compute)), 655 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS)) 656 }, 657 { XE_RTP_NAME("16023105232"), 658 XE_RTP_RULES(MEDIA_VERSION_RANGE(1301, 3000), OR, 659 GRAPHICS_VERSION_RANGE(2001, 3001)), 660 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(0), RC_SEMA_IDLE_MSG_DISABLE, 661 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 662 }, 663 { XE_RTP_NAME("14021402888"), 664 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3003, 3005), FUNC(xe_rtp_match_first_render_or_compute)), 665 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE)) 666 }, 667 { XE_RTP_NAME("18041344222"), 668 XE_RTP_RULES(GRAPHICS_VERSION(3000), 669 FUNC(xe_rtp_match_first_render_or_compute), 670 FUNC(xe_rtp_match_not_sriov_vf), 671 FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)), 672 XE_RTP_ACTIONS(SET(TDL_CHICKEN, EUSTALL_PERF_SAMPLING_DISABLE)) 673 }, 674 }; 675 676 static const struct xe_rtp_entry_sr lrc_was[] = { 677 { XE_RTP_NAME("16011163337"), 678 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 679 /* read verification is ignored due to 1608008084. */ 680 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2, 681 FF_MODE2_GS_TIMER_MASK, 682 FF_MODE2_GS_TIMER_224)) 683 }, 684 { XE_RTP_NAME("1604555607"), 685 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 686 /* read verification is ignored due to 1608008084. */ 687 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2, 688 FF_MODE2_TDS_TIMER_MASK, 689 FF_MODE2_TDS_TIMER_128)) 690 }, 691 { XE_RTP_NAME("1409342910, 14010698770, 14010443199, 1408979724, 1409178076, 1409207793, 1409217633, 1409252684, 1409347922, 1409142259"), 692 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), 693 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN3, 694 DISABLE_CPS_AWARE_COLOR_PIPE)) 695 }, 696 { XE_RTP_NAME("WaDisableGPGPUMidThreadPreemption"), 697 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), 698 XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(RENDER_RING_BASE), 699 PREEMPT_GPGPU_LEVEL_MASK, 700 PREEMPT_GPGPU_THREAD_GROUP_LEVEL)) 701 }, 702 { XE_RTP_NAME("1806527549"), 703 XE_RTP_RULES(GRAPHICS_VERSION(1200)), 704 XE_RTP_ACTIONS(SET(HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE)) 705 }, 706 { XE_RTP_NAME("1606376872"), 707 XE_RTP_RULES(GRAPHICS_VERSION(1200)), 708 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC)) 709 }, 710 711 /* DG1 */ 712 713 { XE_RTP_NAME("1409044764"), 714 XE_RTP_RULES(PLATFORM(DG1)), 715 XE_RTP_ACTIONS(CLR(COMMON_SLICE_CHICKEN3, 716 DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN)) 717 }, 718 { XE_RTP_NAME("22010493298"), 719 XE_RTP_RULES(PLATFORM(DG1)), 720 XE_RTP_ACTIONS(SET(HIZ_CHICKEN, 721 DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE)) 722 }, 723 724 /* DG2 */ 725 726 { XE_RTP_NAME("16013271637"), 727 XE_RTP_RULES(PLATFORM(DG2)), 728 XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1, 729 MSC_MSAA_REODER_BUF_BYPASS_DISABLE)) 730 }, 731 { XE_RTP_NAME("14014947963"), 732 XE_RTP_RULES(PLATFORM(DG2)), 733 XE_RTP_ACTIONS(FIELD_SET(VF_PREEMPTION, 734 PREEMPTION_VERTEX_COUNT, 735 0x4000)) 736 }, 737 { XE_RTP_NAME("18018764978"), 738 XE_RTP_RULES(PLATFORM(DG2)), 739 XE_RTP_ACTIONS(SET(XEHP_PSS_MODE2, 740 SCOREBOARD_STALL_FLUSH_CONTROL)) 741 }, 742 { XE_RTP_NAME("18019271663"), 743 XE_RTP_RULES(PLATFORM(DG2)), 744 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE)) 745 }, 746 { XE_RTP_NAME("14019877138"), 747 XE_RTP_RULES(PLATFORM(DG2)), 748 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 749 }, 750 751 /* PVC */ 752 753 { XE_RTP_NAME("16017236439"), 754 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COPY), 755 FUNC(xe_rtp_match_even_instance)), 756 XE_RTP_ACTIONS(SET(BCS_SWCTRL(0), 757 BCS_SWCTRL_DISABLE_256B, 758 XE_RTP_ACTION_FLAG(ENGINE_BASE))), 759 }, 760 761 /* Xe_LPG */ 762 763 { XE_RTP_NAME("18019271663"), 764 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)), 765 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE)) 766 }, 767 { XE_RTP_NAME("14019877138"), 768 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), ENGINE_CLASS(RENDER)), 769 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 770 }, 771 772 /* Xe2_LPG */ 773 774 { XE_RTP_NAME("14019386621"), 775 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 776 XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE)) 777 }, 778 { XE_RTP_NAME("14019877138"), 779 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 780 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 781 }, 782 { XE_RTP_NAME("14019988906"), 783 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 784 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD)) 785 }, 786 { XE_RTP_NAME("18033852989"), 787 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 788 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST)) 789 }, 790 { XE_RTP_NAME("14021567978"), 791 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED), 792 ENGINE_CLASS(RENDER)), 793 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_2, TBIMR_FAST_CLIP)) 794 }, 795 { XE_RTP_NAME("14020756599"), 796 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER), OR, 797 MEDIA_VERSION_ANY_GT(2000), ENGINE_CLASS(RENDER)), 798 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS)) 799 }, 800 { XE_RTP_NAME("14021490052"), 801 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 802 XE_RTP_ACTIONS(SET(FF_MODE, 803 DIS_MESH_PARTIAL_AUTOSTRIP | 804 DIS_MESH_AUTOSTRIP), 805 SET(VFLSKPD, 806 DIS_PARTIAL_AUTOSTRIP | 807 DIS_AUTOSTRIP)) 808 }, 809 { XE_RTP_NAME("15016589081"), 810 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 811 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX)) 812 }, 813 814 /* Xe2_HPG */ 815 { XE_RTP_NAME("15010599737"), 816 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 817 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN)) 818 }, 819 { XE_RTP_NAME("14019386621"), 820 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), 821 XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE)) 822 }, 823 { XE_RTP_NAME("14020756599"), 824 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 825 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS)) 826 }, 827 { XE_RTP_NAME("14019988906"), 828 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), 829 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD)) 830 }, 831 { XE_RTP_NAME("14019877138"), 832 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), 833 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 834 }, 835 { XE_RTP_NAME("14021490052"), 836 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 837 XE_RTP_ACTIONS(SET(FF_MODE, 838 DIS_MESH_PARTIAL_AUTOSTRIP | 839 DIS_MESH_AUTOSTRIP), 840 SET(VFLSKPD, 841 DIS_PARTIAL_AUTOSTRIP | 842 DIS_AUTOSTRIP)) 843 }, 844 { XE_RTP_NAME("15016589081"), 845 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), 846 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX)) 847 }, 848 { XE_RTP_NAME("22021007897"), 849 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), 850 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE)) 851 }, 852 { XE_RTP_NAME("18033852989"), 853 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 854 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST)) 855 }, 856 857 /* Xe3_LPG */ 858 { XE_RTP_NAME("14021490052"), 859 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0), 860 ENGINE_CLASS(RENDER)), 861 XE_RTP_ACTIONS(SET(FF_MODE, 862 DIS_MESH_PARTIAL_AUTOSTRIP | 863 DIS_MESH_AUTOSTRIP), 864 SET(VFLSKPD, 865 DIS_PARTIAL_AUTOSTRIP | 866 DIS_AUTOSTRIP)) 867 }, 868 { XE_RTP_NAME("22021007897"), 869 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005), ENGINE_CLASS(RENDER)), 870 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE)) 871 }, 872 { XE_RTP_NAME("14024681466"), 873 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005), ENGINE_CLASS(RENDER)), 874 XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1, FAST_CLEAR_VALIGN_FIX)) 875 }, 876 { XE_RTP_NAME("15016589081"), 877 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0), 878 ENGINE_CLASS(RENDER)), 879 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX)) 880 }, 881 }; 882 883 static __maybe_unused const struct xe_rtp_entry oob_was[] = { 884 #include <generated/xe_wa_oob.c> 885 {} 886 }; 887 888 static_assert(ARRAY_SIZE(oob_was) - 1 == _XE_WA_OOB_COUNT); 889 890 static __maybe_unused const struct xe_rtp_entry device_oob_was[] = { 891 #include <generated/xe_device_wa_oob.c> 892 {} 893 }; 894 895 static_assert(ARRAY_SIZE(device_oob_was) - 1 == _XE_DEVICE_WA_OOB_COUNT); 896 897 __diag_pop(); 898 899 /** 900 * xe_wa_process_device_oob - process OOB workaround table 901 * @xe: device instance to process workarounds for 902 * 903 * process OOB workaround table for this device, marking in @xe the 904 * workarounds that are active. 905 */ 906 907 void xe_wa_process_device_oob(struct xe_device *xe) 908 { 909 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(xe); 910 911 xe_rtp_process_ctx_enable_active_tracking(&ctx, xe->wa_active.oob, ARRAY_SIZE(device_oob_was)); 912 913 xe->wa_active.oob_initialized = true; 914 xe_rtp_process(&ctx, device_oob_was); 915 } 916 917 /** 918 * xe_wa_process_gt_oob - process GT OOB workaround table 919 * @gt: GT instance to process workarounds for 920 * 921 * Process OOB workaround table for this platform, marking in @gt the 922 * workarounds that are active. 923 */ 924 void xe_wa_process_gt_oob(struct xe_gt *gt) 925 { 926 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt); 927 928 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.oob, 929 ARRAY_SIZE(oob_was)); 930 gt->wa_active.oob_initialized = true; 931 xe_rtp_process(&ctx, oob_was); 932 } 933 934 /** 935 * xe_wa_process_gt - process GT workaround table 936 * @gt: GT instance to process workarounds for 937 * 938 * Process GT workaround table for this platform, saving in @gt all the 939 * workarounds that need to be applied at the GT level. 940 */ 941 void xe_wa_process_gt(struct xe_gt *gt) 942 { 943 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt); 944 945 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.gt, 946 ARRAY_SIZE(gt_was)); 947 xe_rtp_process_to_sr(&ctx, gt_was, ARRAY_SIZE(gt_was), >->reg_sr); 948 } 949 EXPORT_SYMBOL_IF_KUNIT(xe_wa_process_gt); 950 951 /** 952 * xe_wa_process_engine - process engine workaround table 953 * @hwe: engine instance to process workarounds for 954 * 955 * Process engine workaround table for this platform, saving in @hwe all the 956 * workarounds that need to be applied at the engine level that match this 957 * engine. 958 */ 959 void xe_wa_process_engine(struct xe_hw_engine *hwe) 960 { 961 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); 962 963 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.engine, 964 ARRAY_SIZE(engine_was)); 965 xe_rtp_process_to_sr(&ctx, engine_was, ARRAY_SIZE(engine_was), &hwe->reg_sr); 966 } 967 968 /** 969 * xe_wa_process_lrc - process context workaround table 970 * @hwe: engine instance to process workarounds for 971 * 972 * Process context workaround table for this platform, saving in @hwe all the 973 * workarounds that need to be applied on context restore. These are workarounds 974 * touching registers that are part of the HW context image. 975 */ 976 void xe_wa_process_lrc(struct xe_hw_engine *hwe) 977 { 978 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); 979 980 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.lrc, 981 ARRAY_SIZE(lrc_was)); 982 xe_rtp_process_to_sr(&ctx, lrc_was, ARRAY_SIZE(lrc_was), &hwe->reg_lrc); 983 } 984 985 /** 986 * xe_wa_device_init - initialize device with workaround oob bookkeeping 987 * @xe: Xe device instance to initialize 988 * 989 * Returns 0 for success, negative with error code otherwise 990 */ 991 int xe_wa_device_init(struct xe_device *xe) 992 { 993 unsigned long *p; 994 995 p = drmm_kzalloc(&xe->drm, 996 sizeof(*p) * BITS_TO_LONGS(ARRAY_SIZE(device_oob_was)), 997 GFP_KERNEL); 998 999 if (!p) 1000 return -ENOMEM; 1001 1002 xe->wa_active.oob = p; 1003 1004 return 0; 1005 } 1006 1007 /** 1008 * xe_wa_gt_init - initialize gt with workaround bookkeeping 1009 * @gt: GT instance to initialize 1010 * 1011 * Returns 0 for success, negative error code otherwise. 1012 */ 1013 int xe_wa_gt_init(struct xe_gt *gt) 1014 { 1015 struct xe_device *xe = gt_to_xe(gt); 1016 size_t n_oob, n_lrc, n_engine, n_gt, total; 1017 unsigned long *p; 1018 1019 n_gt = BITS_TO_LONGS(ARRAY_SIZE(gt_was)); 1020 n_engine = BITS_TO_LONGS(ARRAY_SIZE(engine_was)); 1021 n_lrc = BITS_TO_LONGS(ARRAY_SIZE(lrc_was)); 1022 n_oob = BITS_TO_LONGS(ARRAY_SIZE(oob_was)); 1023 total = n_gt + n_engine + n_lrc + n_oob; 1024 1025 p = drmm_kzalloc(&xe->drm, sizeof(*p) * total, GFP_KERNEL); 1026 if (!p) 1027 return -ENOMEM; 1028 1029 gt->wa_active.gt = p; 1030 p += n_gt; 1031 gt->wa_active.engine = p; 1032 p += n_engine; 1033 gt->wa_active.lrc = p; 1034 p += n_lrc; 1035 gt->wa_active.oob = p; 1036 1037 return 0; 1038 } 1039 ALLOW_ERROR_INJECTION(xe_wa_gt_init, ERRNO); /* See xe_pci_probe() */ 1040 1041 void xe_wa_device_dump(struct xe_device *xe, struct drm_printer *p) 1042 { 1043 size_t idx; 1044 1045 drm_printf(p, "Device OOB Workarounds\n"); 1046 for_each_set_bit(idx, xe->wa_active.oob, ARRAY_SIZE(device_oob_was)) 1047 if (device_oob_was[idx].name) 1048 drm_printf_indent(p, 1, "%s\n", device_oob_was[idx].name); 1049 } 1050 1051 /** 1052 * xe_wa_gt_dump() - Dump GT workarounds into a drm printer. 1053 * @gt: the &xe_gt 1054 * @p: the &drm_printer 1055 * 1056 * Return: always 0. 1057 */ 1058 int xe_wa_gt_dump(struct xe_gt *gt, struct drm_printer *p) 1059 { 1060 size_t idx; 1061 1062 drm_printf(p, "GT Workarounds\n"); 1063 for_each_set_bit(idx, gt->wa_active.gt, ARRAY_SIZE(gt_was)) 1064 drm_printf_indent(p, 1, "%s\n", gt_was[idx].name); 1065 1066 drm_puts(p, "\n"); 1067 drm_printf(p, "Engine Workarounds\n"); 1068 for_each_set_bit(idx, gt->wa_active.engine, ARRAY_SIZE(engine_was)) 1069 drm_printf_indent(p, 1, "%s\n", engine_was[idx].name); 1070 1071 drm_puts(p, "\n"); 1072 drm_printf(p, "LRC Workarounds\n"); 1073 for_each_set_bit(idx, gt->wa_active.lrc, ARRAY_SIZE(lrc_was)) 1074 drm_printf_indent(p, 1, "%s\n", lrc_was[idx].name); 1075 1076 drm_puts(p, "\n"); 1077 drm_printf(p, "OOB Workarounds\n"); 1078 for_each_set_bit(idx, gt->wa_active.oob, ARRAY_SIZE(oob_was)) 1079 if (oob_was[idx].name) 1080 drm_printf_indent(p, 1, "%s\n", oob_was[idx].name); 1081 return 0; 1082 } 1083 1084 /* 1085 * Apply tile (non-GT, non-display) workarounds. Think very carefully before 1086 * adding anything to this function; most workarounds should be implemented 1087 * elsewhere. The programming here is primarily for sgunit/soc workarounds, 1088 * which are relatively rare. Since the registers these workarounds target are 1089 * outside the GT, they should only need to be applied once at device 1090 * probe/resume; they will not lose their values on any kind of GT or engine 1091 * reset. 1092 * 1093 * TODO: We may want to move this over to xe_rtp in the future once we have 1094 * enough workarounds to justify the work. 1095 */ 1096 void xe_wa_apply_tile_workarounds(struct xe_tile *tile) 1097 { 1098 struct xe_mmio *mmio = &tile->mmio; 1099 1100 if (IS_SRIOV_VF(tile->xe)) 1101 return; 1102 1103 if (XE_DEVICE_WA(tile->xe, 22010954014)) 1104 xe_mmio_rmw32(mmio, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS); 1105 } 1106