1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_wa.h" 7 8 #include <drm/drm_managed.h> 9 #include <kunit/visibility.h> 10 #include <linux/compiler_types.h> 11 12 #include <generated/xe_wa_oob.h> 13 14 #include "regs/xe_engine_regs.h" 15 #include "regs/xe_gt_regs.h" 16 #include "regs/xe_regs.h" 17 #include "xe_device_types.h" 18 #include "xe_force_wake.h" 19 #include "xe_gt.h" 20 #include "xe_hw_engine_types.h" 21 #include "xe_mmio.h" 22 #include "xe_platform_types.h" 23 #include "xe_rtp.h" 24 #include "xe_step.h" 25 26 /** 27 * DOC: Hardware workarounds 28 * 29 * Hardware workarounds are register programming documented to be executed in 30 * the driver that fall outside of the normal programming sequences for a 31 * platform. There are some basic categories of workarounds, depending on 32 * how/when they are applied: 33 * 34 * - LRC workarounds: workarounds that touch registers that are 35 * saved/restored to/from the HW context image. The list is emitted (via Load 36 * Register Immediate commands) once when initializing the device and saved in 37 * the default context. That default context is then used on every context 38 * creation to have a "primed golden context", i.e. a context image that 39 * already contains the changes needed to all the registers. 40 * 41 * - Engine workarounds: the list of these WAs is applied whenever the specific 42 * engine is reset. It's also possible that a set of engine classes share a 43 * common power domain and they are reset together. This happens on some 44 * platforms with render and compute engines. In this case (at least) one of 45 * them need to keeep the workaround programming: the approach taken in the 46 * driver is to tie those workarounds to the first compute/render engine that 47 * is registered. When executing with GuC submission, engine resets are 48 * outside of kernel driver control, hence the list of registers involved in 49 * written once, on engine initialization, and then passed to GuC, that 50 * saves/restores their values before/after the reset takes place. See 51 * ``drivers/gpu/drm/xe/xe_guc_ads.c`` for reference. 52 * 53 * - GT workarounds: the list of these WAs is applied whenever these registers 54 * revert to their default values: on GPU reset, suspend/resume [1]_, etc. 55 * 56 * - Register whitelist: some workarounds need to be implemented in userspace, 57 * but need to touch privileged registers. The whitelist in the kernel 58 * instructs the hardware to allow the access to happen. From the kernel side, 59 * this is just a special case of a MMIO workaround (as we write the list of 60 * these to/be-whitelisted registers to some special HW registers). 61 * 62 * - Workaround batchbuffers: buffers that get executed automatically by the 63 * hardware on every HW context restore. These buffers are created and 64 * programmed in the default context so the hardware always go through those 65 * programming sequences when switching contexts. The support for workaround 66 * batchbuffers is enabled these hardware mechanisms: 67 * 68 * #. INDIRECT_CTX: A batchbuffer and an offset are provided in the default 69 * context, pointing the hardware to jump to that location when that offset 70 * is reached in the context restore. Workaround batchbuffer in the driver 71 * currently uses this mechanism for all platforms. 72 * 73 * #. BB_PER_CTX_PTR: A batchbuffer is provided in the default context, 74 * pointing the hardware to a buffer to continue executing after the 75 * engine registers are restored in a context restore sequence. This is 76 * currently not used in the driver. 77 * 78 * - Other/OOB: There are WAs that, due to their nature, cannot be applied from 79 * a central place. Those are peppered around the rest of the code, as needed. 80 * Workarounds related to the display IP are the main example. 81 * 82 * .. [1] Technically, some registers are powercontext saved & restored, so they 83 * survive a suspend/resume. In practice, writing them again is not too 84 * costly and simplifies things, so it's the approach taken in the driver. 85 * 86 * .. note:: 87 * Hardware workarounds in xe work the same way as in i915, with the 88 * difference of how they are maintained in the code. In xe it uses the 89 * xe_rtp infrastructure so the workarounds can be kept in tables, following 90 * a more declarative approach rather than procedural. 91 */ 92 93 #undef XE_REG_MCR 94 #define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1) 95 96 __diag_push(); 97 __diag_ignore_all("-Woverride-init", "Allow field overrides in table"); 98 99 static const struct xe_rtp_entry_sr gt_was[] = { 100 { XE_RTP_NAME("14011060649"), 101 XE_RTP_RULES(MEDIA_VERSION_RANGE(1200, 1255), 102 ENGINE_CLASS(VIDEO_DECODE), 103 FUNC(xe_rtp_match_even_instance)), 104 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 105 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 106 }, 107 { XE_RTP_NAME("14011059788"), 108 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), 109 XE_RTP_ACTIONS(SET(DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE)) 110 }, 111 { XE_RTP_NAME("14015795083"), 112 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1260)), 113 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE)) 114 }, 115 116 /* DG1 */ 117 118 { XE_RTP_NAME("1409420604"), 119 XE_RTP_RULES(PLATFORM(DG1)), 120 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE2, CPSSUNIT_CLKGATE_DIS)) 121 }, 122 { XE_RTP_NAME("1408615072"), 123 XE_RTP_RULES(PLATFORM(DG1)), 124 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE2_DIS)) 125 }, 126 127 /* DG2 */ 128 129 { XE_RTP_NAME("22010523718"), 130 XE_RTP_RULES(SUBPLATFORM(DG2, G10)), 131 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE, CG3DDISCFEG_CLKGATE_DIS)) 132 }, 133 { XE_RTP_NAME("14011006942"), 134 XE_RTP_RULES(SUBPLATFORM(DG2, G10)), 135 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE, DSS_ROUTER_CLKGATE_DIS)) 136 }, 137 { XE_RTP_NAME("14014830051"), 138 XE_RTP_RULES(PLATFORM(DG2)), 139 XE_RTP_ACTIONS(CLR(SARB_CHICKEN1, COMP_CKN_IN)) 140 }, 141 { XE_RTP_NAME("18018781329"), 142 XE_RTP_RULES(PLATFORM(DG2)), 143 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB), 144 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB), 145 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB), 146 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB)) 147 }, 148 { XE_RTP_NAME("1509235366"), 149 XE_RTP_RULES(PLATFORM(DG2)), 150 XE_RTP_ACTIONS(SET(XEHP_GAMCNTRL_CTRL, 151 INVALIDATION_BROADCAST_MODE_DIS | 152 GLOBAL_INVALIDATION_MODE)) 153 }, 154 155 /* PVC */ 156 157 { XE_RTP_NAME("18018781329"), 158 XE_RTP_RULES(PLATFORM(PVC)), 159 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB), 160 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB), 161 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB), 162 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB)) 163 }, 164 { XE_RTP_NAME("16016694945"), 165 XE_RTP_RULES(PLATFORM(PVC)), 166 XE_RTP_ACTIONS(SET(XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC)) 167 }, 168 169 /* Xe_LPG */ 170 171 { XE_RTP_NAME("14015795083"), 172 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), GRAPHICS_STEP(A0, B0)), 173 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE)) 174 }, 175 { XE_RTP_NAME("14018575942"), 176 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)), 177 XE_RTP_ACTIONS(SET(COMP_MOD_CTRL, FORCE_MISS_FTLB)) 178 }, 179 { XE_RTP_NAME("22016670082"), 180 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)), 181 XE_RTP_ACTIONS(SET(SQCNT1, ENFORCE_RAR)) 182 }, 183 184 /* Xe_LPM+ */ 185 186 { XE_RTP_NAME("16021867713"), 187 XE_RTP_RULES(MEDIA_VERSION(1300), 188 ENGINE_CLASS(VIDEO_DECODE)), 189 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 190 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 191 }, 192 { XE_RTP_NAME("22016670082"), 193 XE_RTP_RULES(MEDIA_VERSION(1300)), 194 XE_RTP_ACTIONS(SET(XELPMP_SQCNT1, ENFORCE_RAR)) 195 }, 196 197 /* Xe2_LPG */ 198 199 { XE_RTP_NAME("16020975621"), 200 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)), 201 XE_RTP_ACTIONS(SET(XEHP_SLICE_UNIT_LEVEL_CLKGATE, SBEUNIT_CLKGATE_DIS)) 202 }, 203 { XE_RTP_NAME("14018157293"), 204 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)), 205 XE_RTP_ACTIONS(SET(XEHPC_L3CLOS_MASK(0), ~0), 206 SET(XEHPC_L3CLOS_MASK(1), ~0), 207 SET(XEHPC_L3CLOS_MASK(2), ~0), 208 SET(XEHPC_L3CLOS_MASK(3), ~0)) 209 }, 210 211 /* Xe2_LPM */ 212 213 { XE_RTP_NAME("14017421178"), 214 XE_RTP_RULES(MEDIA_VERSION(2000), 215 ENGINE_CLASS(VIDEO_DECODE)), 216 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 217 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 218 }, 219 { XE_RTP_NAME("16021867713"), 220 XE_RTP_RULES(MEDIA_VERSION(2000), 221 ENGINE_CLASS(VIDEO_DECODE)), 222 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 223 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 224 }, 225 { XE_RTP_NAME("14019449301"), 226 XE_RTP_RULES(MEDIA_VERSION(2000), ENGINE_CLASS(VIDEO_DECODE)), 227 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)), 228 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 229 }, 230 231 /* Xe2_HPM */ 232 233 { XE_RTP_NAME("16021867713"), 234 XE_RTP_RULES(MEDIA_VERSION(1301), 235 ENGINE_CLASS(VIDEO_DECODE)), 236 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 237 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 238 }, 239 { XE_RTP_NAME("14020316580"), 240 XE_RTP_RULES(MEDIA_VERSION(1301)), 241 XE_RTP_ACTIONS(CLR(PG_ENABLE, 242 VD0_HCP_POWERGATE_ENABLE | 243 VD0_MFXVDENC_POWERGATE_ENABLE | 244 VD2_HCP_POWERGATE_ENABLE | 245 VD2_MFXVDENC_POWERGATE_ENABLE)), 246 }, 247 { XE_RTP_NAME("14019449301"), 248 XE_RTP_RULES(MEDIA_VERSION(1301), ENGINE_CLASS(VIDEO_DECODE)), 249 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)), 250 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 251 }, 252 253 {} 254 }; 255 256 static const struct xe_rtp_entry_sr engine_was[] = { 257 { XE_RTP_NAME("22010931296, 18011464164, 14010919138"), 258 XE_RTP_RULES(GRAPHICS_VERSION(1200), ENGINE_CLASS(RENDER)), 259 XE_RTP_ACTIONS(SET(FF_THREAD_MODE(RENDER_RING_BASE), 260 FF_TESSELATION_DOP_GATE_DISABLE)) 261 }, 262 { XE_RTP_NAME("1409804808"), 263 XE_RTP_RULES(GRAPHICS_VERSION(1200), 264 ENGINE_CLASS(RENDER), 265 IS_INTEGRATED), 266 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, PUSH_CONST_DEREF_HOLD_DIS)) 267 }, 268 { XE_RTP_NAME("14010229206, 1409085225"), 269 XE_RTP_RULES(GRAPHICS_VERSION(1200), 270 ENGINE_CLASS(RENDER), 271 IS_INTEGRATED), 272 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH)) 273 }, 274 { XE_RTP_NAME("1606931601"), 275 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 276 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_EARLY_READ)) 277 }, 278 { XE_RTP_NAME("14010826681, 1606700617, 22010271021, 18019627453"), 279 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1255), ENGINE_CLASS(RENDER)), 280 XE_RTP_ACTIONS(SET(CS_DEBUG_MODE1(RENDER_RING_BASE), 281 FF_DOP_CLOCK_GATE_DISABLE)) 282 }, 283 { XE_RTP_NAME("1406941453"), 284 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 285 XE_RTP_ACTIONS(SET(SAMPLER_MODE, ENABLE_SMALLPL)) 286 }, 287 { XE_RTP_NAME("FtrPerCtxtPreemptionGranularityControl"), 288 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1250), ENGINE_CLASS(RENDER)), 289 XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN1(RENDER_RING_BASE), 290 FFSC_PERCTX_PREEMPT_CTRL)) 291 }, 292 293 /* TGL */ 294 295 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"), 296 XE_RTP_RULES(PLATFORM(TIGERLAKE), ENGINE_CLASS(RENDER)), 297 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE), 298 WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 299 RC_SEMA_IDLE_MSG_DISABLE)) 300 }, 301 302 /* RKL */ 303 304 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"), 305 XE_RTP_RULES(PLATFORM(ROCKETLAKE), ENGINE_CLASS(RENDER)), 306 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE), 307 WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 308 RC_SEMA_IDLE_MSG_DISABLE)) 309 }, 310 311 /* ADL-P */ 312 313 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"), 314 XE_RTP_RULES(PLATFORM(ALDERLAKE_P), ENGINE_CLASS(RENDER)), 315 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE), 316 WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 317 RC_SEMA_IDLE_MSG_DISABLE)) 318 }, 319 320 /* DG2 */ 321 322 { XE_RTP_NAME("22013037850"), 323 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 324 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, 325 DISABLE_128B_EVICTION_COMMAND_UDW)) 326 }, 327 { XE_RTP_NAME("22014226127"), 328 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 329 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE)) 330 }, 331 { XE_RTP_NAME("18017747507"), 332 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 333 XE_RTP_ACTIONS(SET(VFG_PREEMPTION_CHICKEN, 334 POLYGON_TRIFAN_LINELOOP_DISABLE)) 335 }, 336 { XE_RTP_NAME("22012826095, 22013059131"), 337 XE_RTP_RULES(SUBPLATFORM(DG2, G11), 338 FUNC(xe_rtp_match_first_render_or_compute)), 339 XE_RTP_ACTIONS(FIELD_SET(LSC_CHICKEN_BIT_0_UDW, 340 MAXREQS_PER_BANK, 341 REG_FIELD_PREP(MAXREQS_PER_BANK, 2))) 342 }, 343 { XE_RTP_NAME("22013059131"), 344 XE_RTP_RULES(SUBPLATFORM(DG2, G11), 345 FUNC(xe_rtp_match_first_render_or_compute)), 346 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, FORCE_1_SUB_MESSAGE_PER_FRAGMENT)) 347 }, 348 { XE_RTP_NAME("14015227452"), 349 XE_RTP_RULES(PLATFORM(DG2), 350 FUNC(xe_rtp_match_first_render_or_compute)), 351 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE)) 352 }, 353 { XE_RTP_NAME("18028616096"), 354 XE_RTP_RULES(PLATFORM(DG2), 355 FUNC(xe_rtp_match_first_render_or_compute)), 356 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3)) 357 }, 358 { XE_RTP_NAME("22015475538"), 359 XE_RTP_RULES(PLATFORM(DG2), 360 FUNC(xe_rtp_match_first_render_or_compute)), 361 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8)) 362 }, 363 { XE_RTP_NAME("22012654132"), 364 XE_RTP_RULES(SUBPLATFORM(DG2, G11), 365 FUNC(xe_rtp_match_first_render_or_compute)), 366 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, ENABLE_PREFETCH_INTO_IC, 367 /* 368 * Register can't be read back for verification on 369 * DG2 due to Wa_14012342262 370 */ 371 .read_mask = 0)) 372 }, 373 { XE_RTP_NAME("1509727124"), 374 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 375 XE_RTP_ACTIONS(SET(SAMPLER_MODE, SC_DISABLE_POWER_OPTIMIZATION_EBB)) 376 }, 377 { XE_RTP_NAME("22012856258"), 378 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 379 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_READ_SUPPRESSION)) 380 }, 381 { XE_RTP_NAME("22010960976, 14013347512"), 382 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 383 XE_RTP_ACTIONS(CLR(XEHP_HDC_CHICKEN0, 384 LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK)) 385 }, 386 { XE_RTP_NAME("14015150844"), 387 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 388 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES, 389 XE_RTP_NOCHECK)) 390 }, 391 392 /* PVC */ 393 394 { XE_RTP_NAME("22014226127"), 395 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)), 396 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE)) 397 }, 398 { XE_RTP_NAME("14015227452"), 399 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)), 400 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE)) 401 }, 402 { XE_RTP_NAME("18020744125"), 403 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute), 404 ENGINE_CLASS(COMPUTE)), 405 XE_RTP_ACTIONS(SET(RING_HWSTAM(RENDER_RING_BASE), ~0)) 406 }, 407 { XE_RTP_NAME("14014999345"), 408 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COMPUTE), 409 GRAPHICS_STEP(B0, C0)), 410 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, DISABLE_ECC)) 411 }, 412 413 /* Xe_LPG */ 414 415 { XE_RTP_NAME("14017856879"), 416 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), 417 FUNC(xe_rtp_match_first_render_or_compute)), 418 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, DIS_FIX_EOT1_FLUSH)) 419 }, 420 { XE_RTP_NAME("14015150844"), 421 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), 422 FUNC(xe_rtp_match_first_render_or_compute)), 423 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES, 424 XE_RTP_NOCHECK)) 425 }, 426 { XE_RTP_NAME("14020495402"), 427 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), 428 FUNC(xe_rtp_match_first_render_or_compute)), 429 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_TDL_SVHS_GATING)) 430 }, 431 432 /* Xe2_LPG */ 433 434 { XE_RTP_NAME("18032247524"), 435 XE_RTP_RULES(GRAPHICS_VERSION(2004), 436 FUNC(xe_rtp_match_first_render_or_compute)), 437 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE)) 438 }, 439 { XE_RTP_NAME("16018712365"), 440 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 441 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS)) 442 }, 443 { XE_RTP_NAME("14018957109"), 444 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 445 FUNC(xe_rtp_match_first_render_or_compute)), 446 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN5, DISABLE_SAMPLE_G_PERFORMANCE)) 447 }, 448 { XE_RTP_NAME("14020338487"), 449 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 450 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS)) 451 }, 452 { XE_RTP_NAME("18034896535, 16021540221"), /* 16021540221: GRAPHICS_STEP(A0, B0) */ 453 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), 454 FUNC(xe_rtp_match_first_render_or_compute)), 455 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH)) 456 }, 457 { XE_RTP_NAME("14019322943"), 458 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 459 FUNC(xe_rtp_match_first_render_or_compute)), 460 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, TGM_WRITE_EOM_FORCE)) 461 }, 462 { XE_RTP_NAME("14018471104"), 463 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 464 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL)) 465 }, 466 { XE_RTP_NAME("16018737384"), 467 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 468 XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS)) 469 }, 470 /* 471 * These two workarounds are the same, just applying to different 472 * engines. Although Wa_18032095049 (for the RCS) isn't required on 473 * all steppings, disabling these reports has no impact for our 474 * driver or the GuC, so we go ahead and treat it the same as 475 * Wa_16021639441 which does apply to all steppings. 476 */ 477 { XE_RTP_NAME("18032095049, 16021639441"), 478 XE_RTP_RULES(GRAPHICS_VERSION(2004)), 479 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), 480 GHWSP_CSB_REPORT_DIS | 481 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, 482 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 483 }, 484 { XE_RTP_NAME("16018610683"), 485 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 486 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, SLM_WMTP_RESTORE)) 487 }, 488 489 /* Xe2_HPG */ 490 491 { XE_RTP_NAME("16018712365"), 492 XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)), 493 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS)) 494 }, 495 { XE_RTP_NAME("16018737384"), 496 XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)), 497 XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS)) 498 }, 499 { XE_RTP_NAME("14019988906"), 500 XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)), 501 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD)) 502 }, 503 { XE_RTP_NAME("14019877138"), 504 XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)), 505 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 506 }, 507 { XE_RTP_NAME("14020338487"), 508 XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)), 509 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS)) 510 }, 511 { XE_RTP_NAME("18032247524"), 512 XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)), 513 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE)) 514 }, 515 { XE_RTP_NAME("14018471104"), 516 XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)), 517 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL)) 518 }, 519 /* 520 * Although this workaround isn't required for the RCS, disabling these 521 * reports has no impact for our driver or the GuC, so we go ahead and 522 * apply this to all engines for simplicity. 523 */ 524 { XE_RTP_NAME("16021639441"), 525 XE_RTP_RULES(GRAPHICS_VERSION(2001)), 526 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), 527 GHWSP_CSB_REPORT_DIS | 528 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, 529 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 530 }, 531 { XE_RTP_NAME("14019811474"), 532 XE_RTP_RULES(GRAPHICS_VERSION(2001), 533 FUNC(xe_rtp_match_first_render_or_compute)), 534 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, WR_REQ_CHAINING_DIS)) 535 }, 536 537 /* Xe2_HPM */ 538 539 { XE_RTP_NAME("16021639441"), 540 XE_RTP_RULES(MEDIA_VERSION(1301)), 541 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), 542 GHWSP_CSB_REPORT_DIS | 543 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, 544 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 545 }, 546 547 {} 548 }; 549 550 static const struct xe_rtp_entry_sr lrc_was[] = { 551 { XE_RTP_NAME("1409342910, 14010698770, 14010443199, 1408979724, 1409178076, 1409207793, 1409217633, 1409252684, 1409347922, 1409142259"), 552 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), 553 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN3, 554 DISABLE_CPS_AWARE_COLOR_PIPE)) 555 }, 556 { XE_RTP_NAME("WaDisableGPGPUMidThreadPreemption"), 557 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), 558 XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(RENDER_RING_BASE), 559 PREEMPT_GPGPU_LEVEL_MASK, 560 PREEMPT_GPGPU_THREAD_GROUP_LEVEL)) 561 }, 562 { XE_RTP_NAME("1806527549"), 563 XE_RTP_RULES(GRAPHICS_VERSION(1200)), 564 XE_RTP_ACTIONS(SET(HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE)) 565 }, 566 { XE_RTP_NAME("1606376872"), 567 XE_RTP_RULES(GRAPHICS_VERSION(1200)), 568 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC)) 569 }, 570 571 /* DG1 */ 572 573 { XE_RTP_NAME("1409044764"), 574 XE_RTP_RULES(PLATFORM(DG1)), 575 XE_RTP_ACTIONS(CLR(COMMON_SLICE_CHICKEN3, 576 DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN)) 577 }, 578 { XE_RTP_NAME("22010493298"), 579 XE_RTP_RULES(PLATFORM(DG1)), 580 XE_RTP_ACTIONS(SET(HIZ_CHICKEN, 581 DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE)) 582 }, 583 584 /* DG2 */ 585 586 { XE_RTP_NAME("16013271637"), 587 XE_RTP_RULES(PLATFORM(DG2)), 588 XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1, 589 MSC_MSAA_REODER_BUF_BYPASS_DISABLE)) 590 }, 591 { XE_RTP_NAME("14014947963"), 592 XE_RTP_RULES(PLATFORM(DG2)), 593 XE_RTP_ACTIONS(FIELD_SET(VF_PREEMPTION, 594 PREEMPTION_VERTEX_COUNT, 595 0x4000)) 596 }, 597 { XE_RTP_NAME("18018764978"), 598 XE_RTP_RULES(PLATFORM(DG2)), 599 XE_RTP_ACTIONS(SET(XEHP_PSS_MODE2, 600 SCOREBOARD_STALL_FLUSH_CONTROL)) 601 }, 602 { XE_RTP_NAME("18019271663"), 603 XE_RTP_RULES(PLATFORM(DG2)), 604 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE)) 605 }, 606 { XE_RTP_NAME("14019877138"), 607 XE_RTP_RULES(PLATFORM(DG2)), 608 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 609 }, 610 611 /* PVC */ 612 613 { XE_RTP_NAME("16017236439"), 614 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COPY), 615 FUNC(xe_rtp_match_even_instance)), 616 XE_RTP_ACTIONS(SET(BCS_SWCTRL(0), 617 BCS_SWCTRL_DISABLE_256B, 618 XE_RTP_ACTION_FLAG(ENGINE_BASE))), 619 }, 620 621 /* Xe_LPG */ 622 623 { XE_RTP_NAME("18019271663"), 624 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)), 625 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE)) 626 }, 627 { XE_RTP_NAME("14019877138"), 628 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), ENGINE_CLASS(RENDER)), 629 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 630 }, 631 632 /* Xe2_LPG */ 633 634 { XE_RTP_NAME("16020518922"), 635 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 636 ENGINE_CLASS(RENDER)), 637 XE_RTP_ACTIONS(SET(FF_MODE, 638 DIS_TE_AUTOSTRIP | 639 DIS_MESH_PARTIAL_AUTOSTRIP | 640 DIS_MESH_AUTOSTRIP), 641 SET(VFLSKPD, 642 DIS_PARTIAL_AUTOSTRIP | 643 DIS_AUTOSTRIP)) 644 }, 645 { XE_RTP_NAME("14019386621"), 646 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 647 XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE)) 648 }, 649 { XE_RTP_NAME("14019877138"), 650 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 651 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 652 }, 653 { XE_RTP_NAME("14020013138"), 654 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 655 ENGINE_CLASS(RENDER)), 656 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS)) 657 }, 658 { XE_RTP_NAME("14019988906"), 659 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 660 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD)) 661 }, 662 { XE_RTP_NAME("16020183090"), 663 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 664 ENGINE_CLASS(RENDER)), 665 XE_RTP_ACTIONS(SET(INSTPM(RENDER_RING_BASE), ENABLE_SEMAPHORE_POLL_BIT)) 666 }, 667 { XE_RTP_NAME("18033852989"), 668 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), ENGINE_CLASS(RENDER)), 669 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST)) 670 }, 671 672 /* Xe2_HPG */ 673 { XE_RTP_NAME("15010599737"), 674 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 675 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN)) 676 }, 677 { XE_RTP_NAME("14019386621"), 678 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 679 XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE)) 680 }, 681 { XE_RTP_NAME("14020756599"), 682 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 683 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS)) 684 }, 685 686 {} 687 }; 688 689 static __maybe_unused const struct xe_rtp_entry oob_was[] = { 690 #include <generated/xe_wa_oob.c> 691 {} 692 }; 693 694 static_assert(ARRAY_SIZE(oob_was) - 1 == _XE_WA_OOB_COUNT); 695 696 __diag_pop(); 697 698 /** 699 * xe_wa_process_oob - process OOB workaround table 700 * @gt: GT instance to process workarounds for 701 * 702 * Process OOB workaround table for this platform, marking in @gt the 703 * workarounds that are active. 704 */ 705 void xe_wa_process_oob(struct xe_gt *gt) 706 { 707 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt); 708 709 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.oob, 710 ARRAY_SIZE(oob_was)); 711 xe_rtp_process(&ctx, oob_was); 712 } 713 714 /** 715 * xe_wa_process_gt - process GT workaround table 716 * @gt: GT instance to process workarounds for 717 * 718 * Process GT workaround table for this platform, saving in @gt all the 719 * workarounds that need to be applied at the GT level. 720 */ 721 void xe_wa_process_gt(struct xe_gt *gt) 722 { 723 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt); 724 725 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.gt, 726 ARRAY_SIZE(gt_was)); 727 xe_rtp_process_to_sr(&ctx, gt_was, >->reg_sr); 728 } 729 EXPORT_SYMBOL_IF_KUNIT(xe_wa_process_gt); 730 731 /** 732 * xe_wa_process_engine - process engine workaround table 733 * @hwe: engine instance to process workarounds for 734 * 735 * Process engine workaround table for this platform, saving in @hwe all the 736 * workarounds that need to be applied at the engine level that match this 737 * engine. 738 */ 739 void xe_wa_process_engine(struct xe_hw_engine *hwe) 740 { 741 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); 742 743 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.engine, 744 ARRAY_SIZE(engine_was)); 745 xe_rtp_process_to_sr(&ctx, engine_was, &hwe->reg_sr); 746 } 747 748 /** 749 * xe_wa_process_lrc - process context workaround table 750 * @hwe: engine instance to process workarounds for 751 * 752 * Process context workaround table for this platform, saving in @hwe all the 753 * workarounds that need to be applied on context restore. These are workarounds 754 * touching registers that are part of the HW context image. 755 */ 756 void xe_wa_process_lrc(struct xe_hw_engine *hwe) 757 { 758 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); 759 760 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.lrc, 761 ARRAY_SIZE(lrc_was)); 762 xe_rtp_process_to_sr(&ctx, lrc_was, &hwe->reg_lrc); 763 } 764 765 /** 766 * xe_wa_init - initialize gt with workaround bookkeeping 767 * @gt: GT instance to initialize 768 * 769 * Returns 0 for success, negative error code otherwise. 770 */ 771 int xe_wa_init(struct xe_gt *gt) 772 { 773 struct xe_device *xe = gt_to_xe(gt); 774 size_t n_oob, n_lrc, n_engine, n_gt, total; 775 unsigned long *p; 776 777 n_gt = BITS_TO_LONGS(ARRAY_SIZE(gt_was)); 778 n_engine = BITS_TO_LONGS(ARRAY_SIZE(engine_was)); 779 n_lrc = BITS_TO_LONGS(ARRAY_SIZE(lrc_was)); 780 n_oob = BITS_TO_LONGS(ARRAY_SIZE(oob_was)); 781 total = n_gt + n_engine + n_lrc + n_oob; 782 783 p = drmm_kzalloc(&xe->drm, sizeof(*p) * total, GFP_KERNEL); 784 if (!p) 785 return -ENOMEM; 786 787 gt->wa_active.gt = p; 788 p += n_gt; 789 gt->wa_active.engine = p; 790 p += n_engine; 791 gt->wa_active.lrc = p; 792 p += n_lrc; 793 gt->wa_active.oob = p; 794 795 return 0; 796 } 797 798 void xe_wa_dump(struct xe_gt *gt, struct drm_printer *p) 799 { 800 size_t idx; 801 802 drm_printf(p, "GT Workarounds\n"); 803 for_each_set_bit(idx, gt->wa_active.gt, ARRAY_SIZE(gt_was)) 804 drm_printf_indent(p, 1, "%s\n", gt_was[idx].name); 805 806 drm_printf(p, "\nEngine Workarounds\n"); 807 for_each_set_bit(idx, gt->wa_active.engine, ARRAY_SIZE(engine_was)) 808 drm_printf_indent(p, 1, "%s\n", engine_was[idx].name); 809 810 drm_printf(p, "\nLRC Workarounds\n"); 811 for_each_set_bit(idx, gt->wa_active.lrc, ARRAY_SIZE(lrc_was)) 812 drm_printf_indent(p, 1, "%s\n", lrc_was[idx].name); 813 814 drm_printf(p, "\nOOB Workarounds\n"); 815 for_each_set_bit(idx, gt->wa_active.oob, ARRAY_SIZE(oob_was)) 816 if (oob_was[idx].name) 817 drm_printf_indent(p, 1, "%s\n", oob_was[idx].name); 818 } 819 820 /* 821 * Apply tile (non-GT, non-display) workarounds. Think very carefully before 822 * adding anything to this function; most workarounds should be implemented 823 * elsewhere. The programming here is primarily for sgunit/soc workarounds, 824 * which are relatively rare. Since the registers these workarounds target are 825 * outside the GT, they should only need to be applied once at device 826 * probe/resume; they will not lose their values on any kind of GT or engine 827 * reset. 828 * 829 * TODO: We may want to move this over to xe_rtp in the future once we have 830 * enough workarounds to justify the work. 831 */ 832 void xe_wa_apply_tile_workarounds(struct xe_tile *tile) 833 { 834 struct xe_gt *mmio = tile->primary_gt; 835 836 if (XE_WA(mmio, 22010954014)) 837 xe_mmio_rmw32(mmio, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS); 838 } 839