xref: /linux/drivers/gpu/drm/xe/xe_vram_freq.c (revision ee057c8c194b9283f4137b253b70e292693a39f0)
1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2024 Intel Corporation
4  */
5 #include <linux/sysfs.h>
6 #include <drm/drm_managed.h>
7 
8 #include "xe_gt_types.h"
9 #include "xe_pcode.h"
10 #include "xe_pcode_api.h"
11 #include "xe_tile.h"
12 #include "xe_tile_sysfs.h"
13 #include "xe_vram_freq.h"
14 
15 /**
16  * DOC: Xe VRAM freq
17  *
18  * Provides sysfs entries for vram frequency in tile
19  *
20  * device/tile#/memory/freq0/max_freq - This is maximum frequency. This value is read-only as it
21  *					is the fixed fuse point P0. It is not the system
22  *					configuration.
23  * device/tile#/memory/freq0/min_freq - This is minimum frequency. This value is read-only as it
24  *					is the fixed fuse point PN. It is not the system
25  *					configuration.
26  */
27 
28 static struct xe_tile *dev_to_tile(struct device *dev)
29 {
30 	return kobj_to_tile(dev->kobj.parent);
31 }
32 
33 static ssize_t max_freq_show(struct device *dev, struct device_attribute *attr,
34 			     char *buf)
35 {
36 	struct xe_tile *tile = dev_to_tile(dev);
37 	struct xe_gt *gt = tile->primary_gt;
38 	u32 val, mbox;
39 	int err;
40 
41 	mbox = REG_FIELD_PREP(PCODE_MB_COMMAND, PCODE_FREQUENCY_CONFIG)
42 		| REG_FIELD_PREP(PCODE_MB_PARAM1, PCODE_MBOX_FC_SC_READ_FUSED_P0)
43 		| REG_FIELD_PREP(PCODE_MB_PARAM2, PCODE_MBOX_DOMAIN_HBM);
44 
45 	err = xe_pcode_read(gt, mbox, &val, NULL);
46 	if (err)
47 		return err;
48 
49 	/* data_out - Fused P0 for domain ID in units of 50 MHz */
50 	val *= 50;
51 
52 	return sysfs_emit(buf, "%u\n", val);
53 }
54 static DEVICE_ATTR_RO(max_freq);
55 
56 static ssize_t min_freq_show(struct device *dev, struct device_attribute *attr,
57 			     char *buf)
58 {
59 	struct xe_tile *tile = dev_to_tile(dev);
60 	struct xe_gt *gt = tile->primary_gt;
61 	u32 val, mbox;
62 	int err;
63 
64 	mbox = REG_FIELD_PREP(PCODE_MB_COMMAND, PCODE_FREQUENCY_CONFIG)
65 		| REG_FIELD_PREP(PCODE_MB_PARAM1, PCODE_MBOX_FC_SC_READ_FUSED_PN)
66 		| REG_FIELD_PREP(PCODE_MB_PARAM2, PCODE_MBOX_DOMAIN_HBM);
67 
68 	err = xe_pcode_read(gt, mbox, &val, NULL);
69 	if (err)
70 		return err;
71 
72 	/* data_out - Fused Pn for domain ID in units of 50 MHz */
73 	val *= 50;
74 
75 	return sysfs_emit(buf, "%u\n", val);
76 }
77 static DEVICE_ATTR_RO(min_freq);
78 
79 static struct attribute *freq_attrs[] = {
80 	&dev_attr_max_freq.attr,
81 	&dev_attr_min_freq.attr,
82 	NULL
83 };
84 
85 static const struct attribute_group freq_group_attrs = {
86 	.name = "freq0",
87 	.attrs = freq_attrs,
88 };
89 
90 static void vram_freq_sysfs_fini(void *arg)
91 {
92 	struct kobject *kobj = arg;
93 
94 	sysfs_remove_group(kobj, &freq_group_attrs);
95 	kobject_put(kobj);
96 }
97 
98 /**
99  * xe_vram_freq_sysfs_init - Initialize vram frequency sysfs component
100  * @tile: Xe Tile object
101  *
102  * It needs to be initialized after the main tile component is ready
103  *
104  * Returns: 0 on success, negative error code on error.
105  */
106 int xe_vram_freq_sysfs_init(struct xe_tile *tile)
107 {
108 	struct xe_device *xe = tile_to_xe(tile);
109 	struct kobject *kobj;
110 	int err;
111 
112 	if (xe->info.platform != XE_PVC)
113 		return 0;
114 
115 	kobj = kobject_create_and_add("memory", tile->sysfs);
116 	if (!kobj)
117 		return -ENOMEM;
118 
119 	err = sysfs_create_group(kobj, &freq_group_attrs);
120 	if (err) {
121 		kobject_put(kobj);
122 		return err;
123 	}
124 
125 	return devm_add_action_or_reset(xe->drm.dev, vram_freq_sysfs_fini, kobj);
126 }
127