1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021-2024 Intel Corporation 4 */ 5 6 #include <linux/pci.h> 7 8 #include <drm/drm_managed.h> 9 #include <drm/drm_print.h> 10 11 #include "regs/xe_bars.h" 12 #include "regs/xe_gt_regs.h" 13 #include "regs/xe_regs.h" 14 #include "xe_assert.h" 15 #include "xe_device.h" 16 #include "xe_force_wake.h" 17 #include "xe_gt_mcr.h" 18 #include "xe_gt_sriov_vf.h" 19 #include "xe_mmio.h" 20 #include "xe_module.h" 21 #include "xe_sriov.h" 22 #include "xe_vram.h" 23 24 #define BAR_SIZE_SHIFT 20 25 26 static void 27 _resize_bar(struct xe_device *xe, int resno, resource_size_t size) 28 { 29 struct pci_dev *pdev = to_pci_dev(xe->drm.dev); 30 int bar_size = pci_rebar_bytes_to_size(size); 31 int ret; 32 33 if (pci_resource_len(pdev, resno)) 34 pci_release_resource(pdev, resno); 35 36 ret = pci_resize_resource(pdev, resno, bar_size); 37 if (ret) { 38 drm_info(&xe->drm, "Failed to resize BAR%d to %dM (%pe). Consider enabling 'Resizable BAR' support in your BIOS\n", 39 resno, 1 << bar_size, ERR_PTR(ret)); 40 return; 41 } 42 43 drm_info(&xe->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size); 44 } 45 46 /* 47 * if force_vram_bar_size is set, attempt to set to the requested size 48 * else set to maximum possible size 49 */ 50 static void resize_vram_bar(struct xe_device *xe) 51 { 52 int force_vram_bar_size = xe_modparam.force_vram_bar_size; 53 struct pci_dev *pdev = to_pci_dev(xe->drm.dev); 54 struct pci_bus *root = pdev->bus; 55 resource_size_t current_size; 56 resource_size_t rebar_size; 57 struct resource *root_res; 58 u32 bar_size_mask; 59 u32 pci_cmd; 60 int i; 61 62 /* gather some relevant info */ 63 current_size = pci_resource_len(pdev, LMEM_BAR); 64 bar_size_mask = pci_rebar_get_possible_sizes(pdev, LMEM_BAR); 65 66 if (!bar_size_mask) 67 return; 68 69 if (force_vram_bar_size < 0) 70 return; 71 72 /* set to a specific size? */ 73 if (force_vram_bar_size) { 74 u32 bar_size_bit; 75 76 rebar_size = force_vram_bar_size * (resource_size_t)SZ_1M; 77 78 bar_size_bit = bar_size_mask & BIT(pci_rebar_bytes_to_size(rebar_size)); 79 80 if (!bar_size_bit) { 81 drm_info(&xe->drm, 82 "Requested size: %lluMiB is not supported by rebar sizes: 0x%x. Leaving default: %lluMiB\n", 83 (u64)rebar_size >> 20, bar_size_mask, (u64)current_size >> 20); 84 return; 85 } 86 87 rebar_size = 1ULL << (__fls(bar_size_bit) + BAR_SIZE_SHIFT); 88 89 if (rebar_size == current_size) 90 return; 91 } else { 92 rebar_size = 1ULL << (__fls(bar_size_mask) + BAR_SIZE_SHIFT); 93 94 /* only resize if larger than current */ 95 if (rebar_size <= current_size) 96 return; 97 } 98 99 drm_info(&xe->drm, "Attempting to resize bar from %lluMiB -> %lluMiB\n", 100 (u64)current_size >> 20, (u64)rebar_size >> 20); 101 102 while (root->parent) 103 root = root->parent; 104 105 pci_bus_for_each_resource(root, root_res, i) { 106 if (root_res && root_res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) && 107 (u64)root_res->start > 0x100000000ul) 108 break; 109 } 110 111 if (!root_res) { 112 drm_info(&xe->drm, "Can't resize VRAM BAR - platform support is missing. Consider enabling 'Resizable BAR' support in your BIOS\n"); 113 return; 114 } 115 116 pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd); 117 pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd & ~PCI_COMMAND_MEMORY); 118 119 _resize_bar(xe, LMEM_BAR, rebar_size); 120 121 pci_assign_unassigned_bus_resources(pdev->bus); 122 pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd); 123 } 124 125 static bool resource_is_valid(struct pci_dev *pdev, int bar) 126 { 127 if (!pci_resource_flags(pdev, bar)) 128 return false; 129 130 if (pci_resource_flags(pdev, bar) & IORESOURCE_UNSET) 131 return false; 132 133 if (!pci_resource_len(pdev, bar)) 134 return false; 135 136 return true; 137 } 138 139 static int determine_lmem_bar_size(struct xe_device *xe) 140 { 141 struct pci_dev *pdev = to_pci_dev(xe->drm.dev); 142 143 if (!resource_is_valid(pdev, LMEM_BAR)) { 144 drm_err(&xe->drm, "pci resource is not valid\n"); 145 return -ENXIO; 146 } 147 148 resize_vram_bar(xe); 149 150 xe->mem.vram.io_start = pci_resource_start(pdev, LMEM_BAR); 151 xe->mem.vram.io_size = pci_resource_len(pdev, LMEM_BAR); 152 if (!xe->mem.vram.io_size) 153 return -EIO; 154 155 /* XXX: Need to change when xe link code is ready */ 156 xe->mem.vram.dpa_base = 0; 157 158 /* set up a map to the total memory area. */ 159 xe->mem.vram.mapping = ioremap_wc(xe->mem.vram.io_start, xe->mem.vram.io_size); 160 161 return 0; 162 } 163 164 static inline u64 get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size) 165 { 166 struct xe_device *xe = gt_to_xe(gt); 167 u64 offset; 168 u32 reg; 169 170 if (GRAPHICS_VER(xe) >= 20) { 171 u64 ccs_size = tile_size / 512; 172 u64 offset_hi, offset_lo; 173 u32 nodes, num_enabled; 174 175 reg = xe_mmio_read32(>->mmio, MIRROR_FUSE3); 176 nodes = REG_FIELD_GET(XE2_NODE_ENABLE_MASK, reg); 177 num_enabled = hweight32(nodes); /* Number of enabled l3 nodes */ 178 179 reg = xe_gt_mcr_unicast_read_any(gt, XE2_FLAT_CCS_BASE_RANGE_LOWER); 180 offset_lo = REG_FIELD_GET(XE2_FLAT_CCS_BASE_LOWER_ADDR_MASK, reg); 181 182 reg = xe_gt_mcr_unicast_read_any(gt, XE2_FLAT_CCS_BASE_RANGE_UPPER); 183 offset_hi = REG_FIELD_GET(XE2_FLAT_CCS_BASE_UPPER_ADDR_MASK, reg); 184 185 offset = offset_hi << 32; /* HW view bits 39:32 */ 186 offset |= offset_lo << 6; /* HW view bits 31:6 */ 187 offset *= num_enabled; /* convert to SW view */ 188 offset = round_up(offset, SZ_128K); /* SW must round up to nearest 128K */ 189 190 /* We don't expect any holes */ 191 xe_assert_msg(xe, offset == (xe_mmio_read64_2x32(>_to_tile(gt)->mmio, GSMBASE) - 192 ccs_size), 193 "Hole between CCS and GSM.\n"); 194 } else { 195 reg = xe_gt_mcr_unicast_read_any(gt, XEHP_FLAT_CCS_BASE_ADDR); 196 offset = (u64)REG_FIELD_GET(XEHP_FLAT_CCS_PTR, reg) * SZ_64K; 197 } 198 199 return offset; 200 } 201 202 /* 203 * tile_vram_size() - Collect vram size and offset information 204 * @tile: tile to get info for 205 * @vram_size: available vram (size - device reserved portions) 206 * @tile_size: actual vram size 207 * @tile_offset: physical start point in the vram address space 208 * 209 * There are 4 places for size information: 210 * - io size (from pci_resource_len of LMEM bar) (only used for small bar and DG1) 211 * - TILEx size (actual vram size) 212 * - GSMBASE offset (TILEx - "stolen") 213 * - CSSBASE offset (TILEx - CSS space necessary) 214 * 215 * CSSBASE is always a lower/smaller offset then GSMBASE. 216 * 217 * The actual available size of memory is to the CCS or GSM base. 218 * NOTE: multi-tile bases will include the tile offset. 219 * 220 */ 221 static int tile_vram_size(struct xe_tile *tile, u64 *vram_size, 222 u64 *tile_size, u64 *tile_offset) 223 { 224 struct xe_device *xe = tile_to_xe(tile); 225 struct xe_gt *gt = tile->primary_gt; 226 unsigned int fw_ref; 227 u64 offset; 228 u32 reg; 229 230 if (IS_SRIOV_VF(xe)) { 231 struct xe_tile *t; 232 int id; 233 234 offset = 0; 235 for_each_tile(t, xe, id) 236 for_each_if(t->id < tile->id) 237 offset += xe_gt_sriov_vf_lmem(t->primary_gt); 238 239 *tile_size = xe_gt_sriov_vf_lmem(gt); 240 *vram_size = *tile_size; 241 *tile_offset = offset; 242 243 return 0; 244 } 245 246 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 247 if (!fw_ref) 248 return -ETIMEDOUT; 249 250 /* actual size */ 251 if (unlikely(xe->info.platform == XE_DG1)) { 252 *tile_size = pci_resource_len(to_pci_dev(xe->drm.dev), LMEM_BAR); 253 *tile_offset = 0; 254 } else { 255 reg = xe_gt_mcr_unicast_read_any(gt, XEHP_TILE_ADDR_RANGE(gt->info.id)); 256 *tile_size = (u64)REG_FIELD_GET(GENMASK(14, 8), reg) * SZ_1G; 257 *tile_offset = (u64)REG_FIELD_GET(GENMASK(7, 1), reg) * SZ_1G; 258 } 259 260 /* minus device usage */ 261 if (xe->info.has_flat_ccs) { 262 offset = get_flat_ccs_offset(gt, *tile_size); 263 } else { 264 offset = xe_mmio_read64_2x32(&tile->mmio, GSMBASE); 265 } 266 267 /* remove the tile offset so we have just the available size */ 268 *vram_size = offset - *tile_offset; 269 270 xe_force_wake_put(gt_to_fw(gt), fw_ref); 271 272 return 0; 273 } 274 275 static void vram_fini(void *arg) 276 { 277 struct xe_device *xe = arg; 278 struct xe_tile *tile; 279 int id; 280 281 if (xe->mem.vram.mapping) 282 iounmap(xe->mem.vram.mapping); 283 284 xe->mem.vram.mapping = NULL; 285 286 for_each_tile(tile, xe, id) 287 tile->mem.vram.mapping = NULL; 288 } 289 290 /** 291 * xe_vram_probe() - Probe VRAM configuration 292 * @xe: the &xe_device 293 * 294 * Collect VRAM size and offset information for all tiles. 295 * 296 * Return: 0 on success, error code on failure 297 */ 298 int xe_vram_probe(struct xe_device *xe) 299 { 300 struct xe_tile *tile; 301 resource_size_t io_size; 302 u64 available_size = 0; 303 u64 total_size = 0; 304 u64 tile_offset; 305 u64 tile_size; 306 u64 vram_size; 307 int err; 308 u8 id; 309 310 if (!IS_DGFX(xe)) 311 return 0; 312 313 /* Get the size of the root tile's vram for later accessibility comparison */ 314 tile = xe_device_get_root_tile(xe); 315 err = tile_vram_size(tile, &vram_size, &tile_size, &tile_offset); 316 if (err) 317 return err; 318 319 err = determine_lmem_bar_size(xe); 320 if (err) 321 return err; 322 323 drm_info(&xe->drm, "VISIBLE VRAM: %pa, %pa\n", &xe->mem.vram.io_start, 324 &xe->mem.vram.io_size); 325 326 io_size = xe->mem.vram.io_size; 327 328 /* tile specific ranges */ 329 for_each_tile(tile, xe, id) { 330 err = tile_vram_size(tile, &vram_size, &tile_size, &tile_offset); 331 if (err) 332 return err; 333 334 tile->mem.vram.actual_physical_size = tile_size; 335 tile->mem.vram.io_start = xe->mem.vram.io_start + tile_offset; 336 tile->mem.vram.io_size = min_t(u64, vram_size, io_size); 337 338 if (!tile->mem.vram.io_size) { 339 drm_err(&xe->drm, "Tile without any CPU visible VRAM. Aborting.\n"); 340 return -ENODEV; 341 } 342 343 tile->mem.vram.dpa_base = xe->mem.vram.dpa_base + tile_offset; 344 tile->mem.vram.usable_size = vram_size; 345 tile->mem.vram.mapping = xe->mem.vram.mapping + tile_offset; 346 347 if (tile->mem.vram.io_size < tile->mem.vram.usable_size) 348 drm_info(&xe->drm, "Small BAR device\n"); 349 drm_info(&xe->drm, "VRAM[%u, %u]: Actual physical size %pa, usable size exclude stolen %pa, CPU accessible size %pa\n", id, 350 tile->id, &tile->mem.vram.actual_physical_size, &tile->mem.vram.usable_size, &tile->mem.vram.io_size); 351 drm_info(&xe->drm, "VRAM[%u, %u]: DPA range: [%pa-%llx], io range: [%pa-%llx]\n", id, tile->id, 352 &tile->mem.vram.dpa_base, tile->mem.vram.dpa_base + (u64)tile->mem.vram.actual_physical_size, 353 &tile->mem.vram.io_start, tile->mem.vram.io_start + (u64)tile->mem.vram.io_size); 354 355 /* calculate total size using tile size to get the correct HW sizing */ 356 total_size += tile_size; 357 available_size += vram_size; 358 359 if (total_size > xe->mem.vram.io_size) { 360 drm_info(&xe->drm, "VRAM: %pa is larger than resource %pa\n", 361 &total_size, &xe->mem.vram.io_size); 362 } 363 364 io_size -= min_t(u64, tile_size, io_size); 365 } 366 367 xe->mem.vram.actual_physical_size = total_size; 368 369 drm_info(&xe->drm, "Total VRAM: %pa, %pa\n", &xe->mem.vram.io_start, 370 &xe->mem.vram.actual_physical_size); 371 drm_info(&xe->drm, "Available VRAM: %pa, %pa\n", &xe->mem.vram.io_start, 372 &available_size); 373 374 return devm_add_action_or_reset(xe->drm.dev, vram_fini, xe); 375 } 376