1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021-2024 Intel Corporation 4 */ 5 6 #include <kunit/visibility.h> 7 #include <linux/pci.h> 8 9 #include <drm/drm_managed.h> 10 #include <drm/drm_print.h> 11 12 #include "regs/xe_bars.h" 13 #include "regs/xe_gt_regs.h" 14 #include "regs/xe_regs.h" 15 #include "xe_assert.h" 16 #include "xe_bo.h" 17 #include "xe_device.h" 18 #include "xe_force_wake.h" 19 #include "xe_gt_mcr.h" 20 #include "xe_mmio.h" 21 #include "xe_sriov.h" 22 #include "xe_tile_sriov_vf.h" 23 #include "xe_ttm_vram_mgr.h" 24 #include "xe_vram.h" 25 #include "xe_vram_types.h" 26 27 static bool resource_is_valid(struct pci_dev *pdev, int bar) 28 { 29 if (!pci_resource_flags(pdev, bar)) 30 return false; 31 32 if (pci_resource_flags(pdev, bar) & IORESOURCE_UNSET) 33 return false; 34 35 if (!pci_resource_len(pdev, bar)) 36 return false; 37 38 return true; 39 } 40 41 static int determine_lmem_bar_size(struct xe_device *xe, struct xe_vram_region *lmem_bar) 42 { 43 struct pci_dev *pdev = to_pci_dev(xe->drm.dev); 44 45 if (!resource_is_valid(pdev, LMEM_BAR)) { 46 drm_err(&xe->drm, "pci resource is not valid\n"); 47 return -ENXIO; 48 } 49 50 lmem_bar->io_start = pci_resource_start(pdev, LMEM_BAR); 51 lmem_bar->io_size = pci_resource_len(pdev, LMEM_BAR); 52 if (!lmem_bar->io_size) 53 return -EIO; 54 55 /* XXX: Need to change when xe link code is ready */ 56 lmem_bar->dpa_base = 0; 57 58 /* set up a map to the total memory area. */ 59 lmem_bar->mapping = devm_ioremap_wc(&pdev->dev, lmem_bar->io_start, lmem_bar->io_size); 60 61 return 0; 62 } 63 64 static int get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size, u64 *poffset) 65 { 66 struct xe_device *xe = gt_to_xe(gt); 67 u64 offset; 68 u32 reg; 69 70 CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FW_GT); 71 if (!fw_ref.domains) 72 return -ETIMEDOUT; 73 74 if (GRAPHICS_VER(xe) >= 20) { 75 u64 ccs_size = tile_size / 512; 76 u64 offset_hi, offset_lo; 77 u32 nodes, num_enabled; 78 79 reg = xe_mmio_read32(>->mmio, MIRROR_FUSE3); 80 nodes = REG_FIELD_GET(XE2_NODE_ENABLE_MASK, reg); 81 num_enabled = hweight32(nodes); /* Number of enabled l3 nodes */ 82 83 reg = xe_gt_mcr_unicast_read_any(gt, XE2_FLAT_CCS_BASE_RANGE_LOWER); 84 offset_lo = REG_FIELD_GET(XE2_FLAT_CCS_BASE_LOWER_ADDR_MASK, reg); 85 86 reg = xe_gt_mcr_unicast_read_any(gt, XE2_FLAT_CCS_BASE_RANGE_UPPER); 87 offset_hi = REG_FIELD_GET(XE2_FLAT_CCS_BASE_UPPER_ADDR_MASK, reg); 88 89 offset = offset_hi << 32; /* HW view bits 39:32 */ 90 offset |= offset_lo << 6; /* HW view bits 31:6 */ 91 offset *= num_enabled; /* convert to SW view */ 92 offset = round_up(offset, SZ_128K); /* SW must round up to nearest 128K */ 93 94 /* We don't expect any holes */ 95 xe_assert_msg(xe, offset == (xe_mmio_read64_2x32(>_to_tile(gt)->mmio, GSMBASE) - 96 ccs_size), 97 "Hole between CCS and GSM.\n"); 98 } else { 99 reg = xe_gt_mcr_unicast_read_any(gt, XEHP_FLAT_CCS_BASE_ADDR); 100 offset = (u64)REG_FIELD_GET(XEHP_FLAT_CCS_PTR, reg) * SZ_64K; 101 } 102 103 *poffset = offset; 104 105 return 0; 106 } 107 108 /* 109 * tile_vram_size() - Collect vram size and offset information 110 * @tile: tile to get info for 111 * @vram_size: available vram (size - device reserved portions) 112 * @tile_size: actual vram size 113 * @tile_offset: physical start point in the vram address space 114 * 115 * There are 4 places for size information: 116 * - io size (from pci_resource_len of LMEM bar) (only used for small bar and DG1) 117 * - TILEx size (actual vram size) 118 * - GSMBASE offset (TILEx - "stolen") 119 * - CSSBASE offset (TILEx - CSS space necessary) 120 * 121 * CSSBASE is always a lower/smaller offset then GSMBASE. 122 * 123 * The actual available size of memory is to the CCS or GSM base. 124 * NOTE: multi-tile bases will include the tile offset. 125 * 126 */ 127 static int tile_vram_size(struct xe_tile *tile, u64 *vram_size, 128 u64 *tile_size, u64 *tile_offset) 129 { 130 struct xe_device *xe = tile_to_xe(tile); 131 struct xe_gt *gt = tile->primary_gt; 132 u64 offset; 133 u32 reg; 134 135 if (IS_SRIOV_VF(xe)) { 136 struct xe_tile *t; 137 int id; 138 139 offset = 0; 140 for_each_tile(t, xe, id) 141 for_each_if(t->id < tile->id) 142 offset += xe_tile_sriov_vf_lmem(t); 143 144 *tile_size = xe_tile_sriov_vf_lmem(tile); 145 *vram_size = *tile_size; 146 *tile_offset = offset; 147 148 return 0; 149 } 150 151 /* actual size */ 152 if (unlikely(xe->info.platform == XE_DG1)) { 153 *tile_size = pci_resource_len(to_pci_dev(xe->drm.dev), LMEM_BAR); 154 *tile_offset = 0; 155 } else { 156 reg = xe_mmio_read32(&tile->mmio, SG_TILE_ADDR_RANGE(tile->id)); 157 *tile_size = (u64)REG_FIELD_GET(GENMASK(17, 8), reg) * SZ_1G; 158 *tile_offset = (u64)REG_FIELD_GET(GENMASK(7, 1), reg) * SZ_1G; 159 } 160 161 /* minus device usage */ 162 if (xe->info.has_flat_ccs) { 163 int ret = get_flat_ccs_offset(gt, *tile_size, &offset); 164 165 if (ret) 166 return ret; 167 } else { 168 offset = xe_mmio_read64_2x32(&tile->mmio, GSMBASE); 169 } 170 171 /* remove the tile offset so we have just the available size */ 172 *vram_size = offset - *tile_offset; 173 174 return 0; 175 } 176 177 static void vram_fini(void *arg) 178 { 179 struct xe_device *xe = arg; 180 struct xe_tile *tile; 181 int id; 182 183 xe->mem.vram->mapping = NULL; 184 185 for_each_tile(tile, xe, id) { 186 tile->mem.vram->mapping = NULL; 187 if (tile->mem.kernel_vram) 188 tile->mem.kernel_vram->mapping = NULL; 189 } 190 } 191 192 struct xe_vram_region *xe_vram_region_alloc(struct xe_device *xe, u8 id, u32 placement) 193 { 194 struct xe_vram_region *vram; 195 struct drm_device *drm = &xe->drm; 196 197 xe_assert(xe, id < xe->info.tile_count); 198 199 vram = drmm_kzalloc(drm, sizeof(*vram), GFP_KERNEL); 200 if (!vram) 201 return NULL; 202 203 vram->xe = xe; 204 vram->id = id; 205 vram->placement = placement; 206 #if defined(CONFIG_DRM_XE_PAGEMAP) 207 vram->migrate = xe->tiles[id].migrate; 208 #endif 209 return vram; 210 } 211 212 static void print_vram_region_info(struct xe_device *xe, struct xe_vram_region *vram) 213 { 214 struct drm_device *drm = &xe->drm; 215 216 if (vram->io_size < vram->usable_size) 217 drm_info(drm, "Small BAR device\n"); 218 219 drm_info(drm, 220 "VRAM[%u]: Actual physical size %pa, usable size exclude stolen %pa, CPU accessible size %pa\n", 221 vram->id, &vram->actual_physical_size, &vram->usable_size, &vram->io_size); 222 drm_info(drm, "VRAM[%u]: DPA range: [%pa-%llx], io range: [%pa-%llx]\n", 223 vram->id, &vram->dpa_base, vram->dpa_base + (u64)vram->actual_physical_size, 224 &vram->io_start, vram->io_start + (u64)vram->io_size); 225 } 226 227 static int vram_region_init(struct xe_device *xe, struct xe_vram_region *vram, 228 struct xe_vram_region *lmem_bar, u64 offset, u64 usable_size, 229 u64 region_size, resource_size_t remain_io_size) 230 { 231 /* Check if VRAM region is already initialized */ 232 if (vram->mapping) 233 return 0; 234 235 vram->actual_physical_size = region_size; 236 vram->io_start = lmem_bar->io_start + offset; 237 vram->io_size = min_t(u64, usable_size, remain_io_size); 238 239 if (!vram->io_size) { 240 drm_err(&xe->drm, "Tile without any CPU visible VRAM. Aborting.\n"); 241 return -ENODEV; 242 } 243 244 vram->dpa_base = lmem_bar->dpa_base + offset; 245 vram->mapping = lmem_bar->mapping + offset; 246 vram->usable_size = usable_size; 247 248 print_vram_region_info(xe, vram); 249 250 return 0; 251 } 252 253 /** 254 * xe_map_resource_to_region - Map ttm resource to vram memory region 255 * @res: The ttm resource 256 * 257 * Get vram memory region using vram memory manager managing this resource 258 * 259 * Returns: pointer to xe_vram_region 260 */ 261 struct xe_vram_region *xe_map_resource_to_region(struct ttm_resource *res) 262 { 263 struct xe_device *xe = ttm_to_xe_device(res->bo->bdev); 264 struct ttm_resource_manager *mgr; 265 struct xe_ttm_vram_mgr *vram_mgr; 266 267 xe_assert(xe, mem_type_is_vram(res->mem_type)); 268 mgr = ttm_manager_type(&xe->ttm, res->mem_type); 269 vram_mgr = to_xe_ttm_vram_mgr(mgr); 270 271 return container_of(vram_mgr, struct xe_vram_region, ttm); 272 } 273 274 /** 275 * xe_vram_probe() - Probe VRAM configuration 276 * @xe: the &xe_device 277 * 278 * Collect VRAM size and offset information for all tiles. 279 * 280 * Return: 0 on success, error code on failure 281 */ 282 int xe_vram_probe(struct xe_device *xe) 283 { 284 struct xe_tile *tile; 285 struct xe_vram_region lmem_bar; 286 resource_size_t remain_io_size; 287 u64 available_size = 0; 288 u64 total_size = 0; 289 int err; 290 u8 id; 291 292 if (!IS_DGFX(xe)) 293 return 0; 294 295 err = determine_lmem_bar_size(xe, &lmem_bar); 296 if (err) 297 return err; 298 drm_info(&xe->drm, "VISIBLE VRAM: %pa, %pa\n", &lmem_bar.io_start, &lmem_bar.io_size); 299 300 remain_io_size = lmem_bar.io_size; 301 302 for_each_tile(tile, xe, id) { 303 u64 region_size; 304 u64 usable_size; 305 u64 tile_offset; 306 307 err = tile_vram_size(tile, &usable_size, ®ion_size, &tile_offset); 308 if (err) 309 return err; 310 311 total_size += region_size; 312 available_size += usable_size; 313 314 err = vram_region_init(xe, tile->mem.vram, &lmem_bar, tile_offset, usable_size, 315 region_size, remain_io_size); 316 if (err) 317 return err; 318 319 if (total_size > lmem_bar.io_size) { 320 drm_info(&xe->drm, "VRAM: %pa is larger than resource %pa\n", 321 &total_size, &lmem_bar.io_size); 322 } 323 324 remain_io_size -= min_t(u64, tile->mem.vram->actual_physical_size, remain_io_size); 325 } 326 327 err = vram_region_init(xe, xe->mem.vram, &lmem_bar, 0, available_size, total_size, 328 lmem_bar.io_size); 329 if (err) 330 return err; 331 332 return devm_add_action_or_reset(xe->drm.dev, vram_fini, xe); 333 } 334 335 /** 336 * xe_vram_region_io_start - Get the IO start of a VRAM region 337 * @vram: the VRAM region 338 * 339 * Return: the IO start of the VRAM region, or 0 if not valid 340 */ 341 resource_size_t xe_vram_region_io_start(const struct xe_vram_region *vram) 342 { 343 return vram ? vram->io_start : 0; 344 } 345 346 /** 347 * xe_vram_region_io_size - Get the IO size of a VRAM region 348 * @vram: the VRAM region 349 * 350 * Return: the IO size of the VRAM region, or 0 if not valid 351 */ 352 resource_size_t xe_vram_region_io_size(const struct xe_vram_region *vram) 353 { 354 return vram ? vram->io_size : 0; 355 } 356 357 /** 358 * xe_vram_region_dpa_base - Get the DPA base of a VRAM region 359 * @vram: the VRAM region 360 * 361 * Return: the DPA base of the VRAM region, or 0 if not valid 362 */ 363 resource_size_t xe_vram_region_dpa_base(const struct xe_vram_region *vram) 364 { 365 return vram ? vram->dpa_base : 0; 366 } 367 368 /** 369 * xe_vram_region_usable_size - Get the usable size of a VRAM region 370 * @vram: the VRAM region 371 * 372 * Return: the usable size of the VRAM region, or 0 if not valid 373 */ 374 resource_size_t xe_vram_region_usable_size(const struct xe_vram_region *vram) 375 { 376 return vram ? vram->usable_size : 0; 377 } 378 379 /** 380 * xe_vram_region_actual_physical_size - Get the actual physical size of a VRAM region 381 * @vram: the VRAM region 382 * 383 * Return: the actual physical size of the VRAM region, or 0 if not valid 384 */ 385 resource_size_t xe_vram_region_actual_physical_size(const struct xe_vram_region *vram) 386 { 387 return vram ? vram->actual_physical_size : 0; 388 } 389 EXPORT_SYMBOL_IF_KUNIT(xe_vram_region_actual_physical_size); 390