1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021-2024 Intel Corporation 4 */ 5 6 #include <kunit/visibility.h> 7 #include <linux/pci.h> 8 9 #include <drm/drm_managed.h> 10 #include <drm/drm_print.h> 11 12 #include "regs/xe_bars.h" 13 #include "regs/xe_gt_regs.h" 14 #include "regs/xe_regs.h" 15 #include "xe_assert.h" 16 #include "xe_bo.h" 17 #include "xe_device.h" 18 #include "xe_force_wake.h" 19 #include "xe_gt_mcr.h" 20 #include "xe_mmio.h" 21 #include "xe_sriov.h" 22 #include "xe_tile_sriov_vf.h" 23 #include "xe_ttm_vram_mgr.h" 24 #include "xe_vram.h" 25 #include "xe_vram_types.h" 26 27 static bool resource_is_valid(struct pci_dev *pdev, int bar) 28 { 29 if (!pci_resource_flags(pdev, bar)) 30 return false; 31 32 if (pci_resource_flags(pdev, bar) & IORESOURCE_UNSET) 33 return false; 34 35 if (!pci_resource_len(pdev, bar)) 36 return false; 37 38 return true; 39 } 40 41 static int determine_lmem_bar_size(struct xe_device *xe, struct xe_vram_region *lmem_bar) 42 { 43 struct pci_dev *pdev = to_pci_dev(xe->drm.dev); 44 45 if (!resource_is_valid(pdev, LMEM_BAR)) { 46 drm_err(&xe->drm, "pci resource is not valid\n"); 47 return -ENXIO; 48 } 49 50 lmem_bar->io_start = pci_resource_start(pdev, LMEM_BAR); 51 lmem_bar->io_size = pci_resource_len(pdev, LMEM_BAR); 52 if (!lmem_bar->io_size) 53 return -EIO; 54 55 /* XXX: Need to change when xe link code is ready */ 56 lmem_bar->dpa_base = 0; 57 58 /* set up a map to the total memory area. */ 59 lmem_bar->mapping = devm_ioremap_wc(&pdev->dev, lmem_bar->io_start, lmem_bar->io_size); 60 61 return 0; 62 } 63 64 static int get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size, u64 *poffset) 65 { 66 struct xe_device *xe = gt_to_xe(gt); 67 u64 offset; 68 u32 reg; 69 70 CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FW_GT); 71 if (!fw_ref.domains) 72 return -ETIMEDOUT; 73 74 if (GRAPHICS_VER(xe) >= 20) { 75 u64 ccs_size = tile_size / 512; 76 u64 offset_hi, offset_lo; 77 u32 nodes, num_enabled; 78 79 reg = xe_mmio_read32(>->mmio, MIRROR_FUSE3); 80 nodes = REG_FIELD_GET(XE2_NODE_ENABLE_MASK, reg); 81 num_enabled = hweight32(nodes); /* Number of enabled l3 nodes */ 82 83 reg = xe_gt_mcr_unicast_read_any(gt, XE2_FLAT_CCS_BASE_RANGE_LOWER); 84 offset_lo = REG_FIELD_GET(XE2_FLAT_CCS_BASE_LOWER_ADDR_MASK, reg); 85 86 reg = xe_gt_mcr_unicast_read_any(gt, XE2_FLAT_CCS_BASE_RANGE_UPPER); 87 offset_hi = REG_FIELD_GET(XE2_FLAT_CCS_BASE_UPPER_ADDR_MASK, reg); 88 89 offset = offset_hi << 32; /* HW view bits 39:32 */ 90 offset |= offset_lo << 6; /* HW view bits 31:6 */ 91 offset *= num_enabled; /* convert to SW view */ 92 93 drm_info(&xe->drm, "FLAT_CCS base:%llx, aligned:%s\n", offset, 94 str_yes_no(IS_ALIGNED(offset, SZ_128K))); 95 96 /* 97 * Everything below this offset is handed to the VRAM 98 * allocator, so it has to be the *first* address the 99 * compression hardware owns, rounded down. Rounding it up 100 * publishes CCS storage as free memory. 101 */ 102 offset = round_down(offset, SZ_4K); 103 104 /* 105 * CCS storage must not run into GSM. The old check compared 106 * the offset against GSMBASE - ccs_size for equality, which 107 * could not fail: that value is 128K aligned, so it agreed 108 * with the rounded-up offset even when the base was not 128K 109 * aligned - exactly the case this fixes. 110 */ 111 xe_assert_msg(xe, offset + ccs_size <= 112 xe_mmio_read64_2x32(>_to_tile(gt)->mmio, GSMBASE), 113 "CCS overlaps GSM.\n"); 114 } else { 115 reg = xe_gt_mcr_unicast_read_any(gt, XEHP_FLAT_CCS_BASE_ADDR); 116 offset = (u64)REG_FIELD_GET(XEHP_FLAT_CCS_PTR, reg) * SZ_64K; 117 } 118 119 *poffset = offset; 120 121 return 0; 122 } 123 124 /* 125 * tile_vram_size() - Collect vram size and offset information 126 * @tile: tile to get info for 127 * @vram_size: available vram (size - device reserved portions) 128 * @tile_size: actual vram size 129 * @tile_offset: physical start point in the vram address space 130 * 131 * There are 4 places for size information: 132 * - io size (from pci_resource_len of LMEM bar) (only used for small bar and DG1) 133 * - TILEx size (actual vram size) 134 * - GSMBASE offset (TILEx - "stolen") 135 * - CSSBASE offset (TILEx - CSS space necessary) 136 * 137 * CSSBASE is always a lower/smaller offset then GSMBASE. 138 * 139 * The actual available size of memory is to the CCS or GSM base. 140 * NOTE: multi-tile bases will include the tile offset. 141 * 142 */ 143 static int tile_vram_size(struct xe_tile *tile, u64 *vram_size, 144 u64 *tile_size, u64 *tile_offset) 145 { 146 struct xe_device *xe = tile_to_xe(tile); 147 struct xe_gt *gt = tile->primary_gt; 148 u64 offset; 149 u32 reg; 150 151 if (IS_SRIOV_VF(xe)) { 152 struct xe_tile *t; 153 int id; 154 155 offset = 0; 156 for_each_tile(t, xe, id) 157 for_each_if(t->id < tile->id) 158 offset += xe_tile_sriov_vf_lmem(t); 159 160 *tile_size = xe_tile_sriov_vf_lmem(tile); 161 *vram_size = *tile_size; 162 *tile_offset = offset; 163 164 return 0; 165 } 166 167 /* actual size */ 168 if (unlikely(xe->info.platform == XE_DG1)) { 169 *tile_size = pci_resource_len(to_pci_dev(xe->drm.dev), LMEM_BAR); 170 *tile_offset = 0; 171 } else { 172 reg = xe_mmio_read32(&tile->mmio, SG_TILE_ADDR_RANGE(tile->id)); 173 *tile_size = (u64)REG_FIELD_GET(GENMASK(17, 8), reg) * SZ_1G; 174 *tile_offset = (u64)REG_FIELD_GET(GENMASK(7, 1), reg) * SZ_1G; 175 } 176 177 /* minus device usage */ 178 if (xe->info.has_flat_ccs) { 179 int ret = get_flat_ccs_offset(gt, *tile_size, &offset); 180 181 if (ret) 182 return ret; 183 } else { 184 offset = xe_mmio_read64_2x32(&tile->mmio, GSMBASE); 185 } 186 187 /* remove the tile offset so we have just the available size */ 188 *vram_size = offset - *tile_offset; 189 190 return 0; 191 } 192 193 static void vram_fini(void *arg) 194 { 195 struct xe_device *xe = arg; 196 struct xe_tile *tile; 197 int id; 198 199 xe->mem.vram->mapping = NULL; 200 201 for_each_tile(tile, xe, id) { 202 tile->mem.vram->mapping = NULL; 203 if (tile->mem.kernel_vram) 204 tile->mem.kernel_vram->mapping = NULL; 205 } 206 } 207 208 struct xe_vram_region *xe_vram_region_alloc(struct xe_device *xe, u8 id, u32 placement) 209 { 210 struct xe_vram_region *vram; 211 struct drm_device *drm = &xe->drm; 212 213 xe_assert(xe, id < xe->info.tile_count); 214 215 vram = drmm_kzalloc(drm, sizeof(*vram), GFP_KERNEL); 216 if (!vram) 217 return NULL; 218 219 vram->xe = xe; 220 vram->id = id; 221 vram->placement = placement; 222 #if defined(CONFIG_DRM_XE_PAGEMAP) 223 vram->migrate = xe->tiles[id].migrate; 224 #endif 225 return vram; 226 } 227 228 static void print_vram_region_info(struct xe_device *xe, struct xe_vram_region *vram) 229 { 230 struct drm_device *drm = &xe->drm; 231 232 if (vram->io_size < vram->usable_size) 233 drm_info(drm, "Small BAR device\n"); 234 235 drm_info(drm, 236 "VRAM[%u]: Actual physical size %pa, usable size exclude stolen %pa, CPU accessible size %pa\n", 237 vram->id, &vram->actual_physical_size, &vram->usable_size, &vram->io_size); 238 drm_info(drm, "VRAM[%u]: DPA range: [%pa-%llx], io range: [%pa-%llx]\n", 239 vram->id, &vram->dpa_base, vram->dpa_base + (u64)vram->actual_physical_size, 240 &vram->io_start, vram->io_start + (u64)vram->io_size); 241 } 242 243 static int vram_region_init(struct xe_device *xe, struct xe_vram_region *vram, 244 struct xe_vram_region *lmem_bar, u64 offset, u64 usable_size, 245 u64 region_size, resource_size_t remain_io_size) 246 { 247 /* Check if VRAM region is already initialized */ 248 if (vram->mapping) 249 return 0; 250 251 vram->actual_physical_size = region_size; 252 vram->io_start = lmem_bar->io_start + offset; 253 vram->io_size = min_t(u64, usable_size, remain_io_size); 254 255 if (!vram->io_size) { 256 drm_err(&xe->drm, "Tile without any CPU visible VRAM. Aborting.\n"); 257 return -ENODEV; 258 } 259 260 vram->dpa_base = lmem_bar->dpa_base + offset; 261 vram->mapping = lmem_bar->mapping + offset; 262 vram->usable_size = usable_size; 263 264 print_vram_region_info(xe, vram); 265 266 return 0; 267 } 268 269 /** 270 * xe_map_resource_to_region - Map ttm resource to vram memory region 271 * @res: The ttm resource 272 * 273 * Get vram memory region using vram memory manager managing this resource 274 * 275 * Returns: pointer to xe_vram_region 276 */ 277 struct xe_vram_region *xe_map_resource_to_region(struct ttm_resource *res) 278 { 279 struct xe_device *xe = ttm_to_xe_device(res->bo->bdev); 280 struct ttm_resource_manager *mgr; 281 struct xe_ttm_vram_mgr *vram_mgr; 282 283 xe_assert(xe, mem_type_is_vram(res->mem_type)); 284 mgr = ttm_manager_type(&xe->ttm, res->mem_type); 285 vram_mgr = to_xe_ttm_vram_mgr(mgr); 286 287 return container_of(vram_mgr, struct xe_vram_region, ttm); 288 } 289 290 /** 291 * xe_vram_probe() - Probe VRAM configuration 292 * @xe: the &xe_device 293 * 294 * Collect VRAM size and offset information for all tiles. 295 * 296 * Return: 0 on success, error code on failure 297 */ 298 int xe_vram_probe(struct xe_device *xe) 299 { 300 struct xe_tile *tile; 301 struct xe_vram_region lmem_bar; 302 resource_size_t remain_io_size; 303 u64 available_size = 0; 304 u64 total_size = 0; 305 int err; 306 u8 id; 307 308 if (!IS_DGFX(xe)) 309 return 0; 310 311 err = determine_lmem_bar_size(xe, &lmem_bar); 312 if (err) 313 return err; 314 drm_info(&xe->drm, "VISIBLE VRAM: %pa, %pa\n", &lmem_bar.io_start, &lmem_bar.io_size); 315 316 remain_io_size = lmem_bar.io_size; 317 318 for_each_tile(tile, xe, id) { 319 u64 region_size; 320 u64 usable_size; 321 u64 tile_offset; 322 323 err = tile_vram_size(tile, &usable_size, ®ion_size, &tile_offset); 324 if (err) 325 return err; 326 327 total_size += region_size; 328 available_size += usable_size; 329 330 err = vram_region_init(xe, tile->mem.vram, &lmem_bar, tile_offset, usable_size, 331 region_size, remain_io_size); 332 if (err) 333 return err; 334 335 if (total_size > lmem_bar.io_size) { 336 drm_info(&xe->drm, "VRAM: %pa is larger than resource %pa\n", 337 &total_size, &lmem_bar.io_size); 338 } 339 340 remain_io_size -= min_t(u64, tile->mem.vram->actual_physical_size, remain_io_size); 341 } 342 343 err = vram_region_init(xe, xe->mem.vram, &lmem_bar, 0, available_size, total_size, 344 lmem_bar.io_size); 345 if (err) 346 return err; 347 348 return devm_add_action_or_reset(xe->drm.dev, vram_fini, xe); 349 } 350 351 /** 352 * xe_vram_region_io_start - Get the IO start of a VRAM region 353 * @vram: the VRAM region 354 * 355 * Return: the IO start of the VRAM region, or 0 if not valid 356 */ 357 resource_size_t xe_vram_region_io_start(const struct xe_vram_region *vram) 358 { 359 return vram ? vram->io_start : 0; 360 } 361 362 /** 363 * xe_vram_region_io_size - Get the IO size of a VRAM region 364 * @vram: the VRAM region 365 * 366 * Return: the IO size of the VRAM region, or 0 if not valid 367 */ 368 resource_size_t xe_vram_region_io_size(const struct xe_vram_region *vram) 369 { 370 return vram ? vram->io_size : 0; 371 } 372 373 /** 374 * xe_vram_region_dpa_base - Get the DPA base of a VRAM region 375 * @vram: the VRAM region 376 * 377 * Return: the DPA base of the VRAM region, or 0 if not valid 378 */ 379 resource_size_t xe_vram_region_dpa_base(const struct xe_vram_region *vram) 380 { 381 return vram ? vram->dpa_base : 0; 382 } 383 384 /** 385 * xe_vram_region_usable_size - Get the usable size of a VRAM region 386 * @vram: the VRAM region 387 * 388 * Return: the usable size of the VRAM region, or 0 if not valid 389 */ 390 resource_size_t xe_vram_region_usable_size(const struct xe_vram_region *vram) 391 { 392 return vram ? vram->usable_size : 0; 393 } 394 395 /** 396 * xe_vram_region_actual_physical_size - Get the actual physical size of a VRAM region 397 * @vram: the VRAM region 398 * 399 * Return: the actual physical size of the VRAM region, or 0 if not valid 400 */ 401 resource_size_t xe_vram_region_actual_physical_size(const struct xe_vram_region *vram) 402 { 403 return vram ? vram->actual_physical_size : 0; 404 } 405 EXPORT_SYMBOL_IF_KUNIT(xe_vram_region_actual_physical_size); 406