xref: /linux/drivers/gpu/drm/xe/xe_vm.c (revision 9112fc0109fc0037ac3b8b633a169e78b4e23ca1)
1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2021 Intel Corporation
4  */
5 
6 #include "xe_vm.h"
7 
8 #include <linux/dma-fence-array.h>
9 #include <linux/nospec.h>
10 
11 #include <drm/drm_exec.h>
12 #include <drm/drm_print.h>
13 #include <drm/ttm/ttm_execbuf_util.h>
14 #include <drm/ttm/ttm_tt.h>
15 #include <drm/xe_drm.h>
16 #include <linux/delay.h>
17 #include <linux/kthread.h>
18 #include <linux/mm.h>
19 #include <linux/swap.h>
20 
21 #include "xe_assert.h"
22 #include "xe_bo.h"
23 #include "xe_device.h"
24 #include "xe_drm_client.h"
25 #include "xe_exec_queue.h"
26 #include "xe_gt.h"
27 #include "xe_gt_pagefault.h"
28 #include "xe_gt_tlb_invalidation.h"
29 #include "xe_migrate.h"
30 #include "xe_pat.h"
31 #include "xe_pm.h"
32 #include "xe_preempt_fence.h"
33 #include "xe_pt.h"
34 #include "xe_res_cursor.h"
35 #include "xe_sync.h"
36 #include "xe_trace.h"
37 #include "generated/xe_wa_oob.h"
38 #include "xe_wa.h"
39 
40 static struct drm_gem_object *xe_vm_obj(struct xe_vm *vm)
41 {
42 	return vm->gpuvm.r_obj;
43 }
44 
45 /**
46  * xe_vma_userptr_check_repin() - Advisory check for repin needed
47  * @uvma: The userptr vma
48  *
49  * Check if the userptr vma has been invalidated since last successful
50  * repin. The check is advisory only and can the function can be called
51  * without the vm->userptr.notifier_lock held. There is no guarantee that the
52  * vma userptr will remain valid after a lockless check, so typically
53  * the call needs to be followed by a proper check under the notifier_lock.
54  *
55  * Return: 0 if userptr vma is valid, -EAGAIN otherwise; repin recommended.
56  */
57 int xe_vma_userptr_check_repin(struct xe_userptr_vma *uvma)
58 {
59 	return mmu_interval_check_retry(&uvma->userptr.notifier,
60 					uvma->userptr.notifier_seq) ?
61 		-EAGAIN : 0;
62 }
63 
64 int xe_vma_userptr_pin_pages(struct xe_userptr_vma *uvma)
65 {
66 	struct xe_userptr *userptr = &uvma->userptr;
67 	struct xe_vma *vma = &uvma->vma;
68 	struct xe_vm *vm = xe_vma_vm(vma);
69 	struct xe_device *xe = vm->xe;
70 	const unsigned long num_pages = xe_vma_size(vma) >> PAGE_SHIFT;
71 	struct page **pages;
72 	bool in_kthread = !current->mm;
73 	unsigned long notifier_seq;
74 	int pinned, ret, i;
75 	bool read_only = xe_vma_read_only(vma);
76 
77 	lockdep_assert_held(&vm->lock);
78 	xe_assert(xe, xe_vma_is_userptr(vma));
79 retry:
80 	if (vma->gpuva.flags & XE_VMA_DESTROYED)
81 		return 0;
82 
83 	notifier_seq = mmu_interval_read_begin(&userptr->notifier);
84 	if (notifier_seq == userptr->notifier_seq)
85 		return 0;
86 
87 	pages = kvmalloc_array(num_pages, sizeof(*pages), GFP_KERNEL);
88 	if (!pages)
89 		return -ENOMEM;
90 
91 	if (userptr->sg) {
92 		dma_unmap_sgtable(xe->drm.dev,
93 				  userptr->sg,
94 				  read_only ? DMA_TO_DEVICE :
95 				  DMA_BIDIRECTIONAL, 0);
96 		sg_free_table(userptr->sg);
97 		userptr->sg = NULL;
98 	}
99 
100 	pinned = ret = 0;
101 	if (in_kthread) {
102 		if (!mmget_not_zero(userptr->notifier.mm)) {
103 			ret = -EFAULT;
104 			goto mm_closed;
105 		}
106 		kthread_use_mm(userptr->notifier.mm);
107 	}
108 
109 	while (pinned < num_pages) {
110 		ret = get_user_pages_fast(xe_vma_userptr(vma) +
111 					  pinned * PAGE_SIZE,
112 					  num_pages - pinned,
113 					  read_only ? 0 : FOLL_WRITE,
114 					  &pages[pinned]);
115 		if (ret < 0)
116 			break;
117 
118 		pinned += ret;
119 		ret = 0;
120 	}
121 
122 	if (in_kthread) {
123 		kthread_unuse_mm(userptr->notifier.mm);
124 		mmput(userptr->notifier.mm);
125 	}
126 mm_closed:
127 	if (ret)
128 		goto out;
129 
130 	ret = sg_alloc_table_from_pages_segment(&userptr->sgt, pages,
131 						pinned, 0,
132 						(u64)pinned << PAGE_SHIFT,
133 						xe_sg_segment_size(xe->drm.dev),
134 						GFP_KERNEL);
135 	if (ret) {
136 		userptr->sg = NULL;
137 		goto out;
138 	}
139 	userptr->sg = &userptr->sgt;
140 
141 	ret = dma_map_sgtable(xe->drm.dev, userptr->sg,
142 			      read_only ? DMA_TO_DEVICE :
143 			      DMA_BIDIRECTIONAL,
144 			      DMA_ATTR_SKIP_CPU_SYNC |
145 			      DMA_ATTR_NO_KERNEL_MAPPING);
146 	if (ret) {
147 		sg_free_table(userptr->sg);
148 		userptr->sg = NULL;
149 		goto out;
150 	}
151 
152 	for (i = 0; i < pinned; ++i) {
153 		if (!read_only) {
154 			lock_page(pages[i]);
155 			set_page_dirty(pages[i]);
156 			unlock_page(pages[i]);
157 		}
158 
159 		mark_page_accessed(pages[i]);
160 	}
161 
162 out:
163 	release_pages(pages, pinned);
164 	kvfree(pages);
165 
166 	if (!(ret < 0)) {
167 		userptr->notifier_seq = notifier_seq;
168 		if (xe_vma_userptr_check_repin(uvma) == -EAGAIN)
169 			goto retry;
170 	}
171 
172 	return ret < 0 ? ret : 0;
173 }
174 
175 static bool preempt_fences_waiting(struct xe_vm *vm)
176 {
177 	struct xe_exec_queue *q;
178 
179 	lockdep_assert_held(&vm->lock);
180 	xe_vm_assert_held(vm);
181 
182 	list_for_each_entry(q, &vm->preempt.exec_queues, compute.link) {
183 		if (!q->compute.pfence ||
184 		    (q->compute.pfence && test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
185 						   &q->compute.pfence->flags))) {
186 			return true;
187 		}
188 	}
189 
190 	return false;
191 }
192 
193 static void free_preempt_fences(struct list_head *list)
194 {
195 	struct list_head *link, *next;
196 
197 	list_for_each_safe(link, next, list)
198 		xe_preempt_fence_free(to_preempt_fence_from_link(link));
199 }
200 
201 static int alloc_preempt_fences(struct xe_vm *vm, struct list_head *list,
202 				unsigned int *count)
203 {
204 	lockdep_assert_held(&vm->lock);
205 	xe_vm_assert_held(vm);
206 
207 	if (*count >= vm->preempt.num_exec_queues)
208 		return 0;
209 
210 	for (; *count < vm->preempt.num_exec_queues; ++(*count)) {
211 		struct xe_preempt_fence *pfence = xe_preempt_fence_alloc();
212 
213 		if (IS_ERR(pfence))
214 			return PTR_ERR(pfence);
215 
216 		list_move_tail(xe_preempt_fence_link(pfence), list);
217 	}
218 
219 	return 0;
220 }
221 
222 static int wait_for_existing_preempt_fences(struct xe_vm *vm)
223 {
224 	struct xe_exec_queue *q;
225 
226 	xe_vm_assert_held(vm);
227 
228 	list_for_each_entry(q, &vm->preempt.exec_queues, compute.link) {
229 		if (q->compute.pfence) {
230 			long timeout = dma_fence_wait(q->compute.pfence, false);
231 
232 			if (timeout < 0)
233 				return -ETIME;
234 			dma_fence_put(q->compute.pfence);
235 			q->compute.pfence = NULL;
236 		}
237 	}
238 
239 	return 0;
240 }
241 
242 static bool xe_vm_is_idle(struct xe_vm *vm)
243 {
244 	struct xe_exec_queue *q;
245 
246 	xe_vm_assert_held(vm);
247 	list_for_each_entry(q, &vm->preempt.exec_queues, compute.link) {
248 		if (!xe_exec_queue_is_idle(q))
249 			return false;
250 	}
251 
252 	return true;
253 }
254 
255 static void arm_preempt_fences(struct xe_vm *vm, struct list_head *list)
256 {
257 	struct list_head *link;
258 	struct xe_exec_queue *q;
259 
260 	list_for_each_entry(q, &vm->preempt.exec_queues, compute.link) {
261 		struct dma_fence *fence;
262 
263 		link = list->next;
264 		xe_assert(vm->xe, link != list);
265 
266 		fence = xe_preempt_fence_arm(to_preempt_fence_from_link(link),
267 					     q, q->compute.context,
268 					     ++q->compute.seqno);
269 		dma_fence_put(q->compute.pfence);
270 		q->compute.pfence = fence;
271 	}
272 }
273 
274 static int add_preempt_fences(struct xe_vm *vm, struct xe_bo *bo)
275 {
276 	struct xe_exec_queue *q;
277 	int err;
278 
279 	if (!vm->preempt.num_exec_queues)
280 		return 0;
281 
282 	err = xe_bo_lock(bo, true);
283 	if (err)
284 		return err;
285 
286 	err = dma_resv_reserve_fences(bo->ttm.base.resv, vm->preempt.num_exec_queues);
287 	if (err)
288 		goto out_unlock;
289 
290 	list_for_each_entry(q, &vm->preempt.exec_queues, compute.link)
291 		if (q->compute.pfence) {
292 			dma_resv_add_fence(bo->ttm.base.resv,
293 					   q->compute.pfence,
294 					   DMA_RESV_USAGE_BOOKKEEP);
295 		}
296 
297 out_unlock:
298 	xe_bo_unlock(bo);
299 	return err;
300 }
301 
302 static void resume_and_reinstall_preempt_fences(struct xe_vm *vm,
303 						struct drm_exec *exec)
304 {
305 	struct xe_exec_queue *q;
306 
307 	lockdep_assert_held(&vm->lock);
308 	xe_vm_assert_held(vm);
309 
310 	list_for_each_entry(q, &vm->preempt.exec_queues, compute.link) {
311 		q->ops->resume(q);
312 
313 		drm_gpuvm_resv_add_fence(&vm->gpuvm, exec, q->compute.pfence,
314 					 DMA_RESV_USAGE_BOOKKEEP, DMA_RESV_USAGE_BOOKKEEP);
315 	}
316 }
317 
318 int xe_vm_add_compute_exec_queue(struct xe_vm *vm, struct xe_exec_queue *q)
319 {
320 	struct drm_gpuvm_exec vm_exec = {
321 		.vm = &vm->gpuvm,
322 		.flags = DRM_EXEC_INTERRUPTIBLE_WAIT,
323 		.num_fences = 1,
324 	};
325 	struct drm_exec *exec = &vm_exec.exec;
326 	struct dma_fence *pfence;
327 	int err;
328 	bool wait;
329 
330 	xe_assert(vm->xe, xe_vm_in_preempt_fence_mode(vm));
331 
332 	down_write(&vm->lock);
333 	err = drm_gpuvm_exec_lock(&vm_exec);
334 	if (err)
335 		goto out_up_write;
336 
337 	pfence = xe_preempt_fence_create(q, q->compute.context,
338 					 ++q->compute.seqno);
339 	if (!pfence) {
340 		err = -ENOMEM;
341 		goto out_fini;
342 	}
343 
344 	list_add(&q->compute.link, &vm->preempt.exec_queues);
345 	++vm->preempt.num_exec_queues;
346 	q->compute.pfence = pfence;
347 
348 	down_read(&vm->userptr.notifier_lock);
349 
350 	drm_gpuvm_resv_add_fence(&vm->gpuvm, exec, pfence,
351 				 DMA_RESV_USAGE_BOOKKEEP, DMA_RESV_USAGE_BOOKKEEP);
352 
353 	/*
354 	 * Check to see if a preemption on VM is in flight or userptr
355 	 * invalidation, if so trigger this preempt fence to sync state with
356 	 * other preempt fences on the VM.
357 	 */
358 	wait = __xe_vm_userptr_needs_repin(vm) || preempt_fences_waiting(vm);
359 	if (wait)
360 		dma_fence_enable_sw_signaling(pfence);
361 
362 	up_read(&vm->userptr.notifier_lock);
363 
364 out_fini:
365 	drm_exec_fini(exec);
366 out_up_write:
367 	up_write(&vm->lock);
368 
369 	return err;
370 }
371 
372 /**
373  * xe_vm_remove_compute_exec_queue() - Remove compute exec queue from VM
374  * @vm: The VM.
375  * @q: The exec_queue
376  */
377 void xe_vm_remove_compute_exec_queue(struct xe_vm *vm, struct xe_exec_queue *q)
378 {
379 	if (!xe_vm_in_preempt_fence_mode(vm))
380 		return;
381 
382 	down_write(&vm->lock);
383 	list_del(&q->compute.link);
384 	--vm->preempt.num_exec_queues;
385 	if (q->compute.pfence) {
386 		dma_fence_enable_sw_signaling(q->compute.pfence);
387 		dma_fence_put(q->compute.pfence);
388 		q->compute.pfence = NULL;
389 	}
390 	up_write(&vm->lock);
391 }
392 
393 /**
394  * __xe_vm_userptr_needs_repin() - Check whether the VM does have userptrs
395  * that need repinning.
396  * @vm: The VM.
397  *
398  * This function checks for whether the VM has userptrs that need repinning,
399  * and provides a release-type barrier on the userptr.notifier_lock after
400  * checking.
401  *
402  * Return: 0 if there are no userptrs needing repinning, -EAGAIN if there are.
403  */
404 int __xe_vm_userptr_needs_repin(struct xe_vm *vm)
405 {
406 	lockdep_assert_held_read(&vm->userptr.notifier_lock);
407 
408 	return (list_empty(&vm->userptr.repin_list) &&
409 		list_empty(&vm->userptr.invalidated)) ? 0 : -EAGAIN;
410 }
411 
412 #define XE_VM_REBIND_RETRY_TIMEOUT_MS 1000
413 
414 static void xe_vm_kill(struct xe_vm *vm)
415 {
416 	struct xe_exec_queue *q;
417 
418 	lockdep_assert_held(&vm->lock);
419 
420 	xe_vm_lock(vm, false);
421 	vm->flags |= XE_VM_FLAG_BANNED;
422 	trace_xe_vm_kill(vm);
423 
424 	list_for_each_entry(q, &vm->preempt.exec_queues, compute.link)
425 		q->ops->kill(q);
426 	xe_vm_unlock(vm);
427 
428 	/* TODO: Inform user the VM is banned */
429 }
430 
431 /**
432  * xe_vm_validate_should_retry() - Whether to retry after a validate error.
433  * @exec: The drm_exec object used for locking before validation.
434  * @err: The error returned from ttm_bo_validate().
435  * @end: A ktime_t cookie that should be set to 0 before first use and
436  * that should be reused on subsequent calls.
437  *
438  * With multiple active VMs, under memory pressure, it is possible that
439  * ttm_bo_validate() run into -EDEADLK and in such case returns -ENOMEM.
440  * Until ttm properly handles locking in such scenarios, best thing the
441  * driver can do is retry with a timeout. Check if that is necessary, and
442  * if so unlock the drm_exec's objects while keeping the ticket to prepare
443  * for a rerun.
444  *
445  * Return: true if a retry after drm_exec_init() is recommended;
446  * false otherwise.
447  */
448 bool xe_vm_validate_should_retry(struct drm_exec *exec, int err, ktime_t *end)
449 {
450 	ktime_t cur;
451 
452 	if (err != -ENOMEM)
453 		return false;
454 
455 	cur = ktime_get();
456 	*end = *end ? : ktime_add_ms(cur, XE_VM_REBIND_RETRY_TIMEOUT_MS);
457 	if (!ktime_before(cur, *end))
458 		return false;
459 
460 	msleep(20);
461 	return true;
462 }
463 
464 static int xe_gpuvm_validate(struct drm_gpuvm_bo *vm_bo, struct drm_exec *exec)
465 {
466 	struct xe_vm *vm = gpuvm_to_vm(vm_bo->vm);
467 	struct drm_gpuva *gpuva;
468 	int ret;
469 
470 	lockdep_assert_held(&vm->lock);
471 	drm_gpuvm_bo_for_each_va(gpuva, vm_bo)
472 		list_move_tail(&gpuva_to_vma(gpuva)->combined_links.rebind,
473 			       &vm->rebind_list);
474 
475 	ret = xe_bo_validate(gem_to_xe_bo(vm_bo->obj), vm, false);
476 	if (ret)
477 		return ret;
478 
479 	vm_bo->evicted = false;
480 	return 0;
481 }
482 
483 static int xe_preempt_work_begin(struct drm_exec *exec, struct xe_vm *vm,
484 				 bool *done)
485 {
486 	int err;
487 
488 	/*
489 	 * 1 fence for each preempt fence plus a fence for each tile from a
490 	 * possible rebind
491 	 */
492 	err = drm_gpuvm_prepare_vm(&vm->gpuvm, exec, vm->preempt.num_exec_queues +
493 				   vm->xe->info.tile_count);
494 	if (err)
495 		return err;
496 
497 	if (xe_vm_is_idle(vm)) {
498 		vm->preempt.rebind_deactivated = true;
499 		*done = true;
500 		return 0;
501 	}
502 
503 	if (!preempt_fences_waiting(vm)) {
504 		*done = true;
505 		return 0;
506 	}
507 
508 	err = drm_gpuvm_prepare_objects(&vm->gpuvm, exec, vm->preempt.num_exec_queues);
509 	if (err)
510 		return err;
511 
512 	err = wait_for_existing_preempt_fences(vm);
513 	if (err)
514 		return err;
515 
516 	return drm_gpuvm_validate(&vm->gpuvm, exec);
517 }
518 
519 static void preempt_rebind_work_func(struct work_struct *w)
520 {
521 	struct xe_vm *vm = container_of(w, struct xe_vm, preempt.rebind_work);
522 	struct drm_exec exec;
523 	struct dma_fence *rebind_fence;
524 	unsigned int fence_count = 0;
525 	LIST_HEAD(preempt_fences);
526 	ktime_t end = 0;
527 	int err = 0;
528 	long wait;
529 	int __maybe_unused tries = 0;
530 
531 	xe_assert(vm->xe, xe_vm_in_preempt_fence_mode(vm));
532 	trace_xe_vm_rebind_worker_enter(vm);
533 
534 	down_write(&vm->lock);
535 
536 	if (xe_vm_is_closed_or_banned(vm)) {
537 		up_write(&vm->lock);
538 		trace_xe_vm_rebind_worker_exit(vm);
539 		return;
540 	}
541 
542 retry:
543 	if (xe_vm_userptr_check_repin(vm)) {
544 		err = xe_vm_userptr_pin(vm);
545 		if (err)
546 			goto out_unlock_outer;
547 	}
548 
549 	drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);
550 
551 	drm_exec_until_all_locked(&exec) {
552 		bool done = false;
553 
554 		err = xe_preempt_work_begin(&exec, vm, &done);
555 		drm_exec_retry_on_contention(&exec);
556 		if (err || done) {
557 			drm_exec_fini(&exec);
558 			if (err && xe_vm_validate_should_retry(&exec, err, &end))
559 				err = -EAGAIN;
560 
561 			goto out_unlock_outer;
562 		}
563 	}
564 
565 	err = alloc_preempt_fences(vm, &preempt_fences, &fence_count);
566 	if (err)
567 		goto out_unlock;
568 
569 	rebind_fence = xe_vm_rebind(vm, true);
570 	if (IS_ERR(rebind_fence)) {
571 		err = PTR_ERR(rebind_fence);
572 		goto out_unlock;
573 	}
574 
575 	if (rebind_fence) {
576 		dma_fence_wait(rebind_fence, false);
577 		dma_fence_put(rebind_fence);
578 	}
579 
580 	/* Wait on munmap style VM unbinds */
581 	wait = dma_resv_wait_timeout(xe_vm_resv(vm),
582 				     DMA_RESV_USAGE_KERNEL,
583 				     false, MAX_SCHEDULE_TIMEOUT);
584 	if (wait <= 0) {
585 		err = -ETIME;
586 		goto out_unlock;
587 	}
588 
589 #define retry_required(__tries, __vm) \
590 	(IS_ENABLED(CONFIG_DRM_XE_USERPTR_INVAL_INJECT) ? \
591 	(!(__tries)++ || __xe_vm_userptr_needs_repin(__vm)) : \
592 	__xe_vm_userptr_needs_repin(__vm))
593 
594 	down_read(&vm->userptr.notifier_lock);
595 	if (retry_required(tries, vm)) {
596 		up_read(&vm->userptr.notifier_lock);
597 		err = -EAGAIN;
598 		goto out_unlock;
599 	}
600 
601 #undef retry_required
602 
603 	spin_lock(&vm->xe->ttm.lru_lock);
604 	ttm_lru_bulk_move_tail(&vm->lru_bulk_move);
605 	spin_unlock(&vm->xe->ttm.lru_lock);
606 
607 	/* Point of no return. */
608 	arm_preempt_fences(vm, &preempt_fences);
609 	resume_and_reinstall_preempt_fences(vm, &exec);
610 	up_read(&vm->userptr.notifier_lock);
611 
612 out_unlock:
613 	drm_exec_fini(&exec);
614 out_unlock_outer:
615 	if (err == -EAGAIN) {
616 		trace_xe_vm_rebind_worker_retry(vm);
617 		goto retry;
618 	}
619 
620 	if (err) {
621 		drm_warn(&vm->xe->drm, "VM worker error: %d\n", err);
622 		xe_vm_kill(vm);
623 	}
624 	up_write(&vm->lock);
625 
626 	free_preempt_fences(&preempt_fences);
627 
628 	trace_xe_vm_rebind_worker_exit(vm);
629 }
630 
631 static bool vma_userptr_invalidate(struct mmu_interval_notifier *mni,
632 				   const struct mmu_notifier_range *range,
633 				   unsigned long cur_seq)
634 {
635 	struct xe_userptr *userptr = container_of(mni, typeof(*userptr), notifier);
636 	struct xe_userptr_vma *uvma = container_of(userptr, typeof(*uvma), userptr);
637 	struct xe_vma *vma = &uvma->vma;
638 	struct xe_vm *vm = xe_vma_vm(vma);
639 	struct dma_resv_iter cursor;
640 	struct dma_fence *fence;
641 	long err;
642 
643 	xe_assert(vm->xe, xe_vma_is_userptr(vma));
644 	trace_xe_vma_userptr_invalidate(vma);
645 
646 	if (!mmu_notifier_range_blockable(range))
647 		return false;
648 
649 	down_write(&vm->userptr.notifier_lock);
650 	mmu_interval_set_seq(mni, cur_seq);
651 
652 	/* No need to stop gpu access if the userptr is not yet bound. */
653 	if (!userptr->initial_bind) {
654 		up_write(&vm->userptr.notifier_lock);
655 		return true;
656 	}
657 
658 	/*
659 	 * Tell exec and rebind worker they need to repin and rebind this
660 	 * userptr.
661 	 */
662 	if (!xe_vm_in_fault_mode(vm) &&
663 	    !(vma->gpuva.flags & XE_VMA_DESTROYED) && vma->tile_present) {
664 		spin_lock(&vm->userptr.invalidated_lock);
665 		list_move_tail(&userptr->invalidate_link,
666 			       &vm->userptr.invalidated);
667 		spin_unlock(&vm->userptr.invalidated_lock);
668 	}
669 
670 	up_write(&vm->userptr.notifier_lock);
671 
672 	/*
673 	 * Preempt fences turn into schedule disables, pipeline these.
674 	 * Note that even in fault mode, we need to wait for binds and
675 	 * unbinds to complete, and those are attached as BOOKMARK fences
676 	 * to the vm.
677 	 */
678 	dma_resv_iter_begin(&cursor, xe_vm_resv(vm),
679 			    DMA_RESV_USAGE_BOOKKEEP);
680 	dma_resv_for_each_fence_unlocked(&cursor, fence)
681 		dma_fence_enable_sw_signaling(fence);
682 	dma_resv_iter_end(&cursor);
683 
684 	err = dma_resv_wait_timeout(xe_vm_resv(vm),
685 				    DMA_RESV_USAGE_BOOKKEEP,
686 				    false, MAX_SCHEDULE_TIMEOUT);
687 	XE_WARN_ON(err <= 0);
688 
689 	if (xe_vm_in_fault_mode(vm)) {
690 		err = xe_vm_invalidate_vma(vma);
691 		XE_WARN_ON(err);
692 	}
693 
694 	trace_xe_vma_userptr_invalidate_complete(vma);
695 
696 	return true;
697 }
698 
699 static const struct mmu_interval_notifier_ops vma_userptr_notifier_ops = {
700 	.invalidate = vma_userptr_invalidate,
701 };
702 
703 int xe_vm_userptr_pin(struct xe_vm *vm)
704 {
705 	struct xe_userptr_vma *uvma, *next;
706 	int err = 0;
707 	LIST_HEAD(tmp_evict);
708 
709 	lockdep_assert_held_write(&vm->lock);
710 
711 	/* Collect invalidated userptrs */
712 	spin_lock(&vm->userptr.invalidated_lock);
713 	list_for_each_entry_safe(uvma, next, &vm->userptr.invalidated,
714 				 userptr.invalidate_link) {
715 		list_del_init(&uvma->userptr.invalidate_link);
716 		list_move_tail(&uvma->userptr.repin_link,
717 			       &vm->userptr.repin_list);
718 	}
719 	spin_unlock(&vm->userptr.invalidated_lock);
720 
721 	/* Pin and move to temporary list */
722 	list_for_each_entry_safe(uvma, next, &vm->userptr.repin_list,
723 				 userptr.repin_link) {
724 		err = xe_vma_userptr_pin_pages(uvma);
725 		if (err < 0)
726 			return err;
727 
728 		list_del_init(&uvma->userptr.repin_link);
729 		list_move_tail(&uvma->vma.combined_links.rebind, &vm->rebind_list);
730 	}
731 
732 	return 0;
733 }
734 
735 /**
736  * xe_vm_userptr_check_repin() - Check whether the VM might have userptrs
737  * that need repinning.
738  * @vm: The VM.
739  *
740  * This function does an advisory check for whether the VM has userptrs that
741  * need repinning.
742  *
743  * Return: 0 if there are no indications of userptrs needing repinning,
744  * -EAGAIN if there are.
745  */
746 int xe_vm_userptr_check_repin(struct xe_vm *vm)
747 {
748 	return (list_empty_careful(&vm->userptr.repin_list) &&
749 		list_empty_careful(&vm->userptr.invalidated)) ? 0 : -EAGAIN;
750 }
751 
752 static struct dma_fence *
753 xe_vm_bind_vma(struct xe_vma *vma, struct xe_exec_queue *q,
754 	       struct xe_sync_entry *syncs, u32 num_syncs,
755 	       bool first_op, bool last_op);
756 
757 struct dma_fence *xe_vm_rebind(struct xe_vm *vm, bool rebind_worker)
758 {
759 	struct dma_fence *fence = NULL;
760 	struct xe_vma *vma, *next;
761 
762 	lockdep_assert_held(&vm->lock);
763 	if (xe_vm_in_lr_mode(vm) && !rebind_worker)
764 		return NULL;
765 
766 	xe_vm_assert_held(vm);
767 	list_for_each_entry_safe(vma, next, &vm->rebind_list,
768 				 combined_links.rebind) {
769 		xe_assert(vm->xe, vma->tile_present);
770 
771 		list_del_init(&vma->combined_links.rebind);
772 		dma_fence_put(fence);
773 		if (rebind_worker)
774 			trace_xe_vma_rebind_worker(vma);
775 		else
776 			trace_xe_vma_rebind_exec(vma);
777 		fence = xe_vm_bind_vma(vma, NULL, NULL, 0, false, false);
778 		if (IS_ERR(fence))
779 			return fence;
780 	}
781 
782 	return fence;
783 }
784 
785 static void xe_vma_free(struct xe_vma *vma)
786 {
787 	if (xe_vma_is_userptr(vma))
788 		kfree(to_userptr_vma(vma));
789 	else
790 		kfree(vma);
791 }
792 
793 #define VMA_CREATE_FLAG_READ_ONLY	BIT(0)
794 #define VMA_CREATE_FLAG_IS_NULL		BIT(1)
795 
796 static struct xe_vma *xe_vma_create(struct xe_vm *vm,
797 				    struct xe_bo *bo,
798 				    u64 bo_offset_or_userptr,
799 				    u64 start, u64 end,
800 				    u16 pat_index, unsigned int flags)
801 {
802 	struct xe_vma *vma;
803 	struct xe_tile *tile;
804 	u8 id;
805 	bool read_only = (flags & VMA_CREATE_FLAG_READ_ONLY);
806 	bool is_null = (flags & VMA_CREATE_FLAG_IS_NULL);
807 
808 	xe_assert(vm->xe, start < end);
809 	xe_assert(vm->xe, end < vm->size);
810 
811 	/*
812 	 * Allocate and ensure that the xe_vma_is_userptr() return
813 	 * matches what was allocated.
814 	 */
815 	if (!bo && !is_null) {
816 		struct xe_userptr_vma *uvma = kzalloc(sizeof(*uvma), GFP_KERNEL);
817 
818 		if (!uvma)
819 			return ERR_PTR(-ENOMEM);
820 
821 		vma = &uvma->vma;
822 	} else {
823 		vma = kzalloc(sizeof(*vma), GFP_KERNEL);
824 		if (!vma)
825 			return ERR_PTR(-ENOMEM);
826 
827 		if (is_null)
828 			vma->gpuva.flags |= DRM_GPUVA_SPARSE;
829 		if (bo)
830 			vma->gpuva.gem.obj = &bo->ttm.base;
831 	}
832 
833 	INIT_LIST_HEAD(&vma->combined_links.rebind);
834 
835 	INIT_LIST_HEAD(&vma->gpuva.gem.entry);
836 	vma->gpuva.vm = &vm->gpuvm;
837 	vma->gpuva.va.addr = start;
838 	vma->gpuva.va.range = end - start + 1;
839 	if (read_only)
840 		vma->gpuva.flags |= XE_VMA_READ_ONLY;
841 
842 	for_each_tile(tile, vm->xe, id)
843 		vma->tile_mask |= 0x1 << id;
844 
845 	if (GRAPHICS_VER(vm->xe) >= 20 || vm->xe->info.platform == XE_PVC)
846 		vma->gpuva.flags |= XE_VMA_ATOMIC_PTE_BIT;
847 
848 	vma->pat_index = pat_index;
849 
850 	if (bo) {
851 		struct drm_gpuvm_bo *vm_bo;
852 
853 		xe_bo_assert_held(bo);
854 
855 		vm_bo = drm_gpuvm_bo_obtain(vma->gpuva.vm, &bo->ttm.base);
856 		if (IS_ERR(vm_bo)) {
857 			xe_vma_free(vma);
858 			return ERR_CAST(vm_bo);
859 		}
860 
861 		drm_gpuvm_bo_extobj_add(vm_bo);
862 		drm_gem_object_get(&bo->ttm.base);
863 		vma->gpuva.gem.offset = bo_offset_or_userptr;
864 		drm_gpuva_link(&vma->gpuva, vm_bo);
865 		drm_gpuvm_bo_put(vm_bo);
866 	} else /* userptr or null */ {
867 		if (!is_null) {
868 			struct xe_userptr *userptr = &to_userptr_vma(vma)->userptr;
869 			u64 size = end - start + 1;
870 			int err;
871 
872 			INIT_LIST_HEAD(&userptr->invalidate_link);
873 			INIT_LIST_HEAD(&userptr->repin_link);
874 			vma->gpuva.gem.offset = bo_offset_or_userptr;
875 
876 			err = mmu_interval_notifier_insert(&userptr->notifier,
877 							   current->mm,
878 							   xe_vma_userptr(vma), size,
879 							   &vma_userptr_notifier_ops);
880 			if (err) {
881 				xe_vma_free(vma);
882 				return ERR_PTR(err);
883 			}
884 
885 			userptr->notifier_seq = LONG_MAX;
886 		}
887 
888 		xe_vm_get(vm);
889 	}
890 
891 	return vma;
892 }
893 
894 static void xe_vma_destroy_late(struct xe_vma *vma)
895 {
896 	struct xe_vm *vm = xe_vma_vm(vma);
897 	struct xe_device *xe = vm->xe;
898 	bool read_only = xe_vma_read_only(vma);
899 
900 	if (xe_vma_is_userptr(vma)) {
901 		struct xe_userptr *userptr = &to_userptr_vma(vma)->userptr;
902 
903 		if (userptr->sg) {
904 			dma_unmap_sgtable(xe->drm.dev,
905 					  userptr->sg,
906 					  read_only ? DMA_TO_DEVICE :
907 					  DMA_BIDIRECTIONAL, 0);
908 			sg_free_table(userptr->sg);
909 			userptr->sg = NULL;
910 		}
911 
912 		/*
913 		 * Since userptr pages are not pinned, we can't remove
914 		 * the notifer until we're sure the GPU is not accessing
915 		 * them anymore
916 		 */
917 		mmu_interval_notifier_remove(&userptr->notifier);
918 		xe_vm_put(vm);
919 	} else if (xe_vma_is_null(vma)) {
920 		xe_vm_put(vm);
921 	} else {
922 		xe_bo_put(xe_vma_bo(vma));
923 	}
924 
925 	xe_vma_free(vma);
926 }
927 
928 static void vma_destroy_work_func(struct work_struct *w)
929 {
930 	struct xe_vma *vma =
931 		container_of(w, struct xe_vma, destroy_work);
932 
933 	xe_vma_destroy_late(vma);
934 }
935 
936 static void vma_destroy_cb(struct dma_fence *fence,
937 			   struct dma_fence_cb *cb)
938 {
939 	struct xe_vma *vma = container_of(cb, struct xe_vma, destroy_cb);
940 
941 	INIT_WORK(&vma->destroy_work, vma_destroy_work_func);
942 	queue_work(system_unbound_wq, &vma->destroy_work);
943 }
944 
945 static void xe_vma_destroy(struct xe_vma *vma, struct dma_fence *fence)
946 {
947 	struct xe_vm *vm = xe_vma_vm(vma);
948 
949 	lockdep_assert_held_write(&vm->lock);
950 	xe_assert(vm->xe, list_empty(&vma->combined_links.destroy));
951 
952 	if (xe_vma_is_userptr(vma)) {
953 		xe_assert(vm->xe, vma->gpuva.flags & XE_VMA_DESTROYED);
954 
955 		spin_lock(&vm->userptr.invalidated_lock);
956 		list_del(&to_userptr_vma(vma)->userptr.invalidate_link);
957 		spin_unlock(&vm->userptr.invalidated_lock);
958 	} else if (!xe_vma_is_null(vma)) {
959 		xe_bo_assert_held(xe_vma_bo(vma));
960 
961 		drm_gpuva_unlink(&vma->gpuva);
962 	}
963 
964 	xe_vm_assert_held(vm);
965 	if (fence) {
966 		int ret = dma_fence_add_callback(fence, &vma->destroy_cb,
967 						 vma_destroy_cb);
968 
969 		if (ret) {
970 			XE_WARN_ON(ret != -ENOENT);
971 			xe_vma_destroy_late(vma);
972 		}
973 	} else {
974 		xe_vma_destroy_late(vma);
975 	}
976 }
977 
978 /**
979  * xe_vm_prepare_vma() - drm_exec utility to lock a vma
980  * @exec: The drm_exec object we're currently locking for.
981  * @vma: The vma for witch we want to lock the vm resv and any attached
982  * object's resv.
983  * @num_shared: The number of dma-fence slots to pre-allocate in the
984  * objects' reservation objects.
985  *
986  * Return: 0 on success, negative error code on error. In particular
987  * may return -EDEADLK on WW transaction contention and -EINTR if
988  * an interruptible wait is terminated by a signal.
989  */
990 int xe_vm_prepare_vma(struct drm_exec *exec, struct xe_vma *vma,
991 		      unsigned int num_shared)
992 {
993 	struct xe_vm *vm = xe_vma_vm(vma);
994 	struct xe_bo *bo = xe_vma_bo(vma);
995 	int err;
996 
997 	XE_WARN_ON(!vm);
998 	if (num_shared)
999 		err = drm_exec_prepare_obj(exec, xe_vm_obj(vm), num_shared);
1000 	else
1001 		err = drm_exec_lock_obj(exec, xe_vm_obj(vm));
1002 	if (!err && bo && !bo->vm) {
1003 		if (num_shared)
1004 			err = drm_exec_prepare_obj(exec, &bo->ttm.base, num_shared);
1005 		else
1006 			err = drm_exec_lock_obj(exec, &bo->ttm.base);
1007 	}
1008 
1009 	return err;
1010 }
1011 
1012 static void xe_vma_destroy_unlocked(struct xe_vma *vma)
1013 {
1014 	struct drm_exec exec;
1015 	int err;
1016 
1017 	drm_exec_init(&exec, 0, 0);
1018 	drm_exec_until_all_locked(&exec) {
1019 		err = xe_vm_prepare_vma(&exec, vma, 0);
1020 		drm_exec_retry_on_contention(&exec);
1021 		if (XE_WARN_ON(err))
1022 			break;
1023 	}
1024 
1025 	xe_vma_destroy(vma, NULL);
1026 
1027 	drm_exec_fini(&exec);
1028 }
1029 
1030 struct xe_vma *
1031 xe_vm_find_overlapping_vma(struct xe_vm *vm, u64 start, u64 range)
1032 {
1033 	struct drm_gpuva *gpuva;
1034 
1035 	lockdep_assert_held(&vm->lock);
1036 
1037 	if (xe_vm_is_closed_or_banned(vm))
1038 		return NULL;
1039 
1040 	xe_assert(vm->xe, start + range <= vm->size);
1041 
1042 	gpuva = drm_gpuva_find_first(&vm->gpuvm, start, range);
1043 
1044 	return gpuva ? gpuva_to_vma(gpuva) : NULL;
1045 }
1046 
1047 static int xe_vm_insert_vma(struct xe_vm *vm, struct xe_vma *vma)
1048 {
1049 	int err;
1050 
1051 	xe_assert(vm->xe, xe_vma_vm(vma) == vm);
1052 	lockdep_assert_held(&vm->lock);
1053 
1054 	err = drm_gpuva_insert(&vm->gpuvm, &vma->gpuva);
1055 	XE_WARN_ON(err);	/* Shouldn't be possible */
1056 
1057 	return err;
1058 }
1059 
1060 static void xe_vm_remove_vma(struct xe_vm *vm, struct xe_vma *vma)
1061 {
1062 	xe_assert(vm->xe, xe_vma_vm(vma) == vm);
1063 	lockdep_assert_held(&vm->lock);
1064 
1065 	drm_gpuva_remove(&vma->gpuva);
1066 	if (vm->usm.last_fault_vma == vma)
1067 		vm->usm.last_fault_vma = NULL;
1068 }
1069 
1070 static struct drm_gpuva_op *xe_vm_op_alloc(void)
1071 {
1072 	struct xe_vma_op *op;
1073 
1074 	op = kzalloc(sizeof(*op), GFP_KERNEL);
1075 
1076 	if (unlikely(!op))
1077 		return NULL;
1078 
1079 	return &op->base;
1080 }
1081 
1082 static void xe_vm_free(struct drm_gpuvm *gpuvm);
1083 
1084 static struct drm_gpuvm_ops gpuvm_ops = {
1085 	.op_alloc = xe_vm_op_alloc,
1086 	.vm_bo_validate = xe_gpuvm_validate,
1087 	.vm_free = xe_vm_free,
1088 };
1089 
1090 static u64 pde_encode_pat_index(struct xe_device *xe, u16 pat_index)
1091 {
1092 	u64 pte = 0;
1093 
1094 	if (pat_index & BIT(0))
1095 		pte |= XE_PPGTT_PTE_PAT0;
1096 
1097 	if (pat_index & BIT(1))
1098 		pte |= XE_PPGTT_PTE_PAT1;
1099 
1100 	return pte;
1101 }
1102 
1103 static u64 pte_encode_pat_index(struct xe_device *xe, u16 pat_index,
1104 				u32 pt_level)
1105 {
1106 	u64 pte = 0;
1107 
1108 	if (pat_index & BIT(0))
1109 		pte |= XE_PPGTT_PTE_PAT0;
1110 
1111 	if (pat_index & BIT(1))
1112 		pte |= XE_PPGTT_PTE_PAT1;
1113 
1114 	if (pat_index & BIT(2)) {
1115 		if (pt_level)
1116 			pte |= XE_PPGTT_PDE_PDPE_PAT2;
1117 		else
1118 			pte |= XE_PPGTT_PTE_PAT2;
1119 	}
1120 
1121 	if (pat_index & BIT(3))
1122 		pte |= XELPG_PPGTT_PTE_PAT3;
1123 
1124 	if (pat_index & (BIT(4)))
1125 		pte |= XE2_PPGTT_PTE_PAT4;
1126 
1127 	return pte;
1128 }
1129 
1130 static u64 pte_encode_ps(u32 pt_level)
1131 {
1132 	XE_WARN_ON(pt_level > MAX_HUGEPTE_LEVEL);
1133 
1134 	if (pt_level == 1)
1135 		return XE_PDE_PS_2M;
1136 	else if (pt_level == 2)
1137 		return XE_PDPE_PS_1G;
1138 
1139 	return 0;
1140 }
1141 
1142 static u64 xelp_pde_encode_bo(struct xe_bo *bo, u64 bo_offset,
1143 			      const u16 pat_index)
1144 {
1145 	struct xe_device *xe = xe_bo_device(bo);
1146 	u64 pde;
1147 
1148 	pde = xe_bo_addr(bo, bo_offset, XE_PAGE_SIZE);
1149 	pde |= XE_PAGE_PRESENT | XE_PAGE_RW;
1150 	pde |= pde_encode_pat_index(xe, pat_index);
1151 
1152 	return pde;
1153 }
1154 
1155 static u64 xelp_pte_encode_bo(struct xe_bo *bo, u64 bo_offset,
1156 			      u16 pat_index, u32 pt_level)
1157 {
1158 	struct xe_device *xe = xe_bo_device(bo);
1159 	u64 pte;
1160 
1161 	pte = xe_bo_addr(bo, bo_offset, XE_PAGE_SIZE);
1162 	pte |= XE_PAGE_PRESENT | XE_PAGE_RW;
1163 	pte |= pte_encode_pat_index(xe, pat_index, pt_level);
1164 	pte |= pte_encode_ps(pt_level);
1165 
1166 	if (xe_bo_is_vram(bo) || xe_bo_is_stolen_devmem(bo))
1167 		pte |= XE_PPGTT_PTE_DM;
1168 
1169 	return pte;
1170 }
1171 
1172 static u64 xelp_pte_encode_vma(u64 pte, struct xe_vma *vma,
1173 			       u16 pat_index, u32 pt_level)
1174 {
1175 	struct xe_device *xe = xe_vma_vm(vma)->xe;
1176 
1177 	pte |= XE_PAGE_PRESENT;
1178 
1179 	if (likely(!xe_vma_read_only(vma)))
1180 		pte |= XE_PAGE_RW;
1181 
1182 	pte |= pte_encode_pat_index(xe, pat_index, pt_level);
1183 	pte |= pte_encode_ps(pt_level);
1184 
1185 	if (unlikely(xe_vma_is_null(vma)))
1186 		pte |= XE_PTE_NULL;
1187 
1188 	return pte;
1189 }
1190 
1191 static u64 xelp_pte_encode_addr(struct xe_device *xe, u64 addr,
1192 				u16 pat_index,
1193 				u32 pt_level, bool devmem, u64 flags)
1194 {
1195 	u64 pte;
1196 
1197 	/* Avoid passing random bits directly as flags */
1198 	xe_assert(xe, !(flags & ~XE_PTE_PS64));
1199 
1200 	pte = addr;
1201 	pte |= XE_PAGE_PRESENT | XE_PAGE_RW;
1202 	pte |= pte_encode_pat_index(xe, pat_index, pt_level);
1203 	pte |= pte_encode_ps(pt_level);
1204 
1205 	if (devmem)
1206 		pte |= XE_PPGTT_PTE_DM;
1207 
1208 	pte |= flags;
1209 
1210 	return pte;
1211 }
1212 
1213 static const struct xe_pt_ops xelp_pt_ops = {
1214 	.pte_encode_bo = xelp_pte_encode_bo,
1215 	.pte_encode_vma = xelp_pte_encode_vma,
1216 	.pte_encode_addr = xelp_pte_encode_addr,
1217 	.pde_encode_bo = xelp_pde_encode_bo,
1218 };
1219 
1220 static void vm_destroy_work_func(struct work_struct *w);
1221 
1222 /**
1223  * xe_vm_create_scratch() - Setup a scratch memory pagetable tree for the
1224  * given tile and vm.
1225  * @xe: xe device.
1226  * @tile: tile to set up for.
1227  * @vm: vm to set up for.
1228  *
1229  * Sets up a pagetable tree with one page-table per level and a single
1230  * leaf PTE. All pagetable entries point to the single page-table or,
1231  * for MAX_HUGEPTE_LEVEL, a NULL huge PTE returning 0 on read and
1232  * writes become NOPs.
1233  *
1234  * Return: 0 on success, negative error code on error.
1235  */
1236 static int xe_vm_create_scratch(struct xe_device *xe, struct xe_tile *tile,
1237 				struct xe_vm *vm)
1238 {
1239 	u8 id = tile->id;
1240 	int i;
1241 
1242 	for (i = MAX_HUGEPTE_LEVEL; i < vm->pt_root[id]->level; i++) {
1243 		vm->scratch_pt[id][i] = xe_pt_create(vm, tile, i);
1244 		if (IS_ERR(vm->scratch_pt[id][i]))
1245 			return PTR_ERR(vm->scratch_pt[id][i]);
1246 
1247 		xe_pt_populate_empty(tile, vm, vm->scratch_pt[id][i]);
1248 	}
1249 
1250 	return 0;
1251 }
1252 
1253 static void xe_vm_free_scratch(struct xe_vm *vm)
1254 {
1255 	struct xe_tile *tile;
1256 	u8 id;
1257 
1258 	if (!xe_vm_has_scratch(vm))
1259 		return;
1260 
1261 	for_each_tile(tile, vm->xe, id) {
1262 		u32 i;
1263 
1264 		if (!vm->pt_root[id])
1265 			continue;
1266 
1267 		for (i = MAX_HUGEPTE_LEVEL; i < vm->pt_root[id]->level; ++i)
1268 			if (vm->scratch_pt[id][i])
1269 				xe_pt_destroy(vm->scratch_pt[id][i], vm->flags, NULL);
1270 	}
1271 }
1272 
1273 struct xe_vm *xe_vm_create(struct xe_device *xe, u32 flags)
1274 {
1275 	struct drm_gem_object *vm_resv_obj;
1276 	struct xe_vm *vm;
1277 	int err, number_tiles = 0;
1278 	struct xe_tile *tile;
1279 	u8 id;
1280 
1281 	vm = kzalloc(sizeof(*vm), GFP_KERNEL);
1282 	if (!vm)
1283 		return ERR_PTR(-ENOMEM);
1284 
1285 	vm->xe = xe;
1286 
1287 	vm->size = 1ull << xe->info.va_bits;
1288 
1289 	vm->flags = flags;
1290 
1291 	init_rwsem(&vm->lock);
1292 
1293 	INIT_LIST_HEAD(&vm->rebind_list);
1294 
1295 	INIT_LIST_HEAD(&vm->userptr.repin_list);
1296 	INIT_LIST_HEAD(&vm->userptr.invalidated);
1297 	init_rwsem(&vm->userptr.notifier_lock);
1298 	spin_lock_init(&vm->userptr.invalidated_lock);
1299 
1300 	INIT_WORK(&vm->destroy_work, vm_destroy_work_func);
1301 
1302 	INIT_LIST_HEAD(&vm->preempt.exec_queues);
1303 	vm->preempt.min_run_period_ms = 10;	/* FIXME: Wire up to uAPI */
1304 
1305 	for_each_tile(tile, xe, id)
1306 		xe_range_fence_tree_init(&vm->rftree[id]);
1307 
1308 	vm->pt_ops = &xelp_pt_ops;
1309 
1310 	if (!(flags & XE_VM_FLAG_MIGRATION))
1311 		xe_device_mem_access_get(xe);
1312 
1313 	vm_resv_obj = drm_gpuvm_resv_object_alloc(&xe->drm);
1314 	if (!vm_resv_obj) {
1315 		err = -ENOMEM;
1316 		goto err_no_resv;
1317 	}
1318 
1319 	drm_gpuvm_init(&vm->gpuvm, "Xe VM", DRM_GPUVM_RESV_PROTECTED, &xe->drm,
1320 		       vm_resv_obj, 0, vm->size, 0, 0, &gpuvm_ops);
1321 
1322 	drm_gem_object_put(vm_resv_obj);
1323 
1324 	err = dma_resv_lock_interruptible(xe_vm_resv(vm), NULL);
1325 	if (err)
1326 		goto err_close;
1327 
1328 	if (IS_DGFX(xe) && xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K)
1329 		vm->flags |= XE_VM_FLAG_64K;
1330 
1331 	for_each_tile(tile, xe, id) {
1332 		if (flags & XE_VM_FLAG_MIGRATION &&
1333 		    tile->id != XE_VM_FLAG_TILE_ID(flags))
1334 			continue;
1335 
1336 		vm->pt_root[id] = xe_pt_create(vm, tile, xe->info.vm_max_level);
1337 		if (IS_ERR(vm->pt_root[id])) {
1338 			err = PTR_ERR(vm->pt_root[id]);
1339 			vm->pt_root[id] = NULL;
1340 			goto err_unlock_close;
1341 		}
1342 	}
1343 
1344 	if (xe_vm_has_scratch(vm)) {
1345 		for_each_tile(tile, xe, id) {
1346 			if (!vm->pt_root[id])
1347 				continue;
1348 
1349 			err = xe_vm_create_scratch(xe, tile, vm);
1350 			if (err)
1351 				goto err_unlock_close;
1352 		}
1353 		vm->batch_invalidate_tlb = true;
1354 	}
1355 
1356 	if (flags & XE_VM_FLAG_LR_MODE) {
1357 		INIT_WORK(&vm->preempt.rebind_work, preempt_rebind_work_func);
1358 		vm->flags |= XE_VM_FLAG_LR_MODE;
1359 		vm->batch_invalidate_tlb = false;
1360 	}
1361 
1362 	/* Fill pt_root after allocating scratch tables */
1363 	for_each_tile(tile, xe, id) {
1364 		if (!vm->pt_root[id])
1365 			continue;
1366 
1367 		xe_pt_populate_empty(tile, vm, vm->pt_root[id]);
1368 	}
1369 	dma_resv_unlock(xe_vm_resv(vm));
1370 
1371 	/* Kernel migration VM shouldn't have a circular loop.. */
1372 	if (!(flags & XE_VM_FLAG_MIGRATION)) {
1373 		for_each_tile(tile, xe, id) {
1374 			struct xe_gt *gt = tile->primary_gt;
1375 			struct xe_vm *migrate_vm;
1376 			struct xe_exec_queue *q;
1377 			u32 create_flags = EXEC_QUEUE_FLAG_VM;
1378 
1379 			if (!vm->pt_root[id])
1380 				continue;
1381 
1382 			migrate_vm = xe_migrate_get_vm(tile->migrate);
1383 			q = xe_exec_queue_create_class(xe, gt, migrate_vm,
1384 						       XE_ENGINE_CLASS_COPY,
1385 						       create_flags);
1386 			xe_vm_put(migrate_vm);
1387 			if (IS_ERR(q)) {
1388 				err = PTR_ERR(q);
1389 				goto err_close;
1390 			}
1391 			vm->q[id] = q;
1392 			number_tiles++;
1393 		}
1394 	}
1395 
1396 	if (number_tiles > 1)
1397 		vm->composite_fence_ctx = dma_fence_context_alloc(1);
1398 
1399 	mutex_lock(&xe->usm.lock);
1400 	if (flags & XE_VM_FLAG_FAULT_MODE)
1401 		xe->usm.num_vm_in_fault_mode++;
1402 	else if (!(flags & XE_VM_FLAG_MIGRATION))
1403 		xe->usm.num_vm_in_non_fault_mode++;
1404 	mutex_unlock(&xe->usm.lock);
1405 
1406 	trace_xe_vm_create(vm);
1407 
1408 	return vm;
1409 
1410 err_unlock_close:
1411 	dma_resv_unlock(xe_vm_resv(vm));
1412 err_close:
1413 	xe_vm_close_and_put(vm);
1414 	return ERR_PTR(err);
1415 
1416 err_no_resv:
1417 	for_each_tile(tile, xe, id)
1418 		xe_range_fence_tree_fini(&vm->rftree[id]);
1419 	kfree(vm);
1420 	if (!(flags & XE_VM_FLAG_MIGRATION))
1421 		xe_device_mem_access_put(xe);
1422 	return ERR_PTR(err);
1423 }
1424 
1425 static void xe_vm_close(struct xe_vm *vm)
1426 {
1427 	down_write(&vm->lock);
1428 	vm->size = 0;
1429 	up_write(&vm->lock);
1430 }
1431 
1432 void xe_vm_close_and_put(struct xe_vm *vm)
1433 {
1434 	LIST_HEAD(contested);
1435 	struct xe_device *xe = vm->xe;
1436 	struct xe_tile *tile;
1437 	struct xe_vma *vma, *next_vma;
1438 	struct drm_gpuva *gpuva, *next;
1439 	u8 id;
1440 
1441 	xe_assert(xe, !vm->preempt.num_exec_queues);
1442 
1443 	xe_vm_close(vm);
1444 	if (xe_vm_in_preempt_fence_mode(vm))
1445 		flush_work(&vm->preempt.rebind_work);
1446 
1447 	down_write(&vm->lock);
1448 	for_each_tile(tile, xe, id) {
1449 		if (vm->q[id])
1450 			xe_exec_queue_last_fence_put(vm->q[id], vm);
1451 	}
1452 	up_write(&vm->lock);
1453 
1454 	for_each_tile(tile, xe, id) {
1455 		if (vm->q[id]) {
1456 			xe_exec_queue_kill(vm->q[id]);
1457 			xe_exec_queue_put(vm->q[id]);
1458 			vm->q[id] = NULL;
1459 		}
1460 	}
1461 
1462 	down_write(&vm->lock);
1463 	xe_vm_lock(vm, false);
1464 	drm_gpuvm_for_each_va_safe(gpuva, next, &vm->gpuvm) {
1465 		vma = gpuva_to_vma(gpuva);
1466 
1467 		if (xe_vma_has_no_bo(vma)) {
1468 			down_read(&vm->userptr.notifier_lock);
1469 			vma->gpuva.flags |= XE_VMA_DESTROYED;
1470 			up_read(&vm->userptr.notifier_lock);
1471 		}
1472 
1473 		xe_vm_remove_vma(vm, vma);
1474 
1475 		/* easy case, remove from VMA? */
1476 		if (xe_vma_has_no_bo(vma) || xe_vma_bo(vma)->vm) {
1477 			list_del_init(&vma->combined_links.rebind);
1478 			xe_vma_destroy(vma, NULL);
1479 			continue;
1480 		}
1481 
1482 		list_move_tail(&vma->combined_links.destroy, &contested);
1483 		vma->gpuva.flags |= XE_VMA_DESTROYED;
1484 	}
1485 
1486 	/*
1487 	 * All vm operations will add shared fences to resv.
1488 	 * The only exception is eviction for a shared object,
1489 	 * but even so, the unbind when evicted would still
1490 	 * install a fence to resv. Hence it's safe to
1491 	 * destroy the pagetables immediately.
1492 	 */
1493 	xe_vm_free_scratch(vm);
1494 
1495 	for_each_tile(tile, xe, id) {
1496 		if (vm->pt_root[id]) {
1497 			xe_pt_destroy(vm->pt_root[id], vm->flags, NULL);
1498 			vm->pt_root[id] = NULL;
1499 		}
1500 	}
1501 	xe_vm_unlock(vm);
1502 
1503 	/*
1504 	 * VM is now dead, cannot re-add nodes to vm->vmas if it's NULL
1505 	 * Since we hold a refcount to the bo, we can remove and free
1506 	 * the members safely without locking.
1507 	 */
1508 	list_for_each_entry_safe(vma, next_vma, &contested,
1509 				 combined_links.destroy) {
1510 		list_del_init(&vma->combined_links.destroy);
1511 		xe_vma_destroy_unlocked(vma);
1512 	}
1513 
1514 	up_write(&vm->lock);
1515 
1516 	mutex_lock(&xe->usm.lock);
1517 	if (vm->flags & XE_VM_FLAG_FAULT_MODE)
1518 		xe->usm.num_vm_in_fault_mode--;
1519 	else if (!(vm->flags & XE_VM_FLAG_MIGRATION))
1520 		xe->usm.num_vm_in_non_fault_mode--;
1521 	mutex_unlock(&xe->usm.lock);
1522 
1523 	for_each_tile(tile, xe, id)
1524 		xe_range_fence_tree_fini(&vm->rftree[id]);
1525 
1526 	xe_vm_put(vm);
1527 }
1528 
1529 static void vm_destroy_work_func(struct work_struct *w)
1530 {
1531 	struct xe_vm *vm =
1532 		container_of(w, struct xe_vm, destroy_work);
1533 	struct xe_device *xe = vm->xe;
1534 	struct xe_tile *tile;
1535 	u8 id;
1536 	void *lookup;
1537 
1538 	/* xe_vm_close_and_put was not called? */
1539 	xe_assert(xe, !vm->size);
1540 
1541 	if (!(vm->flags & XE_VM_FLAG_MIGRATION)) {
1542 		xe_device_mem_access_put(xe);
1543 
1544 		if (xe->info.has_asid && vm->usm.asid) {
1545 			mutex_lock(&xe->usm.lock);
1546 			lookup = xa_erase(&xe->usm.asid_to_vm, vm->usm.asid);
1547 			xe_assert(xe, lookup == vm);
1548 			mutex_unlock(&xe->usm.lock);
1549 		}
1550 	}
1551 
1552 	for_each_tile(tile, xe, id)
1553 		XE_WARN_ON(vm->pt_root[id]);
1554 
1555 	trace_xe_vm_free(vm);
1556 	dma_fence_put(vm->rebind_fence);
1557 	kfree(vm);
1558 }
1559 
1560 static void xe_vm_free(struct drm_gpuvm *gpuvm)
1561 {
1562 	struct xe_vm *vm = container_of(gpuvm, struct xe_vm, gpuvm);
1563 
1564 	/* To destroy the VM we need to be able to sleep */
1565 	queue_work(system_unbound_wq, &vm->destroy_work);
1566 }
1567 
1568 struct xe_vm *xe_vm_lookup(struct xe_file *xef, u32 id)
1569 {
1570 	struct xe_vm *vm;
1571 
1572 	mutex_lock(&xef->vm.lock);
1573 	vm = xa_load(&xef->vm.xa, id);
1574 	if (vm)
1575 		xe_vm_get(vm);
1576 	mutex_unlock(&xef->vm.lock);
1577 
1578 	return vm;
1579 }
1580 
1581 u64 xe_vm_pdp4_descriptor(struct xe_vm *vm, struct xe_tile *tile)
1582 {
1583 	return vm->pt_ops->pde_encode_bo(vm->pt_root[tile->id]->bo, 0,
1584 					 tile_to_xe(tile)->pat.idx[XE_CACHE_WB]);
1585 }
1586 
1587 static struct xe_exec_queue *
1588 to_wait_exec_queue(struct xe_vm *vm, struct xe_exec_queue *q)
1589 {
1590 	return q ? q : vm->q[0];
1591 }
1592 
1593 static struct dma_fence *
1594 xe_vm_unbind_vma(struct xe_vma *vma, struct xe_exec_queue *q,
1595 		 struct xe_sync_entry *syncs, u32 num_syncs,
1596 		 bool first_op, bool last_op)
1597 {
1598 	struct xe_vm *vm = xe_vma_vm(vma);
1599 	struct xe_exec_queue *wait_exec_queue = to_wait_exec_queue(vm, q);
1600 	struct xe_tile *tile;
1601 	struct dma_fence *fence = NULL;
1602 	struct dma_fence **fences = NULL;
1603 	struct dma_fence_array *cf = NULL;
1604 	int cur_fence = 0, i;
1605 	int number_tiles = hweight8(vma->tile_present);
1606 	int err;
1607 	u8 id;
1608 
1609 	trace_xe_vma_unbind(vma);
1610 
1611 	if (number_tiles > 1) {
1612 		fences = kmalloc_array(number_tiles, sizeof(*fences),
1613 				       GFP_KERNEL);
1614 		if (!fences)
1615 			return ERR_PTR(-ENOMEM);
1616 	}
1617 
1618 	for_each_tile(tile, vm->xe, id) {
1619 		if (!(vma->tile_present & BIT(id)))
1620 			goto next;
1621 
1622 		fence = __xe_pt_unbind_vma(tile, vma, q ? q : vm->q[id],
1623 					   first_op ? syncs : NULL,
1624 					   first_op ? num_syncs : 0);
1625 		if (IS_ERR(fence)) {
1626 			err = PTR_ERR(fence);
1627 			goto err_fences;
1628 		}
1629 
1630 		if (fences)
1631 			fences[cur_fence++] = fence;
1632 
1633 next:
1634 		if (q && vm->pt_root[id] && !list_empty(&q->multi_gt_list))
1635 			q = list_next_entry(q, multi_gt_list);
1636 	}
1637 
1638 	if (fences) {
1639 		cf = dma_fence_array_create(number_tiles, fences,
1640 					    vm->composite_fence_ctx,
1641 					    vm->composite_fence_seqno++,
1642 					    false);
1643 		if (!cf) {
1644 			--vm->composite_fence_seqno;
1645 			err = -ENOMEM;
1646 			goto err_fences;
1647 		}
1648 	}
1649 
1650 	fence = cf ? &cf->base : !fence ?
1651 		xe_exec_queue_last_fence_get(wait_exec_queue, vm) : fence;
1652 	if (last_op) {
1653 		for (i = 0; i < num_syncs; i++)
1654 			xe_sync_entry_signal(&syncs[i], NULL, fence);
1655 	}
1656 
1657 	return fence;
1658 
1659 err_fences:
1660 	if (fences) {
1661 		while (cur_fence)
1662 			dma_fence_put(fences[--cur_fence]);
1663 		kfree(fences);
1664 	}
1665 
1666 	return ERR_PTR(err);
1667 }
1668 
1669 static struct dma_fence *
1670 xe_vm_bind_vma(struct xe_vma *vma, struct xe_exec_queue *q,
1671 	       struct xe_sync_entry *syncs, u32 num_syncs,
1672 	       bool first_op, bool last_op)
1673 {
1674 	struct xe_tile *tile;
1675 	struct dma_fence *fence;
1676 	struct dma_fence **fences = NULL;
1677 	struct dma_fence_array *cf = NULL;
1678 	struct xe_vm *vm = xe_vma_vm(vma);
1679 	int cur_fence = 0, i;
1680 	int number_tiles = hweight8(vma->tile_mask);
1681 	int err;
1682 	u8 id;
1683 
1684 	trace_xe_vma_bind(vma);
1685 
1686 	if (number_tiles > 1) {
1687 		fences = kmalloc_array(number_tiles, sizeof(*fences),
1688 				       GFP_KERNEL);
1689 		if (!fences)
1690 			return ERR_PTR(-ENOMEM);
1691 	}
1692 
1693 	for_each_tile(tile, vm->xe, id) {
1694 		if (!(vma->tile_mask & BIT(id)))
1695 			goto next;
1696 
1697 		fence = __xe_pt_bind_vma(tile, vma, q ? q : vm->q[id],
1698 					 first_op ? syncs : NULL,
1699 					 first_op ? num_syncs : 0,
1700 					 vma->tile_present & BIT(id));
1701 		if (IS_ERR(fence)) {
1702 			err = PTR_ERR(fence);
1703 			goto err_fences;
1704 		}
1705 
1706 		if (fences)
1707 			fences[cur_fence++] = fence;
1708 
1709 next:
1710 		if (q && vm->pt_root[id] && !list_empty(&q->multi_gt_list))
1711 			q = list_next_entry(q, multi_gt_list);
1712 	}
1713 
1714 	if (fences) {
1715 		cf = dma_fence_array_create(number_tiles, fences,
1716 					    vm->composite_fence_ctx,
1717 					    vm->composite_fence_seqno++,
1718 					    false);
1719 		if (!cf) {
1720 			--vm->composite_fence_seqno;
1721 			err = -ENOMEM;
1722 			goto err_fences;
1723 		}
1724 	}
1725 
1726 	if (last_op) {
1727 		for (i = 0; i < num_syncs; i++)
1728 			xe_sync_entry_signal(&syncs[i], NULL,
1729 					     cf ? &cf->base : fence);
1730 	}
1731 
1732 	return cf ? &cf->base : fence;
1733 
1734 err_fences:
1735 	if (fences) {
1736 		while (cur_fence)
1737 			dma_fence_put(fences[--cur_fence]);
1738 		kfree(fences);
1739 	}
1740 
1741 	return ERR_PTR(err);
1742 }
1743 
1744 static int __xe_vm_bind(struct xe_vm *vm, struct xe_vma *vma,
1745 			struct xe_exec_queue *q, struct xe_sync_entry *syncs,
1746 			u32 num_syncs, bool immediate, bool first_op,
1747 			bool last_op)
1748 {
1749 	struct dma_fence *fence;
1750 	struct xe_exec_queue *wait_exec_queue = to_wait_exec_queue(vm, q);
1751 
1752 	xe_vm_assert_held(vm);
1753 
1754 	if (immediate) {
1755 		fence = xe_vm_bind_vma(vma, q, syncs, num_syncs, first_op,
1756 				       last_op);
1757 		if (IS_ERR(fence))
1758 			return PTR_ERR(fence);
1759 	} else {
1760 		int i;
1761 
1762 		xe_assert(vm->xe, xe_vm_in_fault_mode(vm));
1763 
1764 		fence = xe_exec_queue_last_fence_get(wait_exec_queue, vm);
1765 		if (last_op) {
1766 			for (i = 0; i < num_syncs; i++)
1767 				xe_sync_entry_signal(&syncs[i], NULL, fence);
1768 		}
1769 	}
1770 
1771 	if (last_op)
1772 		xe_exec_queue_last_fence_set(wait_exec_queue, vm, fence);
1773 	dma_fence_put(fence);
1774 
1775 	return 0;
1776 }
1777 
1778 static int xe_vm_bind(struct xe_vm *vm, struct xe_vma *vma, struct xe_exec_queue *q,
1779 		      struct xe_bo *bo, struct xe_sync_entry *syncs,
1780 		      u32 num_syncs, bool immediate, bool first_op,
1781 		      bool last_op)
1782 {
1783 	int err;
1784 
1785 	xe_vm_assert_held(vm);
1786 	xe_bo_assert_held(bo);
1787 
1788 	if (bo && immediate) {
1789 		err = xe_bo_validate(bo, vm, true);
1790 		if (err)
1791 			return err;
1792 	}
1793 
1794 	return __xe_vm_bind(vm, vma, q, syncs, num_syncs, immediate, first_op,
1795 			    last_op);
1796 }
1797 
1798 static int xe_vm_unbind(struct xe_vm *vm, struct xe_vma *vma,
1799 			struct xe_exec_queue *q, struct xe_sync_entry *syncs,
1800 			u32 num_syncs, bool first_op, bool last_op)
1801 {
1802 	struct dma_fence *fence;
1803 	struct xe_exec_queue *wait_exec_queue = to_wait_exec_queue(vm, q);
1804 
1805 	xe_vm_assert_held(vm);
1806 	xe_bo_assert_held(xe_vma_bo(vma));
1807 
1808 	fence = xe_vm_unbind_vma(vma, q, syncs, num_syncs, first_op, last_op);
1809 	if (IS_ERR(fence))
1810 		return PTR_ERR(fence);
1811 
1812 	xe_vma_destroy(vma, fence);
1813 	if (last_op)
1814 		xe_exec_queue_last_fence_set(wait_exec_queue, vm, fence);
1815 	dma_fence_put(fence);
1816 
1817 	return 0;
1818 }
1819 
1820 #define ALL_DRM_XE_VM_CREATE_FLAGS (DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE | \
1821 				    DRM_XE_VM_CREATE_FLAG_LR_MODE | \
1822 				    DRM_XE_VM_CREATE_FLAG_FAULT_MODE)
1823 
1824 int xe_vm_create_ioctl(struct drm_device *dev, void *data,
1825 		       struct drm_file *file)
1826 {
1827 	struct xe_device *xe = to_xe_device(dev);
1828 	struct xe_file *xef = to_xe_file(file);
1829 	struct drm_xe_vm_create *args = data;
1830 	struct xe_tile *tile;
1831 	struct xe_vm *vm;
1832 	u32 id, asid;
1833 	int err;
1834 	u32 flags = 0;
1835 
1836 	if (XE_IOCTL_DBG(xe, args->extensions))
1837 		return -EINVAL;
1838 
1839 	if (XE_WA(xe_root_mmio_gt(xe), 14016763929))
1840 		args->flags |= DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE;
1841 
1842 	if (XE_IOCTL_DBG(xe, args->flags & DRM_XE_VM_CREATE_FLAG_FAULT_MODE &&
1843 			 !xe->info.has_usm))
1844 		return -EINVAL;
1845 
1846 	if (XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1]))
1847 		return -EINVAL;
1848 
1849 	if (XE_IOCTL_DBG(xe, args->flags & ~ALL_DRM_XE_VM_CREATE_FLAGS))
1850 		return -EINVAL;
1851 
1852 	if (XE_IOCTL_DBG(xe, args->flags & DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE &&
1853 			 args->flags & DRM_XE_VM_CREATE_FLAG_FAULT_MODE))
1854 		return -EINVAL;
1855 
1856 	if (XE_IOCTL_DBG(xe, !(args->flags & DRM_XE_VM_CREATE_FLAG_LR_MODE) &&
1857 			 args->flags & DRM_XE_VM_CREATE_FLAG_FAULT_MODE))
1858 		return -EINVAL;
1859 
1860 	if (XE_IOCTL_DBG(xe, args->flags & DRM_XE_VM_CREATE_FLAG_FAULT_MODE &&
1861 			 xe_device_in_non_fault_mode(xe)))
1862 		return -EINVAL;
1863 
1864 	if (XE_IOCTL_DBG(xe, !(args->flags & DRM_XE_VM_CREATE_FLAG_FAULT_MODE) &&
1865 			 xe_device_in_fault_mode(xe)))
1866 		return -EINVAL;
1867 
1868 	if (XE_IOCTL_DBG(xe, args->extensions))
1869 		return -EINVAL;
1870 
1871 	if (args->flags & DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE)
1872 		flags |= XE_VM_FLAG_SCRATCH_PAGE;
1873 	if (args->flags & DRM_XE_VM_CREATE_FLAG_LR_MODE)
1874 		flags |= XE_VM_FLAG_LR_MODE;
1875 	if (args->flags & DRM_XE_VM_CREATE_FLAG_FAULT_MODE)
1876 		flags |= XE_VM_FLAG_FAULT_MODE;
1877 
1878 	vm = xe_vm_create(xe, flags);
1879 	if (IS_ERR(vm))
1880 		return PTR_ERR(vm);
1881 
1882 	mutex_lock(&xef->vm.lock);
1883 	err = xa_alloc(&xef->vm.xa, &id, vm, xa_limit_32b, GFP_KERNEL);
1884 	mutex_unlock(&xef->vm.lock);
1885 	if (err)
1886 		goto err_close_and_put;
1887 
1888 	if (xe->info.has_asid) {
1889 		mutex_lock(&xe->usm.lock);
1890 		err = xa_alloc_cyclic(&xe->usm.asid_to_vm, &asid, vm,
1891 				      XA_LIMIT(1, XE_MAX_ASID - 1),
1892 				      &xe->usm.next_asid, GFP_KERNEL);
1893 		mutex_unlock(&xe->usm.lock);
1894 		if (err < 0)
1895 			goto err_free_id;
1896 
1897 		vm->usm.asid = asid;
1898 	}
1899 
1900 	args->vm_id = id;
1901 	vm->xef = xef;
1902 
1903 	/* Record BO memory for VM pagetable created against client */
1904 	for_each_tile(tile, xe, id)
1905 		if (vm->pt_root[id])
1906 			xe_drm_client_add_bo(vm->xef->client, vm->pt_root[id]->bo);
1907 
1908 #if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
1909 	/* Warning: Security issue - never enable by default */
1910 	args->reserved[0] = xe_bo_main_addr(vm->pt_root[0]->bo, XE_PAGE_SIZE);
1911 #endif
1912 
1913 	return 0;
1914 
1915 err_free_id:
1916 	mutex_lock(&xef->vm.lock);
1917 	xa_erase(&xef->vm.xa, id);
1918 	mutex_unlock(&xef->vm.lock);
1919 err_close_and_put:
1920 	xe_vm_close_and_put(vm);
1921 
1922 	return err;
1923 }
1924 
1925 int xe_vm_destroy_ioctl(struct drm_device *dev, void *data,
1926 			struct drm_file *file)
1927 {
1928 	struct xe_device *xe = to_xe_device(dev);
1929 	struct xe_file *xef = to_xe_file(file);
1930 	struct drm_xe_vm_destroy *args = data;
1931 	struct xe_vm *vm;
1932 	int err = 0;
1933 
1934 	if (XE_IOCTL_DBG(xe, args->pad) ||
1935 	    XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1]))
1936 		return -EINVAL;
1937 
1938 	mutex_lock(&xef->vm.lock);
1939 	vm = xa_load(&xef->vm.xa, args->vm_id);
1940 	if (XE_IOCTL_DBG(xe, !vm))
1941 		err = -ENOENT;
1942 	else if (XE_IOCTL_DBG(xe, vm->preempt.num_exec_queues))
1943 		err = -EBUSY;
1944 	else
1945 		xa_erase(&xef->vm.xa, args->vm_id);
1946 	mutex_unlock(&xef->vm.lock);
1947 
1948 	if (!err)
1949 		xe_vm_close_and_put(vm);
1950 
1951 	return err;
1952 }
1953 
1954 static const u32 region_to_mem_type[] = {
1955 	XE_PL_TT,
1956 	XE_PL_VRAM0,
1957 	XE_PL_VRAM1,
1958 };
1959 
1960 static int xe_vm_prefetch(struct xe_vm *vm, struct xe_vma *vma,
1961 			  struct xe_exec_queue *q, u32 region,
1962 			  struct xe_sync_entry *syncs, u32 num_syncs,
1963 			  bool first_op, bool last_op)
1964 {
1965 	struct xe_exec_queue *wait_exec_queue = to_wait_exec_queue(vm, q);
1966 	int err;
1967 
1968 	xe_assert(vm->xe, region <= ARRAY_SIZE(region_to_mem_type));
1969 
1970 	if (!xe_vma_has_no_bo(vma)) {
1971 		err = xe_bo_migrate(xe_vma_bo(vma), region_to_mem_type[region]);
1972 		if (err)
1973 			return err;
1974 	}
1975 
1976 	if (vma->tile_mask != (vma->tile_present & ~vma->usm.tile_invalidated)) {
1977 		return xe_vm_bind(vm, vma, q, xe_vma_bo(vma), syncs, num_syncs,
1978 				  true, first_op, last_op);
1979 	} else {
1980 		int i;
1981 
1982 		/* Nothing to do, signal fences now */
1983 		if (last_op) {
1984 			for (i = 0; i < num_syncs; i++) {
1985 				struct dma_fence *fence =
1986 					xe_exec_queue_last_fence_get(wait_exec_queue, vm);
1987 
1988 				xe_sync_entry_signal(&syncs[i], NULL, fence);
1989 				dma_fence_put(fence);
1990 			}
1991 		}
1992 
1993 		return 0;
1994 	}
1995 }
1996 
1997 static void prep_vma_destroy(struct xe_vm *vm, struct xe_vma *vma,
1998 			     bool post_commit)
1999 {
2000 	down_read(&vm->userptr.notifier_lock);
2001 	vma->gpuva.flags |= XE_VMA_DESTROYED;
2002 	up_read(&vm->userptr.notifier_lock);
2003 	if (post_commit)
2004 		xe_vm_remove_vma(vm, vma);
2005 }
2006 
2007 #undef ULL
2008 #define ULL	unsigned long long
2009 
2010 #if IS_ENABLED(CONFIG_DRM_XE_DEBUG_VM)
2011 static void print_op(struct xe_device *xe, struct drm_gpuva_op *op)
2012 {
2013 	struct xe_vma *vma;
2014 
2015 	switch (op->op) {
2016 	case DRM_GPUVA_OP_MAP:
2017 		vm_dbg(&xe->drm, "MAP: addr=0x%016llx, range=0x%016llx",
2018 		       (ULL)op->map.va.addr, (ULL)op->map.va.range);
2019 		break;
2020 	case DRM_GPUVA_OP_REMAP:
2021 		vma = gpuva_to_vma(op->remap.unmap->va);
2022 		vm_dbg(&xe->drm, "REMAP:UNMAP: addr=0x%016llx, range=0x%016llx, keep=%d",
2023 		       (ULL)xe_vma_start(vma), (ULL)xe_vma_size(vma),
2024 		       op->remap.unmap->keep ? 1 : 0);
2025 		if (op->remap.prev)
2026 			vm_dbg(&xe->drm,
2027 			       "REMAP:PREV: addr=0x%016llx, range=0x%016llx",
2028 			       (ULL)op->remap.prev->va.addr,
2029 			       (ULL)op->remap.prev->va.range);
2030 		if (op->remap.next)
2031 			vm_dbg(&xe->drm,
2032 			       "REMAP:NEXT: addr=0x%016llx, range=0x%016llx",
2033 			       (ULL)op->remap.next->va.addr,
2034 			       (ULL)op->remap.next->va.range);
2035 		break;
2036 	case DRM_GPUVA_OP_UNMAP:
2037 		vma = gpuva_to_vma(op->unmap.va);
2038 		vm_dbg(&xe->drm, "UNMAP: addr=0x%016llx, range=0x%016llx, keep=%d",
2039 		       (ULL)xe_vma_start(vma), (ULL)xe_vma_size(vma),
2040 		       op->unmap.keep ? 1 : 0);
2041 		break;
2042 	case DRM_GPUVA_OP_PREFETCH:
2043 		vma = gpuva_to_vma(op->prefetch.va);
2044 		vm_dbg(&xe->drm, "PREFETCH: addr=0x%016llx, range=0x%016llx",
2045 		       (ULL)xe_vma_start(vma), (ULL)xe_vma_size(vma));
2046 		break;
2047 	default:
2048 		drm_warn(&xe->drm, "NOT POSSIBLE");
2049 	}
2050 }
2051 #else
2052 static void print_op(struct xe_device *xe, struct drm_gpuva_op *op)
2053 {
2054 }
2055 #endif
2056 
2057 /*
2058  * Create operations list from IOCTL arguments, setup operations fields so parse
2059  * and commit steps are decoupled from IOCTL arguments. This step can fail.
2060  */
2061 static struct drm_gpuva_ops *
2062 vm_bind_ioctl_ops_create(struct xe_vm *vm, struct xe_bo *bo,
2063 			 u64 bo_offset_or_userptr, u64 addr, u64 range,
2064 			 u32 operation, u32 flags,
2065 			 u32 prefetch_region, u16 pat_index)
2066 {
2067 	struct drm_gem_object *obj = bo ? &bo->ttm.base : NULL;
2068 	struct drm_gpuva_ops *ops;
2069 	struct drm_gpuva_op *__op;
2070 	struct drm_gpuvm_bo *vm_bo;
2071 	int err;
2072 
2073 	lockdep_assert_held_write(&vm->lock);
2074 
2075 	vm_dbg(&vm->xe->drm,
2076 	       "op=%d, addr=0x%016llx, range=0x%016llx, bo_offset_or_userptr=0x%016llx",
2077 	       operation, (ULL)addr, (ULL)range,
2078 	       (ULL)bo_offset_or_userptr);
2079 
2080 	switch (operation) {
2081 	case DRM_XE_VM_BIND_OP_MAP:
2082 	case DRM_XE_VM_BIND_OP_MAP_USERPTR:
2083 		ops = drm_gpuvm_sm_map_ops_create(&vm->gpuvm, addr, range,
2084 						  obj, bo_offset_or_userptr);
2085 		break;
2086 	case DRM_XE_VM_BIND_OP_UNMAP:
2087 		ops = drm_gpuvm_sm_unmap_ops_create(&vm->gpuvm, addr, range);
2088 		break;
2089 	case DRM_XE_VM_BIND_OP_PREFETCH:
2090 		ops = drm_gpuvm_prefetch_ops_create(&vm->gpuvm, addr, range);
2091 		break;
2092 	case DRM_XE_VM_BIND_OP_UNMAP_ALL:
2093 		xe_assert(vm->xe, bo);
2094 
2095 		err = xe_bo_lock(bo, true);
2096 		if (err)
2097 			return ERR_PTR(err);
2098 
2099 		vm_bo = drm_gpuvm_bo_obtain(&vm->gpuvm, obj);
2100 		if (IS_ERR(vm_bo)) {
2101 			xe_bo_unlock(bo);
2102 			return ERR_CAST(vm_bo);
2103 		}
2104 
2105 		ops = drm_gpuvm_bo_unmap_ops_create(vm_bo);
2106 		drm_gpuvm_bo_put(vm_bo);
2107 		xe_bo_unlock(bo);
2108 		break;
2109 	default:
2110 		drm_warn(&vm->xe->drm, "NOT POSSIBLE");
2111 		ops = ERR_PTR(-EINVAL);
2112 	}
2113 	if (IS_ERR(ops))
2114 		return ops;
2115 
2116 	drm_gpuva_for_each_op(__op, ops) {
2117 		struct xe_vma_op *op = gpuva_op_to_vma_op(__op);
2118 
2119 		if (__op->op == DRM_GPUVA_OP_MAP) {
2120 			op->map.immediate =
2121 				flags & DRM_XE_VM_BIND_FLAG_IMMEDIATE;
2122 			op->map.read_only =
2123 				flags & DRM_XE_VM_BIND_FLAG_READONLY;
2124 			op->map.is_null = flags & DRM_XE_VM_BIND_FLAG_NULL;
2125 			op->map.pat_index = pat_index;
2126 		} else if (__op->op == DRM_GPUVA_OP_PREFETCH) {
2127 			op->prefetch.region = prefetch_region;
2128 		}
2129 
2130 		print_op(vm->xe, __op);
2131 	}
2132 
2133 	return ops;
2134 }
2135 
2136 static struct xe_vma *new_vma(struct xe_vm *vm, struct drm_gpuva_op_map *op,
2137 			      u16 pat_index, unsigned int flags)
2138 {
2139 	struct xe_bo *bo = op->gem.obj ? gem_to_xe_bo(op->gem.obj) : NULL;
2140 	struct drm_exec exec;
2141 	struct xe_vma *vma;
2142 	int err;
2143 
2144 	lockdep_assert_held_write(&vm->lock);
2145 
2146 	if (bo) {
2147 		drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);
2148 		drm_exec_until_all_locked(&exec) {
2149 			err = 0;
2150 			if (!bo->vm) {
2151 				err = drm_exec_lock_obj(&exec, xe_vm_obj(vm));
2152 				drm_exec_retry_on_contention(&exec);
2153 			}
2154 			if (!err) {
2155 				err = drm_exec_lock_obj(&exec, &bo->ttm.base);
2156 				drm_exec_retry_on_contention(&exec);
2157 			}
2158 			if (err) {
2159 				drm_exec_fini(&exec);
2160 				return ERR_PTR(err);
2161 			}
2162 		}
2163 	}
2164 	vma = xe_vma_create(vm, bo, op->gem.offset,
2165 			    op->va.addr, op->va.addr +
2166 			    op->va.range - 1, pat_index, flags);
2167 	if (bo)
2168 		drm_exec_fini(&exec);
2169 
2170 	if (xe_vma_is_userptr(vma)) {
2171 		err = xe_vma_userptr_pin_pages(to_userptr_vma(vma));
2172 		if (err) {
2173 			prep_vma_destroy(vm, vma, false);
2174 			xe_vma_destroy_unlocked(vma);
2175 			return ERR_PTR(err);
2176 		}
2177 	} else if (!xe_vma_has_no_bo(vma) && !bo->vm) {
2178 		err = add_preempt_fences(vm, bo);
2179 		if (err) {
2180 			prep_vma_destroy(vm, vma, false);
2181 			xe_vma_destroy_unlocked(vma);
2182 			return ERR_PTR(err);
2183 		}
2184 	}
2185 
2186 	return vma;
2187 }
2188 
2189 static u64 xe_vma_max_pte_size(struct xe_vma *vma)
2190 {
2191 	if (vma->gpuva.flags & XE_VMA_PTE_1G)
2192 		return SZ_1G;
2193 	else if (vma->gpuva.flags & (XE_VMA_PTE_2M | XE_VMA_PTE_COMPACT))
2194 		return SZ_2M;
2195 	else if (vma->gpuva.flags & XE_VMA_PTE_64K)
2196 		return SZ_64K;
2197 	else if (vma->gpuva.flags & XE_VMA_PTE_4K)
2198 		return SZ_4K;
2199 
2200 	return SZ_1G;	/* Uninitialized, used max size */
2201 }
2202 
2203 static void xe_vma_set_pte_size(struct xe_vma *vma, u64 size)
2204 {
2205 	switch (size) {
2206 	case SZ_1G:
2207 		vma->gpuva.flags |= XE_VMA_PTE_1G;
2208 		break;
2209 	case SZ_2M:
2210 		vma->gpuva.flags |= XE_VMA_PTE_2M;
2211 		break;
2212 	case SZ_64K:
2213 		vma->gpuva.flags |= XE_VMA_PTE_64K;
2214 		break;
2215 	case SZ_4K:
2216 		vma->gpuva.flags |= XE_VMA_PTE_4K;
2217 		break;
2218 	}
2219 }
2220 
2221 static int xe_vma_op_commit(struct xe_vm *vm, struct xe_vma_op *op)
2222 {
2223 	int err = 0;
2224 
2225 	lockdep_assert_held_write(&vm->lock);
2226 
2227 	switch (op->base.op) {
2228 	case DRM_GPUVA_OP_MAP:
2229 		err |= xe_vm_insert_vma(vm, op->map.vma);
2230 		if (!err)
2231 			op->flags |= XE_VMA_OP_COMMITTED;
2232 		break;
2233 	case DRM_GPUVA_OP_REMAP:
2234 	{
2235 		u8 tile_present =
2236 			gpuva_to_vma(op->base.remap.unmap->va)->tile_present;
2237 
2238 		prep_vma_destroy(vm, gpuva_to_vma(op->base.remap.unmap->va),
2239 				 true);
2240 		op->flags |= XE_VMA_OP_COMMITTED;
2241 
2242 		if (op->remap.prev) {
2243 			err |= xe_vm_insert_vma(vm, op->remap.prev);
2244 			if (!err)
2245 				op->flags |= XE_VMA_OP_PREV_COMMITTED;
2246 			if (!err && op->remap.skip_prev) {
2247 				op->remap.prev->tile_present =
2248 					tile_present;
2249 				op->remap.prev = NULL;
2250 			}
2251 		}
2252 		if (op->remap.next) {
2253 			err |= xe_vm_insert_vma(vm, op->remap.next);
2254 			if (!err)
2255 				op->flags |= XE_VMA_OP_NEXT_COMMITTED;
2256 			if (!err && op->remap.skip_next) {
2257 				op->remap.next->tile_present =
2258 					tile_present;
2259 				op->remap.next = NULL;
2260 			}
2261 		}
2262 
2263 		/* Adjust for partial unbind after removin VMA from VM */
2264 		if (!err) {
2265 			op->base.remap.unmap->va->va.addr = op->remap.start;
2266 			op->base.remap.unmap->va->va.range = op->remap.range;
2267 		}
2268 		break;
2269 	}
2270 	case DRM_GPUVA_OP_UNMAP:
2271 		prep_vma_destroy(vm, gpuva_to_vma(op->base.unmap.va), true);
2272 		op->flags |= XE_VMA_OP_COMMITTED;
2273 		break;
2274 	case DRM_GPUVA_OP_PREFETCH:
2275 		op->flags |= XE_VMA_OP_COMMITTED;
2276 		break;
2277 	default:
2278 		drm_warn(&vm->xe->drm, "NOT POSSIBLE");
2279 	}
2280 
2281 	return err;
2282 }
2283 
2284 
2285 static int vm_bind_ioctl_ops_parse(struct xe_vm *vm, struct xe_exec_queue *q,
2286 				   struct drm_gpuva_ops *ops,
2287 				   struct xe_sync_entry *syncs, u32 num_syncs,
2288 				   struct list_head *ops_list, bool last)
2289 {
2290 	struct xe_vma_op *last_op = NULL;
2291 	struct drm_gpuva_op *__op;
2292 	int err = 0;
2293 
2294 	lockdep_assert_held_write(&vm->lock);
2295 
2296 	drm_gpuva_for_each_op(__op, ops) {
2297 		struct xe_vma_op *op = gpuva_op_to_vma_op(__op);
2298 		struct xe_vma *vma;
2299 		bool first = list_empty(ops_list);
2300 		unsigned int flags = 0;
2301 
2302 		INIT_LIST_HEAD(&op->link);
2303 		list_add_tail(&op->link, ops_list);
2304 
2305 		if (first) {
2306 			op->flags |= XE_VMA_OP_FIRST;
2307 			op->num_syncs = num_syncs;
2308 			op->syncs = syncs;
2309 		}
2310 
2311 		op->q = q;
2312 
2313 		switch (op->base.op) {
2314 		case DRM_GPUVA_OP_MAP:
2315 		{
2316 			flags |= op->map.read_only ?
2317 				VMA_CREATE_FLAG_READ_ONLY : 0;
2318 			flags |= op->map.is_null ?
2319 				VMA_CREATE_FLAG_IS_NULL : 0;
2320 
2321 			vma = new_vma(vm, &op->base.map, op->map.pat_index,
2322 				      flags);
2323 			if (IS_ERR(vma))
2324 				return PTR_ERR(vma);
2325 
2326 			op->map.vma = vma;
2327 			break;
2328 		}
2329 		case DRM_GPUVA_OP_REMAP:
2330 		{
2331 			struct xe_vma *old =
2332 				gpuva_to_vma(op->base.remap.unmap->va);
2333 
2334 			op->remap.start = xe_vma_start(old);
2335 			op->remap.range = xe_vma_size(old);
2336 
2337 			if (op->base.remap.prev) {
2338 				flags |= op->base.remap.unmap->va->flags &
2339 					XE_VMA_READ_ONLY ?
2340 					VMA_CREATE_FLAG_READ_ONLY : 0;
2341 				flags |= op->base.remap.unmap->va->flags &
2342 					DRM_GPUVA_SPARSE ?
2343 					VMA_CREATE_FLAG_IS_NULL : 0;
2344 
2345 				vma = new_vma(vm, op->base.remap.prev,
2346 					      old->pat_index, flags);
2347 				if (IS_ERR(vma))
2348 					return PTR_ERR(vma);
2349 
2350 				op->remap.prev = vma;
2351 
2352 				/*
2353 				 * Userptr creates a new SG mapping so
2354 				 * we must also rebind.
2355 				 */
2356 				op->remap.skip_prev = !xe_vma_is_userptr(old) &&
2357 					IS_ALIGNED(xe_vma_end(vma),
2358 						   xe_vma_max_pte_size(old));
2359 				if (op->remap.skip_prev) {
2360 					xe_vma_set_pte_size(vma, xe_vma_max_pte_size(old));
2361 					op->remap.range -=
2362 						xe_vma_end(vma) -
2363 						xe_vma_start(old);
2364 					op->remap.start = xe_vma_end(vma);
2365 				}
2366 			}
2367 
2368 			if (op->base.remap.next) {
2369 				flags |= op->base.remap.unmap->va->flags &
2370 					XE_VMA_READ_ONLY ?
2371 					VMA_CREATE_FLAG_READ_ONLY : 0;
2372 				flags |= op->base.remap.unmap->va->flags &
2373 					DRM_GPUVA_SPARSE ?
2374 					VMA_CREATE_FLAG_IS_NULL : 0;
2375 
2376 				vma = new_vma(vm, op->base.remap.next,
2377 					      old->pat_index, flags);
2378 				if (IS_ERR(vma))
2379 					return PTR_ERR(vma);
2380 
2381 				op->remap.next = vma;
2382 
2383 				/*
2384 				 * Userptr creates a new SG mapping so
2385 				 * we must also rebind.
2386 				 */
2387 				op->remap.skip_next = !xe_vma_is_userptr(old) &&
2388 					IS_ALIGNED(xe_vma_start(vma),
2389 						   xe_vma_max_pte_size(old));
2390 				if (op->remap.skip_next) {
2391 					xe_vma_set_pte_size(vma, xe_vma_max_pte_size(old));
2392 					op->remap.range -=
2393 						xe_vma_end(old) -
2394 						xe_vma_start(vma);
2395 				}
2396 			}
2397 			break;
2398 		}
2399 		case DRM_GPUVA_OP_UNMAP:
2400 		case DRM_GPUVA_OP_PREFETCH:
2401 			/* Nothing to do */
2402 			break;
2403 		default:
2404 			drm_warn(&vm->xe->drm, "NOT POSSIBLE");
2405 		}
2406 
2407 		last_op = op;
2408 
2409 		err = xe_vma_op_commit(vm, op);
2410 		if (err)
2411 			return err;
2412 	}
2413 
2414 	/* FIXME: Unhandled corner case */
2415 	XE_WARN_ON(!last_op && last && !list_empty(ops_list));
2416 
2417 	if (!last_op)
2418 		return 0;
2419 
2420 	last_op->ops = ops;
2421 	if (last) {
2422 		last_op->flags |= XE_VMA_OP_LAST;
2423 		last_op->num_syncs = num_syncs;
2424 		last_op->syncs = syncs;
2425 	}
2426 
2427 	return 0;
2428 }
2429 
2430 static int op_execute(struct drm_exec *exec, struct xe_vm *vm,
2431 		      struct xe_vma *vma, struct xe_vma_op *op)
2432 {
2433 	int err;
2434 
2435 	lockdep_assert_held_write(&vm->lock);
2436 
2437 	err = xe_vm_prepare_vma(exec, vma, 1);
2438 	if (err)
2439 		return err;
2440 
2441 	xe_vm_assert_held(vm);
2442 	xe_bo_assert_held(xe_vma_bo(vma));
2443 
2444 	switch (op->base.op) {
2445 	case DRM_GPUVA_OP_MAP:
2446 		err = xe_vm_bind(vm, vma, op->q, xe_vma_bo(vma),
2447 				 op->syncs, op->num_syncs,
2448 				 op->map.immediate || !xe_vm_in_fault_mode(vm),
2449 				 op->flags & XE_VMA_OP_FIRST,
2450 				 op->flags & XE_VMA_OP_LAST);
2451 		break;
2452 	case DRM_GPUVA_OP_REMAP:
2453 	{
2454 		bool prev = !!op->remap.prev;
2455 		bool next = !!op->remap.next;
2456 
2457 		if (!op->remap.unmap_done) {
2458 			if (prev || next)
2459 				vma->gpuva.flags |= XE_VMA_FIRST_REBIND;
2460 			err = xe_vm_unbind(vm, vma, op->q, op->syncs,
2461 					   op->num_syncs,
2462 					   op->flags & XE_VMA_OP_FIRST,
2463 					   op->flags & XE_VMA_OP_LAST &&
2464 					   !prev && !next);
2465 			if (err)
2466 				break;
2467 			op->remap.unmap_done = true;
2468 		}
2469 
2470 		if (prev) {
2471 			op->remap.prev->gpuva.flags |= XE_VMA_LAST_REBIND;
2472 			err = xe_vm_bind(vm, op->remap.prev, op->q,
2473 					 xe_vma_bo(op->remap.prev), op->syncs,
2474 					 op->num_syncs, true, false,
2475 					 op->flags & XE_VMA_OP_LAST && !next);
2476 			op->remap.prev->gpuva.flags &= ~XE_VMA_LAST_REBIND;
2477 			if (err)
2478 				break;
2479 			op->remap.prev = NULL;
2480 		}
2481 
2482 		if (next) {
2483 			op->remap.next->gpuva.flags |= XE_VMA_LAST_REBIND;
2484 			err = xe_vm_bind(vm, op->remap.next, op->q,
2485 					 xe_vma_bo(op->remap.next),
2486 					 op->syncs, op->num_syncs,
2487 					 true, false,
2488 					 op->flags & XE_VMA_OP_LAST);
2489 			op->remap.next->gpuva.flags &= ~XE_VMA_LAST_REBIND;
2490 			if (err)
2491 				break;
2492 			op->remap.next = NULL;
2493 		}
2494 
2495 		break;
2496 	}
2497 	case DRM_GPUVA_OP_UNMAP:
2498 		err = xe_vm_unbind(vm, vma, op->q, op->syncs,
2499 				   op->num_syncs, op->flags & XE_VMA_OP_FIRST,
2500 				   op->flags & XE_VMA_OP_LAST);
2501 		break;
2502 	case DRM_GPUVA_OP_PREFETCH:
2503 		err = xe_vm_prefetch(vm, vma, op->q, op->prefetch.region,
2504 				     op->syncs, op->num_syncs,
2505 				     op->flags & XE_VMA_OP_FIRST,
2506 				     op->flags & XE_VMA_OP_LAST);
2507 		break;
2508 	default:
2509 		drm_warn(&vm->xe->drm, "NOT POSSIBLE");
2510 	}
2511 
2512 	if (err)
2513 		trace_xe_vma_fail(vma);
2514 
2515 	return err;
2516 }
2517 
2518 static int __xe_vma_op_execute(struct xe_vm *vm, struct xe_vma *vma,
2519 			       struct xe_vma_op *op)
2520 {
2521 	struct drm_exec exec;
2522 	int err;
2523 
2524 retry_userptr:
2525 	drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);
2526 	drm_exec_until_all_locked(&exec) {
2527 		err = op_execute(&exec, vm, vma, op);
2528 		drm_exec_retry_on_contention(&exec);
2529 		if (err)
2530 			break;
2531 	}
2532 	drm_exec_fini(&exec);
2533 
2534 	if (err == -EAGAIN) {
2535 		lockdep_assert_held_write(&vm->lock);
2536 
2537 		if (op->base.op == DRM_GPUVA_OP_REMAP) {
2538 			if (!op->remap.unmap_done)
2539 				vma = gpuva_to_vma(op->base.remap.unmap->va);
2540 			else if (op->remap.prev)
2541 				vma = op->remap.prev;
2542 			else
2543 				vma = op->remap.next;
2544 		}
2545 
2546 		if (xe_vma_is_userptr(vma)) {
2547 			err = xe_vma_userptr_pin_pages(to_userptr_vma(vma));
2548 			if (!err)
2549 				goto retry_userptr;
2550 
2551 			trace_xe_vma_fail(vma);
2552 		}
2553 	}
2554 
2555 	return err;
2556 }
2557 
2558 static int xe_vma_op_execute(struct xe_vm *vm, struct xe_vma_op *op)
2559 {
2560 	int ret = 0;
2561 
2562 	lockdep_assert_held_write(&vm->lock);
2563 
2564 	switch (op->base.op) {
2565 	case DRM_GPUVA_OP_MAP:
2566 		ret = __xe_vma_op_execute(vm, op->map.vma, op);
2567 		break;
2568 	case DRM_GPUVA_OP_REMAP:
2569 	{
2570 		struct xe_vma *vma;
2571 
2572 		if (!op->remap.unmap_done)
2573 			vma = gpuva_to_vma(op->base.remap.unmap->va);
2574 		else if (op->remap.prev)
2575 			vma = op->remap.prev;
2576 		else
2577 			vma = op->remap.next;
2578 
2579 		ret = __xe_vma_op_execute(vm, vma, op);
2580 		break;
2581 	}
2582 	case DRM_GPUVA_OP_UNMAP:
2583 		ret = __xe_vma_op_execute(vm, gpuva_to_vma(op->base.unmap.va),
2584 					  op);
2585 		break;
2586 	case DRM_GPUVA_OP_PREFETCH:
2587 		ret = __xe_vma_op_execute(vm,
2588 					  gpuva_to_vma(op->base.prefetch.va),
2589 					  op);
2590 		break;
2591 	default:
2592 		drm_warn(&vm->xe->drm, "NOT POSSIBLE");
2593 	}
2594 
2595 	return ret;
2596 }
2597 
2598 static void xe_vma_op_cleanup(struct xe_vm *vm, struct xe_vma_op *op)
2599 {
2600 	bool last = op->flags & XE_VMA_OP_LAST;
2601 
2602 	if (last) {
2603 		while (op->num_syncs--)
2604 			xe_sync_entry_cleanup(&op->syncs[op->num_syncs]);
2605 		kfree(op->syncs);
2606 		if (op->q)
2607 			xe_exec_queue_put(op->q);
2608 	}
2609 	if (!list_empty(&op->link))
2610 		list_del(&op->link);
2611 	if (op->ops)
2612 		drm_gpuva_ops_free(&vm->gpuvm, op->ops);
2613 	if (last)
2614 		xe_vm_put(vm);
2615 }
2616 
2617 static void xe_vma_op_unwind(struct xe_vm *vm, struct xe_vma_op *op,
2618 			     bool post_commit, bool prev_post_commit,
2619 			     bool next_post_commit)
2620 {
2621 	lockdep_assert_held_write(&vm->lock);
2622 
2623 	switch (op->base.op) {
2624 	case DRM_GPUVA_OP_MAP:
2625 		if (op->map.vma) {
2626 			prep_vma_destroy(vm, op->map.vma, post_commit);
2627 			xe_vma_destroy_unlocked(op->map.vma);
2628 		}
2629 		break;
2630 	case DRM_GPUVA_OP_UNMAP:
2631 	{
2632 		struct xe_vma *vma = gpuva_to_vma(op->base.unmap.va);
2633 
2634 		if (vma) {
2635 			down_read(&vm->userptr.notifier_lock);
2636 			vma->gpuva.flags &= ~XE_VMA_DESTROYED;
2637 			up_read(&vm->userptr.notifier_lock);
2638 			if (post_commit)
2639 				xe_vm_insert_vma(vm, vma);
2640 		}
2641 		break;
2642 	}
2643 	case DRM_GPUVA_OP_REMAP:
2644 	{
2645 		struct xe_vma *vma = gpuva_to_vma(op->base.remap.unmap->va);
2646 
2647 		if (op->remap.prev) {
2648 			prep_vma_destroy(vm, op->remap.prev, prev_post_commit);
2649 			xe_vma_destroy_unlocked(op->remap.prev);
2650 		}
2651 		if (op->remap.next) {
2652 			prep_vma_destroy(vm, op->remap.next, next_post_commit);
2653 			xe_vma_destroy_unlocked(op->remap.next);
2654 		}
2655 		if (vma) {
2656 			down_read(&vm->userptr.notifier_lock);
2657 			vma->gpuva.flags &= ~XE_VMA_DESTROYED;
2658 			up_read(&vm->userptr.notifier_lock);
2659 			if (post_commit)
2660 				xe_vm_insert_vma(vm, vma);
2661 		}
2662 		break;
2663 	}
2664 	case DRM_GPUVA_OP_PREFETCH:
2665 		/* Nothing to do */
2666 		break;
2667 	default:
2668 		drm_warn(&vm->xe->drm, "NOT POSSIBLE");
2669 	}
2670 }
2671 
2672 static void vm_bind_ioctl_ops_unwind(struct xe_vm *vm,
2673 				     struct drm_gpuva_ops **ops,
2674 				     int num_ops_list)
2675 {
2676 	int i;
2677 
2678 	for (i = num_ops_list - 1; i >= 0; --i) {
2679 		struct drm_gpuva_ops *__ops = ops[i];
2680 		struct drm_gpuva_op *__op;
2681 
2682 		if (!__ops)
2683 			continue;
2684 
2685 		drm_gpuva_for_each_op_reverse(__op, __ops) {
2686 			struct xe_vma_op *op = gpuva_op_to_vma_op(__op);
2687 
2688 			xe_vma_op_unwind(vm, op,
2689 					 op->flags & XE_VMA_OP_COMMITTED,
2690 					 op->flags & XE_VMA_OP_PREV_COMMITTED,
2691 					 op->flags & XE_VMA_OP_NEXT_COMMITTED);
2692 		}
2693 
2694 		drm_gpuva_ops_free(&vm->gpuvm, __ops);
2695 	}
2696 }
2697 
2698 static int vm_bind_ioctl_ops_execute(struct xe_vm *vm,
2699 				     struct list_head *ops_list)
2700 {
2701 	struct xe_vma_op *op, *next;
2702 	int err;
2703 
2704 	lockdep_assert_held_write(&vm->lock);
2705 
2706 	list_for_each_entry_safe(op, next, ops_list, link) {
2707 		err = xe_vma_op_execute(vm, op);
2708 		if (err) {
2709 			drm_warn(&vm->xe->drm, "VM op(%d) failed with %d",
2710 				 op->base.op, err);
2711 			/*
2712 			 * FIXME: Killing VM rather than proper error handling
2713 			 */
2714 			xe_vm_kill(vm);
2715 			return -ENOSPC;
2716 		}
2717 		xe_vma_op_cleanup(vm, op);
2718 	}
2719 
2720 	return 0;
2721 }
2722 
2723 #define SUPPORTED_FLAGS	\
2724 	(DRM_XE_VM_BIND_FLAG_READONLY | \
2725 	 DRM_XE_VM_BIND_FLAG_IMMEDIATE | DRM_XE_VM_BIND_FLAG_NULL)
2726 #define XE_64K_PAGE_MASK 0xffffull
2727 #define ALL_DRM_XE_SYNCS_FLAGS (DRM_XE_SYNCS_FLAG_WAIT_FOR_OP)
2728 
2729 #define MAX_BINDS	512	/* FIXME: Picking random upper limit */
2730 
2731 static int vm_bind_ioctl_check_args(struct xe_device *xe,
2732 				    struct drm_xe_vm_bind *args,
2733 				    struct drm_xe_vm_bind_op **bind_ops)
2734 {
2735 	int err;
2736 	int i;
2737 
2738 	if (XE_IOCTL_DBG(xe, args->pad || args->pad2) ||
2739 	    XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1]))
2740 		return -EINVAL;
2741 
2742 	if (XE_IOCTL_DBG(xe, args->extensions) ||
2743 	    XE_IOCTL_DBG(xe, args->num_binds > MAX_BINDS))
2744 		return -EINVAL;
2745 
2746 	if (args->num_binds > 1) {
2747 		u64 __user *bind_user =
2748 			u64_to_user_ptr(args->vector_of_binds);
2749 
2750 		*bind_ops = kmalloc(sizeof(struct drm_xe_vm_bind_op) *
2751 				    args->num_binds, GFP_KERNEL);
2752 		if (!*bind_ops)
2753 			return -ENOMEM;
2754 
2755 		err = __copy_from_user(*bind_ops, bind_user,
2756 				       sizeof(struct drm_xe_vm_bind_op) *
2757 				       args->num_binds);
2758 		if (XE_IOCTL_DBG(xe, err)) {
2759 			err = -EFAULT;
2760 			goto free_bind_ops;
2761 		}
2762 	} else {
2763 		*bind_ops = &args->bind;
2764 	}
2765 
2766 	for (i = 0; i < args->num_binds; ++i) {
2767 		u64 range = (*bind_ops)[i].range;
2768 		u64 addr = (*bind_ops)[i].addr;
2769 		u32 op = (*bind_ops)[i].op;
2770 		u32 flags = (*bind_ops)[i].flags;
2771 		u32 obj = (*bind_ops)[i].obj;
2772 		u64 obj_offset = (*bind_ops)[i].obj_offset;
2773 		u32 prefetch_region = (*bind_ops)[i].prefetch_mem_region_instance;
2774 		bool is_null = flags & DRM_XE_VM_BIND_FLAG_NULL;
2775 		u16 pat_index = (*bind_ops)[i].pat_index;
2776 		u16 coh_mode;
2777 
2778 		if (XE_IOCTL_DBG(xe, pat_index >= xe->pat.n_entries)) {
2779 			err = -EINVAL;
2780 			goto free_bind_ops;
2781 		}
2782 
2783 		pat_index = array_index_nospec(pat_index, xe->pat.n_entries);
2784 		(*bind_ops)[i].pat_index = pat_index;
2785 		coh_mode = xe_pat_index_get_coh_mode(xe, pat_index);
2786 		if (XE_IOCTL_DBG(xe, !coh_mode)) { /* hw reserved */
2787 			err = -EINVAL;
2788 			goto free_bind_ops;
2789 		}
2790 
2791 		if (XE_WARN_ON(coh_mode > XE_COH_AT_LEAST_1WAY)) {
2792 			err = -EINVAL;
2793 			goto free_bind_ops;
2794 		}
2795 
2796 		if (XE_IOCTL_DBG(xe, op > DRM_XE_VM_BIND_OP_PREFETCH) ||
2797 		    XE_IOCTL_DBG(xe, flags & ~SUPPORTED_FLAGS) ||
2798 		    XE_IOCTL_DBG(xe, obj && is_null) ||
2799 		    XE_IOCTL_DBG(xe, obj_offset && is_null) ||
2800 		    XE_IOCTL_DBG(xe, op != DRM_XE_VM_BIND_OP_MAP &&
2801 				 is_null) ||
2802 		    XE_IOCTL_DBG(xe, !obj &&
2803 				 op == DRM_XE_VM_BIND_OP_MAP &&
2804 				 !is_null) ||
2805 		    XE_IOCTL_DBG(xe, !obj &&
2806 				 op == DRM_XE_VM_BIND_OP_UNMAP_ALL) ||
2807 		    XE_IOCTL_DBG(xe, addr &&
2808 				 op == DRM_XE_VM_BIND_OP_UNMAP_ALL) ||
2809 		    XE_IOCTL_DBG(xe, range &&
2810 				 op == DRM_XE_VM_BIND_OP_UNMAP_ALL) ||
2811 		    XE_IOCTL_DBG(xe, obj &&
2812 				 op == DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
2813 		    XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE &&
2814 				 op == DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
2815 		    XE_IOCTL_DBG(xe, obj &&
2816 				 op == DRM_XE_VM_BIND_OP_PREFETCH) ||
2817 		    XE_IOCTL_DBG(xe, prefetch_region &&
2818 				 op != DRM_XE_VM_BIND_OP_PREFETCH) ||
2819 		    XE_IOCTL_DBG(xe, !(BIT(prefetch_region) &
2820 				       xe->info.mem_region_mask)) ||
2821 		    XE_IOCTL_DBG(xe, obj &&
2822 				 op == DRM_XE_VM_BIND_OP_UNMAP)) {
2823 			err = -EINVAL;
2824 			goto free_bind_ops;
2825 		}
2826 
2827 		if (XE_IOCTL_DBG(xe, obj_offset & ~PAGE_MASK) ||
2828 		    XE_IOCTL_DBG(xe, addr & ~PAGE_MASK) ||
2829 		    XE_IOCTL_DBG(xe, range & ~PAGE_MASK) ||
2830 		    XE_IOCTL_DBG(xe, !range &&
2831 				 op != DRM_XE_VM_BIND_OP_UNMAP_ALL)) {
2832 			err = -EINVAL;
2833 			goto free_bind_ops;
2834 		}
2835 	}
2836 
2837 	return 0;
2838 
2839 free_bind_ops:
2840 	if (args->num_binds > 1)
2841 		kfree(*bind_ops);
2842 	return err;
2843 }
2844 
2845 static int vm_bind_ioctl_signal_fences(struct xe_vm *vm,
2846 				       struct xe_exec_queue *q,
2847 				       struct xe_sync_entry *syncs,
2848 				       int num_syncs)
2849 {
2850 	struct dma_fence *fence;
2851 	int i, err = 0;
2852 
2853 	fence = xe_sync_in_fence_get(syncs, num_syncs,
2854 				     to_wait_exec_queue(vm, q), vm);
2855 	if (IS_ERR(fence))
2856 		return PTR_ERR(fence);
2857 
2858 	for (i = 0; i < num_syncs; i++)
2859 		xe_sync_entry_signal(&syncs[i], NULL, fence);
2860 
2861 	xe_exec_queue_last_fence_set(to_wait_exec_queue(vm, q), vm,
2862 				     fence);
2863 	dma_fence_put(fence);
2864 
2865 	return err;
2866 }
2867 
2868 int xe_vm_bind_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2869 {
2870 	struct xe_device *xe = to_xe_device(dev);
2871 	struct xe_file *xef = to_xe_file(file);
2872 	struct drm_xe_vm_bind *args = data;
2873 	struct drm_xe_sync __user *syncs_user;
2874 	struct xe_bo **bos = NULL;
2875 	struct drm_gpuva_ops **ops = NULL;
2876 	struct xe_vm *vm;
2877 	struct xe_exec_queue *q = NULL;
2878 	u32 num_syncs, num_ufence = 0;
2879 	struct xe_sync_entry *syncs = NULL;
2880 	struct drm_xe_vm_bind_op *bind_ops;
2881 	LIST_HEAD(ops_list);
2882 	int err;
2883 	int i;
2884 
2885 	err = vm_bind_ioctl_check_args(xe, args, &bind_ops);
2886 	if (err)
2887 		return err;
2888 
2889 	if (args->exec_queue_id) {
2890 		q = xe_exec_queue_lookup(xef, args->exec_queue_id);
2891 		if (XE_IOCTL_DBG(xe, !q)) {
2892 			err = -ENOENT;
2893 			goto free_objs;
2894 		}
2895 
2896 		if (XE_IOCTL_DBG(xe, !(q->flags & EXEC_QUEUE_FLAG_VM))) {
2897 			err = -EINVAL;
2898 			goto put_exec_queue;
2899 		}
2900 	}
2901 
2902 	vm = xe_vm_lookup(xef, args->vm_id);
2903 	if (XE_IOCTL_DBG(xe, !vm)) {
2904 		err = -EINVAL;
2905 		goto put_exec_queue;
2906 	}
2907 
2908 	err = down_write_killable(&vm->lock);
2909 	if (err)
2910 		goto put_vm;
2911 
2912 	if (XE_IOCTL_DBG(xe, xe_vm_is_closed_or_banned(vm))) {
2913 		err = -ENOENT;
2914 		goto release_vm_lock;
2915 	}
2916 
2917 	for (i = 0; i < args->num_binds; ++i) {
2918 		u64 range = bind_ops[i].range;
2919 		u64 addr = bind_ops[i].addr;
2920 
2921 		if (XE_IOCTL_DBG(xe, range > vm->size) ||
2922 		    XE_IOCTL_DBG(xe, addr > vm->size - range)) {
2923 			err = -EINVAL;
2924 			goto release_vm_lock;
2925 		}
2926 	}
2927 
2928 	if (args->num_binds) {
2929 		bos = kcalloc(args->num_binds, sizeof(*bos), GFP_KERNEL);
2930 		if (!bos) {
2931 			err = -ENOMEM;
2932 			goto release_vm_lock;
2933 		}
2934 
2935 		ops = kcalloc(args->num_binds, sizeof(*ops), GFP_KERNEL);
2936 		if (!ops) {
2937 			err = -ENOMEM;
2938 			goto release_vm_lock;
2939 		}
2940 	}
2941 
2942 	for (i = 0; i < args->num_binds; ++i) {
2943 		struct drm_gem_object *gem_obj;
2944 		u64 range = bind_ops[i].range;
2945 		u64 addr = bind_ops[i].addr;
2946 		u32 obj = bind_ops[i].obj;
2947 		u64 obj_offset = bind_ops[i].obj_offset;
2948 		u16 pat_index = bind_ops[i].pat_index;
2949 		u16 coh_mode;
2950 
2951 		if (!obj)
2952 			continue;
2953 
2954 		gem_obj = drm_gem_object_lookup(file, obj);
2955 		if (XE_IOCTL_DBG(xe, !gem_obj)) {
2956 			err = -ENOENT;
2957 			goto put_obj;
2958 		}
2959 		bos[i] = gem_to_xe_bo(gem_obj);
2960 
2961 		if (XE_IOCTL_DBG(xe, range > bos[i]->size) ||
2962 		    XE_IOCTL_DBG(xe, obj_offset >
2963 				 bos[i]->size - range)) {
2964 			err = -EINVAL;
2965 			goto put_obj;
2966 		}
2967 
2968 		if (bos[i]->flags & XE_BO_INTERNAL_64K) {
2969 			if (XE_IOCTL_DBG(xe, obj_offset &
2970 					 XE_64K_PAGE_MASK) ||
2971 			    XE_IOCTL_DBG(xe, addr & XE_64K_PAGE_MASK) ||
2972 			    XE_IOCTL_DBG(xe, range & XE_64K_PAGE_MASK)) {
2973 				err = -EINVAL;
2974 				goto put_obj;
2975 			}
2976 		}
2977 
2978 		coh_mode = xe_pat_index_get_coh_mode(xe, pat_index);
2979 		if (bos[i]->cpu_caching) {
2980 			if (XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE &&
2981 					 bos[i]->cpu_caching == DRM_XE_GEM_CPU_CACHING_WB)) {
2982 				err = -EINVAL;
2983 				goto put_obj;
2984 			}
2985 		} else if (XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE)) {
2986 			/*
2987 			 * Imported dma-buf from a different device should
2988 			 * require 1way or 2way coherency since we don't know
2989 			 * how it was mapped on the CPU. Just assume is it
2990 			 * potentially cached on CPU side.
2991 			 */
2992 			err = -EINVAL;
2993 			goto put_obj;
2994 		}
2995 	}
2996 
2997 	if (args->num_syncs) {
2998 		syncs = kcalloc(args->num_syncs, sizeof(*syncs), GFP_KERNEL);
2999 		if (!syncs) {
3000 			err = -ENOMEM;
3001 			goto put_obj;
3002 		}
3003 	}
3004 
3005 	syncs_user = u64_to_user_ptr(args->syncs);
3006 	for (num_syncs = 0; num_syncs < args->num_syncs; num_syncs++) {
3007 		err = xe_sync_entry_parse(xe, xef, &syncs[num_syncs],
3008 					  &syncs_user[num_syncs],
3009 					  (xe_vm_in_lr_mode(vm) ?
3010 					   SYNC_PARSE_FLAG_LR_MODE : 0) |
3011 					  (!args->num_binds ?
3012 					   SYNC_PARSE_FLAG_DISALLOW_USER_FENCE : 0));
3013 		if (err)
3014 			goto free_syncs;
3015 
3016 		if (xe_sync_is_ufence(&syncs[num_syncs]))
3017 			num_ufence++;
3018 	}
3019 
3020 	if (XE_IOCTL_DBG(xe, num_ufence > 1)) {
3021 		err = -EINVAL;
3022 		goto free_syncs;
3023 	}
3024 
3025 	if (!args->num_binds) {
3026 		err = -ENODATA;
3027 		goto free_syncs;
3028 	}
3029 
3030 	for (i = 0; i < args->num_binds; ++i) {
3031 		u64 range = bind_ops[i].range;
3032 		u64 addr = bind_ops[i].addr;
3033 		u32 op = bind_ops[i].op;
3034 		u32 flags = bind_ops[i].flags;
3035 		u64 obj_offset = bind_ops[i].obj_offset;
3036 		u32 prefetch_region = bind_ops[i].prefetch_mem_region_instance;
3037 		u16 pat_index = bind_ops[i].pat_index;
3038 
3039 		ops[i] = vm_bind_ioctl_ops_create(vm, bos[i], obj_offset,
3040 						  addr, range, op, flags,
3041 						  prefetch_region, pat_index);
3042 		if (IS_ERR(ops[i])) {
3043 			err = PTR_ERR(ops[i]);
3044 			ops[i] = NULL;
3045 			goto unwind_ops;
3046 		}
3047 
3048 		err = vm_bind_ioctl_ops_parse(vm, q, ops[i], syncs, num_syncs,
3049 					      &ops_list,
3050 					      i == args->num_binds - 1);
3051 		if (err)
3052 			goto unwind_ops;
3053 	}
3054 
3055 	/* Nothing to do */
3056 	if (list_empty(&ops_list)) {
3057 		err = -ENODATA;
3058 		goto unwind_ops;
3059 	}
3060 
3061 	xe_vm_get(vm);
3062 	if (q)
3063 		xe_exec_queue_get(q);
3064 
3065 	err = vm_bind_ioctl_ops_execute(vm, &ops_list);
3066 
3067 	up_write(&vm->lock);
3068 
3069 	if (q)
3070 		xe_exec_queue_put(q);
3071 	xe_vm_put(vm);
3072 
3073 	for (i = 0; bos && i < args->num_binds; ++i)
3074 		xe_bo_put(bos[i]);
3075 
3076 	kfree(bos);
3077 	kfree(ops);
3078 	if (args->num_binds > 1)
3079 		kfree(bind_ops);
3080 
3081 	return err;
3082 
3083 unwind_ops:
3084 	vm_bind_ioctl_ops_unwind(vm, ops, args->num_binds);
3085 free_syncs:
3086 	if (err == -ENODATA)
3087 		err = vm_bind_ioctl_signal_fences(vm, q, syncs, num_syncs);
3088 	while (num_syncs--)
3089 		xe_sync_entry_cleanup(&syncs[num_syncs]);
3090 
3091 	kfree(syncs);
3092 put_obj:
3093 	for (i = 0; i < args->num_binds; ++i)
3094 		xe_bo_put(bos[i]);
3095 release_vm_lock:
3096 	up_write(&vm->lock);
3097 put_vm:
3098 	xe_vm_put(vm);
3099 put_exec_queue:
3100 	if (q)
3101 		xe_exec_queue_put(q);
3102 free_objs:
3103 	kfree(bos);
3104 	kfree(ops);
3105 	if (args->num_binds > 1)
3106 		kfree(bind_ops);
3107 	return err;
3108 }
3109 
3110 /**
3111  * xe_vm_lock() - Lock the vm's dma_resv object
3112  * @vm: The struct xe_vm whose lock is to be locked
3113  * @intr: Whether to perform any wait interruptible
3114  *
3115  * Return: 0 on success, -EINTR if @intr is true and the wait for a
3116  * contended lock was interrupted. If @intr is false, the function
3117  * always returns 0.
3118  */
3119 int xe_vm_lock(struct xe_vm *vm, bool intr)
3120 {
3121 	if (intr)
3122 		return dma_resv_lock_interruptible(xe_vm_resv(vm), NULL);
3123 
3124 	return dma_resv_lock(xe_vm_resv(vm), NULL);
3125 }
3126 
3127 /**
3128  * xe_vm_unlock() - Unlock the vm's dma_resv object
3129  * @vm: The struct xe_vm whose lock is to be released.
3130  *
3131  * Unlock a buffer object lock that was locked by xe_vm_lock().
3132  */
3133 void xe_vm_unlock(struct xe_vm *vm)
3134 {
3135 	dma_resv_unlock(xe_vm_resv(vm));
3136 }
3137 
3138 /**
3139  * xe_vm_invalidate_vma - invalidate GPU mappings for VMA without a lock
3140  * @vma: VMA to invalidate
3141  *
3142  * Walks a list of page tables leaves which it memset the entries owned by this
3143  * VMA to zero, invalidates the TLBs, and block until TLBs invalidation is
3144  * complete.
3145  *
3146  * Returns 0 for success, negative error code otherwise.
3147  */
3148 int xe_vm_invalidate_vma(struct xe_vma *vma)
3149 {
3150 	struct xe_device *xe = xe_vma_vm(vma)->xe;
3151 	struct xe_tile *tile;
3152 	u32 tile_needs_invalidate = 0;
3153 	int seqno[XE_MAX_TILES_PER_DEVICE];
3154 	u8 id;
3155 	int ret;
3156 
3157 	xe_assert(xe, xe_vm_in_fault_mode(xe_vma_vm(vma)));
3158 	xe_assert(xe, !xe_vma_is_null(vma));
3159 	trace_xe_vma_usm_invalidate(vma);
3160 
3161 	/* Check that we don't race with page-table updates */
3162 	if (IS_ENABLED(CONFIG_PROVE_LOCKING)) {
3163 		if (xe_vma_is_userptr(vma)) {
3164 			WARN_ON_ONCE(!mmu_interval_check_retry
3165 				     (&to_userptr_vma(vma)->userptr.notifier,
3166 				      to_userptr_vma(vma)->userptr.notifier_seq));
3167 			WARN_ON_ONCE(!dma_resv_test_signaled(xe_vm_resv(xe_vma_vm(vma)),
3168 							     DMA_RESV_USAGE_BOOKKEEP));
3169 
3170 		} else {
3171 			xe_bo_assert_held(xe_vma_bo(vma));
3172 		}
3173 	}
3174 
3175 	for_each_tile(tile, xe, id) {
3176 		if (xe_pt_zap_ptes(tile, vma)) {
3177 			tile_needs_invalidate |= BIT(id);
3178 			xe_device_wmb(xe);
3179 			/*
3180 			 * FIXME: We potentially need to invalidate multiple
3181 			 * GTs within the tile
3182 			 */
3183 			seqno[id] = xe_gt_tlb_invalidation_vma(tile->primary_gt, NULL, vma);
3184 			if (seqno[id] < 0)
3185 				return seqno[id];
3186 		}
3187 	}
3188 
3189 	for_each_tile(tile, xe, id) {
3190 		if (tile_needs_invalidate & BIT(id)) {
3191 			ret = xe_gt_tlb_invalidation_wait(tile->primary_gt, seqno[id]);
3192 			if (ret < 0)
3193 				return ret;
3194 		}
3195 	}
3196 
3197 	vma->usm.tile_invalidated = vma->tile_mask;
3198 
3199 	return 0;
3200 }
3201 
3202 int xe_analyze_vm(struct drm_printer *p, struct xe_vm *vm, int gt_id)
3203 {
3204 	struct drm_gpuva *gpuva;
3205 	bool is_vram;
3206 	uint64_t addr;
3207 
3208 	if (!down_read_trylock(&vm->lock)) {
3209 		drm_printf(p, " Failed to acquire VM lock to dump capture");
3210 		return 0;
3211 	}
3212 	if (vm->pt_root[gt_id]) {
3213 		addr = xe_bo_addr(vm->pt_root[gt_id]->bo, 0, XE_PAGE_SIZE);
3214 		is_vram = xe_bo_is_vram(vm->pt_root[gt_id]->bo);
3215 		drm_printf(p, " VM root: A:0x%llx %s\n", addr,
3216 			   is_vram ? "VRAM" : "SYS");
3217 	}
3218 
3219 	drm_gpuvm_for_each_va(gpuva, &vm->gpuvm) {
3220 		struct xe_vma *vma = gpuva_to_vma(gpuva);
3221 		bool is_userptr = xe_vma_is_userptr(vma);
3222 		bool is_null = xe_vma_is_null(vma);
3223 
3224 		if (is_null) {
3225 			addr = 0;
3226 		} else if (is_userptr) {
3227 			struct sg_table *sg = to_userptr_vma(vma)->userptr.sg;
3228 			struct xe_res_cursor cur;
3229 
3230 			if (sg) {
3231 				xe_res_first_sg(sg, 0, XE_PAGE_SIZE, &cur);
3232 				addr = xe_res_dma(&cur);
3233 			} else {
3234 				addr = 0;
3235 			}
3236 		} else {
3237 			addr = __xe_bo_addr(xe_vma_bo(vma), 0, XE_PAGE_SIZE);
3238 			is_vram = xe_bo_is_vram(xe_vma_bo(vma));
3239 		}
3240 		drm_printf(p, " [%016llx-%016llx] S:0x%016llx A:%016llx %s\n",
3241 			   xe_vma_start(vma), xe_vma_end(vma) - 1,
3242 			   xe_vma_size(vma),
3243 			   addr, is_null ? "NULL" : is_userptr ? "USR" :
3244 			   is_vram ? "VRAM" : "SYS");
3245 	}
3246 	up_read(&vm->lock);
3247 
3248 	return 0;
3249 }
3250