1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_tuning.h" 7 8 #include <kunit/visibility.h> 9 10 #include "regs/xe_gt_regs.h" 11 #include "xe_gt_types.h" 12 #include "xe_platform_types.h" 13 #include "xe_rtp.h" 14 15 #undef XE_REG_MCR 16 #define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1) 17 18 static const struct xe_rtp_entry_sr gt_tunings[] = { 19 { XE_RTP_NAME("Tuning: Blend Fill Caching Optimization Disable"), 20 XE_RTP_RULES(PLATFORM(DG2)), 21 XE_RTP_ACTIONS(SET(XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS)) 22 }, 23 { XE_RTP_NAME("Tuning: 32B Access Enable"), 24 XE_RTP_RULES(PLATFORM(DG2)), 25 XE_RTP_ACTIONS(SET(XEHP_SQCM, EN_32B_ACCESS)) 26 }, 27 28 /* Xe2 */ 29 30 { XE_RTP_NAME("Tuning: L3 cache"), 31 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)), 32 XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK, 33 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f))) 34 }, 35 { XE_RTP_NAME("Tuning: L3 cache - media"), 36 XE_RTP_RULES(MEDIA_VERSION(2000)), 37 XE_RTP_ACTIONS(FIELD_SET(XE2LPM_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK, 38 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f))) 39 }, 40 { XE_RTP_NAME("Tuning: Compression Overfetch"), 41 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)), 42 XE_RTP_ACTIONS(CLR(CCCHKNREG1, ENCOMPPERFFIX), 43 SET(CCCHKNREG1, L3CMPCTRL)) 44 }, 45 { XE_RTP_NAME("Tuning: Enable compressible partial write overfetch in L3"), 46 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)), 47 XE_RTP_ACTIONS(SET(L3SQCREG3, COMPPWOVERFETCHEN)) 48 }, 49 { XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only"), 50 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)), 51 XE_RTP_ACTIONS(SET(L3SQCREG2, 52 COMPMEMRD256BOVRFETCHEN)) 53 }, 54 { XE_RTP_NAME("Tuning: Stateless compression control"), 55 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)), 56 XE_RTP_ACTIONS(FIELD_SET(STATELESS_COMPRESSION_CTRL, UNIFIED_COMPRESSION_FORMAT, 57 REG_FIELD_PREP(UNIFIED_COMPRESSION_FORMAT, 0))) 58 }, 59 {} 60 }; 61 62 static const struct xe_rtp_entry_sr engine_tunings[] = { 63 { XE_RTP_NAME("Tuning: Set Indirect State Override"), 64 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1274), 65 ENGINE_CLASS(RENDER)), 66 XE_RTP_ACTIONS(SET(SAMPLER_MODE, INDIRECT_STATE_BASE_ADDR_OVERRIDE)) 67 }, 68 {} 69 }; 70 71 static const struct xe_rtp_entry_sr lrc_tunings[] = { 72 { XE_RTP_NAME("Tuning: ganged timer, also known as 16011163337"), 73 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 74 /* read verification is ignored due to 1608008084. */ 75 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2, 76 FF_MODE2_GS_TIMER_MASK, 77 FF_MODE2_GS_TIMER_224)) 78 }, 79 80 /* DG2 */ 81 82 { XE_RTP_NAME("Tuning: L3 cache"), 83 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 84 XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK, 85 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f))) 86 }, 87 { XE_RTP_NAME("Tuning: TDS gang timer"), 88 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 89 /* read verification is ignored as in i915 - need to check enabling */ 90 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(XEHP_FF_MODE2, 91 FF_MODE2_TDS_TIMER_MASK, 92 FF_MODE2_TDS_TIMER_128)) 93 }, 94 { XE_RTP_NAME("Tuning: TBIMR fast clip"), 95 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 96 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_2, TBIMR_FAST_CLIP)) 97 }, 98 99 /* Xe_LPG */ 100 101 { XE_RTP_NAME("Tuning: L3 cache"), 102 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), ENGINE_CLASS(RENDER)), 103 XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK, 104 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f))) 105 }, 106 107 /* Xe2_HPG */ 108 109 { XE_RTP_NAME("Tuning: vs hit max value"), 110 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 111 XE_RTP_ACTIONS(FIELD_SET(FF_MODE, VS_HIT_MAX_VALUE_MASK, 112 REG_FIELD_PREP(VS_HIT_MAX_VALUE_MASK, 0x3f))) 113 }, 114 115 {} 116 }; 117 118 void xe_tuning_process_gt(struct xe_gt *gt) 119 { 120 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt); 121 122 xe_rtp_process_to_sr(&ctx, gt_tunings, >->reg_sr); 123 } 124 EXPORT_SYMBOL_IF_KUNIT(xe_tuning_process_gt); 125 126 void xe_tuning_process_engine(struct xe_hw_engine *hwe) 127 { 128 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); 129 130 xe_rtp_process_to_sr(&ctx, engine_tunings, &hwe->reg_sr); 131 } 132 EXPORT_SYMBOL_IF_KUNIT(xe_tuning_process_engine); 133 134 /** 135 * xe_tuning_process_lrc - process lrc tunings 136 * @hwe: engine instance to process tunings for 137 * 138 * Process LRC table for this platform, saving in @hwe all the tunings that need 139 * to be applied on context restore. These are tunings touching registers that 140 * are part of the HW context image. 141 */ 142 void xe_tuning_process_lrc(struct xe_hw_engine *hwe) 143 { 144 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); 145 146 xe_rtp_process_to_sr(&ctx, lrc_tunings, &hwe->reg_lrc); 147 } 148