1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_tuning.h" 7 8 #include <kunit/visibility.h> 9 10 #include "regs/xe_gt_regs.h" 11 #include "xe_gt_types.h" 12 #include "xe_platform_types.h" 13 #include "xe_rtp.h" 14 15 #undef XE_REG_MCR 16 #define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1) 17 18 static const struct xe_rtp_entry_sr gt_tunings[] = { 19 { XE_RTP_NAME("Tuning: Blend Fill Caching Optimization Disable"), 20 XE_RTP_RULES(PLATFORM(DG2)), 21 XE_RTP_ACTIONS(SET(XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS)) 22 }, 23 { XE_RTP_NAME("Tuning: 32B Access Enable"), 24 XE_RTP_RULES(PLATFORM(DG2)), 25 XE_RTP_ACTIONS(SET(XEHP_SQCM, EN_32B_ACCESS)) 26 }, 27 28 /* Xe2 */ 29 30 { XE_RTP_NAME("Tuning: L3 cache"), 31 XE_RTP_RULES(GRAPHICS_VERSION(2004)), 32 XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK, 33 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f))) 34 }, 35 { XE_RTP_NAME("Tuning: L3 cache - media"), 36 XE_RTP_RULES(MEDIA_VERSION(2000)), 37 XE_RTP_ACTIONS(FIELD_SET(XE2LPM_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK, 38 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f))) 39 }, 40 41 {} 42 }; 43 44 static const struct xe_rtp_entry_sr engine_tunings[] = { 45 { XE_RTP_NAME("Tuning: Set Indirect State Override"), 46 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1271), 47 ENGINE_CLASS(RENDER)), 48 XE_RTP_ACTIONS(SET(SAMPLER_MODE, INDIRECT_STATE_BASE_ADDR_OVERRIDE)) 49 }, 50 {} 51 }; 52 53 static const struct xe_rtp_entry_sr lrc_tunings[] = { 54 { XE_RTP_NAME("Tuning: ganged timer, also known as 16011163337"), 55 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 56 /* read verification is ignored due to 1608008084. */ 57 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2, 58 FF_MODE2_GS_TIMER_MASK, 59 FF_MODE2_GS_TIMER_224)) 60 }, 61 62 /* DG2 */ 63 64 { XE_RTP_NAME("Tuning: L3 cache"), 65 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 66 XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK, 67 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f))) 68 }, 69 { XE_RTP_NAME("Tuning: TDS gang timer"), 70 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 71 /* read verification is ignored as in i915 - need to check enabling */ 72 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(XEHP_FF_MODE2, 73 FF_MODE2_TDS_TIMER_MASK, 74 FF_MODE2_TDS_TIMER_128)) 75 }, 76 { XE_RTP_NAME("Tuning: TBIMR fast clip"), 77 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 78 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_2, TBIMR_FAST_CLIP)) 79 }, 80 81 /* Xe_LPG */ 82 83 { XE_RTP_NAME("Tuning: L3 cache"), 84 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), ENGINE_CLASS(RENDER)), 85 XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK, 86 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f))) 87 }, 88 89 {} 90 }; 91 92 void xe_tuning_process_gt(struct xe_gt *gt) 93 { 94 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt); 95 96 xe_rtp_process_to_sr(&ctx, gt_tunings, >->reg_sr); 97 } 98 EXPORT_SYMBOL_IF_KUNIT(xe_tuning_process_gt); 99 100 void xe_tuning_process_engine(struct xe_hw_engine *hwe) 101 { 102 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); 103 104 xe_rtp_process_to_sr(&ctx, engine_tunings, &hwe->reg_sr); 105 } 106 EXPORT_SYMBOL_IF_KUNIT(xe_tuning_process_engine); 107 108 /** 109 * xe_tuning_process_lrc - process lrc tunings 110 * @hwe: engine instance to process tunings for 111 * 112 * Process LRC table for this platform, saving in @hwe all the tunings that need 113 * to be applied on context restore. These are tunings touching registers that 114 * are part of the HW context image. 115 */ 116 void xe_tuning_process_lrc(struct xe_hw_engine *hwe) 117 { 118 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); 119 120 xe_rtp_process_to_sr(&ctx, lrc_tunings, &hwe->reg_lrc); 121 } 122