1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_tuning.h" 7 8 #include <kunit/visibility.h> 9 10 #include "regs/xe_gt_regs.h" 11 #include "xe_gt_types.h" 12 #include "xe_platform_types.h" 13 #include "xe_rtp.h" 14 15 #undef XE_REG_MCR 16 #define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1) 17 18 static const struct xe_rtp_entry_sr gt_tunings[] = { 19 { XE_RTP_NAME("Tuning: Blend Fill Caching Optimization Disable"), 20 XE_RTP_RULES(PLATFORM(DG2)), 21 XE_RTP_ACTIONS(SET(XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS)) 22 }, 23 { XE_RTP_NAME("Tuning: 32B Access Enable"), 24 XE_RTP_RULES(PLATFORM(DG2)), 25 XE_RTP_ACTIONS(SET(XEHP_SQCM, EN_32B_ACCESS)) 26 }, 27 28 /* Xe2 */ 29 30 { XE_RTP_NAME("Tuning: L3 cache"), 31 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)), 32 XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK, 33 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f))) 34 }, 35 { XE_RTP_NAME("Tuning: L3 cache - media"), 36 XE_RTP_RULES(MEDIA_VERSION(2000)), 37 XE_RTP_ACTIONS(FIELD_SET(XE2LPM_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK, 38 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f))) 39 }, 40 { XE_RTP_NAME("Tuning: Compression Overfetch"), 41 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)), 42 XE_RTP_ACTIONS(CLR(CCCHKNREG1, ENCOMPPERFFIX)), 43 }, 44 { XE_RTP_NAME("Tuning: Enable compressible partial write overfetch in L3"), 45 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)), 46 XE_RTP_ACTIONS(SET(L3SQCREG3, COMPPWOVERFETCHEN)) 47 }, 48 {} 49 }; 50 51 static const struct xe_rtp_entry_sr engine_tunings[] = { 52 { XE_RTP_NAME("Tuning: Set Indirect State Override"), 53 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1274), 54 ENGINE_CLASS(RENDER)), 55 XE_RTP_ACTIONS(SET(SAMPLER_MODE, INDIRECT_STATE_BASE_ADDR_OVERRIDE)) 56 }, 57 {} 58 }; 59 60 static const struct xe_rtp_entry_sr lrc_tunings[] = { 61 { XE_RTP_NAME("Tuning: ganged timer, also known as 16011163337"), 62 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 63 /* read verification is ignored due to 1608008084. */ 64 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2, 65 FF_MODE2_GS_TIMER_MASK, 66 FF_MODE2_GS_TIMER_224)) 67 }, 68 69 /* DG2 */ 70 71 { XE_RTP_NAME("Tuning: L3 cache"), 72 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 73 XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK, 74 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f))) 75 }, 76 { XE_RTP_NAME("Tuning: TDS gang timer"), 77 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 78 /* read verification is ignored as in i915 - need to check enabling */ 79 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(XEHP_FF_MODE2, 80 FF_MODE2_TDS_TIMER_MASK, 81 FF_MODE2_TDS_TIMER_128)) 82 }, 83 { XE_RTP_NAME("Tuning: TBIMR fast clip"), 84 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 85 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_2, TBIMR_FAST_CLIP)) 86 }, 87 88 /* Xe_LPG */ 89 90 { XE_RTP_NAME("Tuning: L3 cache"), 91 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), ENGINE_CLASS(RENDER)), 92 XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK, 93 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f))) 94 }, 95 96 {} 97 }; 98 99 void xe_tuning_process_gt(struct xe_gt *gt) 100 { 101 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt); 102 103 xe_rtp_process_to_sr(&ctx, gt_tunings, >->reg_sr); 104 } 105 EXPORT_SYMBOL_IF_KUNIT(xe_tuning_process_gt); 106 107 void xe_tuning_process_engine(struct xe_hw_engine *hwe) 108 { 109 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); 110 111 xe_rtp_process_to_sr(&ctx, engine_tunings, &hwe->reg_sr); 112 } 113 EXPORT_SYMBOL_IF_KUNIT(xe_tuning_process_engine); 114 115 /** 116 * xe_tuning_process_lrc - process lrc tunings 117 * @hwe: engine instance to process tunings for 118 * 119 * Process LRC table for this platform, saving in @hwe all the tunings that need 120 * to be applied on context restore. These are tunings touching registers that 121 * are part of the HW context image. 122 */ 123 void xe_tuning_process_lrc(struct xe_hw_engine *hwe) 124 { 125 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); 126 127 xe_rtp_process_to_sr(&ctx, lrc_tunings, &hwe->reg_lrc); 128 } 129