1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_tuning.h" 7 8 #include <kunit/visibility.h> 9 10 #include "regs/xe_gt_regs.h" 11 #include "xe_gt_types.h" 12 #include "xe_platform_types.h" 13 #include "xe_rtp.h" 14 15 #undef XE_REG_MCR 16 #define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1) 17 18 static const struct xe_rtp_entry_sr gt_tunings[] = { 19 { XE_RTP_NAME("Tuning: Blend Fill Caching Optimization Disable"), 20 XE_RTP_RULES(PLATFORM(DG2)), 21 XE_RTP_ACTIONS(SET(XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS)) 22 }, 23 { XE_RTP_NAME("Tuning: 32B Access Enable"), 24 XE_RTP_RULES(PLATFORM(DG2)), 25 XE_RTP_ACTIONS(SET(XEHP_SQCM, EN_32B_ACCESS)) 26 }, 27 {} 28 }; 29 30 static const struct xe_rtp_entry_sr lrc_tunings[] = { 31 { XE_RTP_NAME("Tuning: ganged timer, also known as 16011163337"), 32 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), 33 /* read verification is ignored due to 1608008084. */ 34 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2, 35 FF_MODE2_GS_TIMER_MASK, 36 FF_MODE2_GS_TIMER_224)) 37 }, 38 39 /* DG2 */ 40 41 { XE_RTP_NAME("Tuning: L3 cache"), 42 XE_RTP_RULES(PLATFORM(DG2)), 43 XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK, 44 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f))) 45 }, 46 { XE_RTP_NAME("Tuning: TDS gang timer"), 47 XE_RTP_RULES(PLATFORM(DG2)), 48 /* read verification is ignored as in i915 - need to check enabling */ 49 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(XEHP_FF_MODE2, 50 FF_MODE2_TDS_TIMER_MASK, 51 FF_MODE2_TDS_TIMER_128)) 52 }, 53 { XE_RTP_NAME("Tuning: TBIMR fast clip"), 54 XE_RTP_RULES(PLATFORM(DG2)), 55 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_2, TBIMR_FAST_CLIP)) 56 }, 57 {} 58 }; 59 60 void xe_tuning_process_gt(struct xe_gt *gt) 61 { 62 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt); 63 64 xe_rtp_process_to_sr(&ctx, gt_tunings, >->reg_sr); 65 } 66 EXPORT_SYMBOL_IF_KUNIT(xe_tuning_process_gt); 67 68 /** 69 * xe_tuning_process_lrc - process lrc tunings 70 * @hwe: engine instance to process tunings for 71 * 72 * Process LRC table for this platform, saving in @hwe all the tunings that need 73 * to be applied on context restore. These are tunings touching registers that 74 * are part of the HW context image. 75 */ 76 void xe_tuning_process_lrc(struct xe_hw_engine *hwe) 77 { 78 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); 79 80 xe_rtp_process_to_sr(&ctx, lrc_tunings, &hwe->reg_lrc); 81 } 82