1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #include <linux/fault-inject.h> 7 8 #include <drm/drm_managed.h> 9 10 #include "xe_device.h" 11 #include "xe_ggtt.h" 12 #include "xe_gt.h" 13 #include "xe_migrate.h" 14 #include "xe_pcode.h" 15 #include "xe_sa.h" 16 #include "xe_tile.h" 17 #include "xe_tile_sysfs.h" 18 #include "xe_ttm_vram_mgr.h" 19 #include "xe_wa.h" 20 21 /** 22 * DOC: Multi-tile Design 23 * 24 * Different vendors use the term "tile" a bit differently, but in the Intel 25 * world, a 'tile' is pretty close to what most people would think of as being 26 * a complete GPU. When multiple GPUs are placed behind a single PCI device, 27 * that's what is referred to as a "multi-tile device." In such cases, pretty 28 * much all hardware is replicated per-tile, although certain responsibilities 29 * like PCI communication, reporting of interrupts to the OS, etc. are handled 30 * solely by the "root tile." A multi-tile platform takes care of tying the 31 * tiles together in a way such that interrupt notifications from remote tiles 32 * are forwarded to the root tile, the per-tile vram is combined into a single 33 * address space, etc. 34 * 35 * In contrast, a "GT" (which officially stands for "Graphics Technology") is 36 * the subset of a GPU/tile that is responsible for implementing graphics 37 * and/or media operations. The GT is where a lot of the driver implementation 38 * happens since it's where the hardware engines, the execution units, and the 39 * GuC all reside. 40 * 41 * Historically most Intel devices were single-tile devices that contained a 42 * single GT. PVC is an example of an Intel platform built on a multi-tile 43 * design (i.e., multiple GPUs behind a single PCI device); each PVC tile only 44 * has a single GT. In contrast, platforms like MTL that have separate chips 45 * for render and media IP are still only a single logical GPU, but the 46 * graphics and media IP blocks are each exposed as a separate GT within that 47 * single GPU. This is important from a software perspective because multi-GT 48 * platforms like MTL only replicate a subset of the GPU hardware and behave 49 * differently than multi-tile platforms like PVC where nearly everything is 50 * replicated. 51 * 52 * Per-tile functionality (shared by all GTs within the tile): 53 * - Complete 4MB MMIO space (containing SGunit/SoC registers, GT 54 * registers, display registers, etc.) 55 * - Global GTT 56 * - VRAM (if discrete) 57 * - Interrupt flows 58 * - Migration context 59 * - kernel batchbuffer pool 60 * - Primary GT 61 * - Media GT (if media version >= 13) 62 * 63 * Per-GT functionality: 64 * - GuC 65 * - Hardware engines 66 * - Programmable hardware units (subslices, EUs) 67 * - GSI subset of registers (multiple copies of these registers reside 68 * within the complete MMIO space provided by the tile, but at different 69 * offsets --- 0 for render, 0x380000 for media) 70 * - Multicast register steering 71 * - TLBs to cache page table translations 72 * - Reset capability 73 * - Low-level power management (e.g., C6) 74 * - Clock frequency 75 * - MOCS and PAT programming 76 */ 77 78 /** 79 * xe_tile_alloc - Perform per-tile memory allocation 80 * @tile: Tile to perform allocations for 81 * 82 * Allocates various per-tile data structures using DRM-managed allocations. 83 * Does not touch the hardware. 84 * 85 * Returns -ENOMEM if allocations fail, otherwise 0. 86 */ 87 static int xe_tile_alloc(struct xe_tile *tile) 88 { 89 struct drm_device *drm = &tile_to_xe(tile)->drm; 90 91 tile->mem.ggtt = drmm_kzalloc(drm, sizeof(*tile->mem.ggtt), 92 GFP_KERNEL); 93 if (!tile->mem.ggtt) 94 return -ENOMEM; 95 tile->mem.ggtt->tile = tile; 96 97 return 0; 98 } 99 100 /** 101 * xe_tile_init_early - Initialize the tile and primary GT 102 * @tile: Tile to initialize 103 * @xe: Parent Xe device 104 * @id: Tile ID 105 * 106 * Initializes per-tile resources that don't require any interactions with the 107 * hardware or any knowledge about the Graphics/Media IP version. 108 * 109 * Returns: 0 on success, negative error code on error. 110 */ 111 int xe_tile_init_early(struct xe_tile *tile, struct xe_device *xe, u8 id) 112 { 113 int err; 114 115 tile->xe = xe; 116 tile->id = id; 117 118 err = xe_tile_alloc(tile); 119 if (err) 120 return err; 121 122 tile->primary_gt = xe_gt_alloc(tile); 123 if (IS_ERR(tile->primary_gt)) 124 return PTR_ERR(tile->primary_gt); 125 126 xe_pcode_init(tile); 127 128 return 0; 129 } 130 ALLOW_ERROR_INJECTION(xe_tile_init_early, ERRNO); /* See xe_pci_probe() */ 131 132 static int tile_ttm_mgr_init(struct xe_tile *tile) 133 { 134 struct xe_device *xe = tile_to_xe(tile); 135 int err; 136 137 if (tile->mem.vram.usable_size) { 138 err = xe_ttm_vram_mgr_init(tile, &tile->mem.vram.ttm); 139 if (err) 140 return err; 141 xe->info.mem_region_mask |= BIT(tile->id) << 1; 142 } 143 144 return 0; 145 } 146 147 /** 148 * xe_tile_init_noalloc - Init tile up to the point where allocations can happen. 149 * @tile: The tile to initialize. 150 * 151 * This function prepares the tile to allow memory allocations to VRAM, but is 152 * not allowed to allocate memory itself. This state is useful for display 153 * readout, because the inherited display framebuffer will otherwise be 154 * overwritten as it is usually put at the start of VRAM. 155 * 156 * Note that since this is tile initialization, it should not perform any 157 * GT-specific operations, and thus does not need to hold GT forcewake. 158 * 159 * Returns: 0 on success, negative error code on error. 160 */ 161 int xe_tile_init_noalloc(struct xe_tile *tile) 162 { 163 int err; 164 165 err = tile_ttm_mgr_init(tile); 166 if (err) 167 return err; 168 169 xe_wa_apply_tile_workarounds(tile); 170 171 return xe_tile_sysfs_init(tile); 172 } 173 174 int xe_tile_init(struct xe_tile *tile) 175 { 176 tile->mem.kernel_bb_pool = xe_sa_bo_manager_init(tile, SZ_1M, 16); 177 if (IS_ERR(tile->mem.kernel_bb_pool)) 178 return PTR_ERR(tile->mem.kernel_bb_pool); 179 180 return 0; 181 } 182 void xe_tile_migrate_wait(struct xe_tile *tile) 183 { 184 xe_migrate_wait(tile->migrate); 185 } 186