1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #include <drm/drm_managed.h> 7 8 #include "xe_device.h" 9 #include "xe_ggtt.h" 10 #include "xe_gt.h" 11 #include "xe_migrate.h" 12 #include "xe_pcode.h" 13 #include "xe_sa.h" 14 #include "xe_tile.h" 15 #include "xe_tile_sysfs.h" 16 #include "xe_ttm_vram_mgr.h" 17 #include "xe_wa.h" 18 19 /** 20 * DOC: Multi-tile Design 21 * 22 * Different vendors use the term "tile" a bit differently, but in the Intel 23 * world, a 'tile' is pretty close to what most people would think of as being 24 * a complete GPU. When multiple GPUs are placed behind a single PCI device, 25 * that's what is referred to as a "multi-tile device." In such cases, pretty 26 * much all hardware is replicated per-tile, although certain responsibilities 27 * like PCI communication, reporting of interrupts to the OS, etc. are handled 28 * solely by the "root tile." A multi-tile platform takes care of tying the 29 * tiles together in a way such that interrupt notifications from remote tiles 30 * are forwarded to the root tile, the per-tile vram is combined into a single 31 * address space, etc. 32 * 33 * In contrast, a "GT" (which officially stands for "Graphics Technology") is 34 * the subset of a GPU/tile that is responsible for implementing graphics 35 * and/or media operations. The GT is where a lot of the driver implementation 36 * happens since it's where the hardware engines, the execution units, and the 37 * GuC all reside. 38 * 39 * Historically most Intel devices were single-tile devices that contained a 40 * single GT. PVC is an example of an Intel platform built on a multi-tile 41 * design (i.e., multiple GPUs behind a single PCI device); each PVC tile only 42 * has a single GT. In contrast, platforms like MTL that have separate chips 43 * for render and media IP are still only a single logical GPU, but the 44 * graphics and media IP blocks are each exposed as a separate GT within that 45 * single GPU. This is important from a software perspective because multi-GT 46 * platforms like MTL only replicate a subset of the GPU hardware and behave 47 * differently than multi-tile platforms like PVC where nearly everything is 48 * replicated. 49 * 50 * Per-tile functionality (shared by all GTs within the tile): 51 * - Complete 4MB MMIO space (containing SGunit/SoC registers, GT 52 * registers, display registers, etc.) 53 * - Global GTT 54 * - VRAM (if discrete) 55 * - Interrupt flows 56 * - Migration context 57 * - kernel batchbuffer pool 58 * - Primary GT 59 * - Media GT (if media version >= 13) 60 * 61 * Per-GT functionality: 62 * - GuC 63 * - Hardware engines 64 * - Programmable hardware units (subslices, EUs) 65 * - GSI subset of registers (multiple copies of these registers reside 66 * within the complete MMIO space provided by the tile, but at different 67 * offsets --- 0 for render, 0x380000 for media) 68 * - Multicast register steering 69 * - TLBs to cache page table translations 70 * - Reset capability 71 * - Low-level power management (e.g., C6) 72 * - Clock frequency 73 * - MOCS and PAT programming 74 */ 75 76 /** 77 * xe_tile_alloc - Perform per-tile memory allocation 78 * @tile: Tile to perform allocations for 79 * 80 * Allocates various per-tile data structures using DRM-managed allocations. 81 * Does not touch the hardware. 82 * 83 * Returns -ENOMEM if allocations fail, otherwise 0. 84 */ 85 static int xe_tile_alloc(struct xe_tile *tile) 86 { 87 struct drm_device *drm = &tile_to_xe(tile)->drm; 88 89 tile->mem.ggtt = drmm_kzalloc(drm, sizeof(*tile->mem.ggtt), 90 GFP_KERNEL); 91 if (!tile->mem.ggtt) 92 return -ENOMEM; 93 tile->mem.ggtt->tile = tile; 94 95 tile->mem.vram_mgr = drmm_kzalloc(drm, sizeof(*tile->mem.vram_mgr), GFP_KERNEL); 96 if (!tile->mem.vram_mgr) 97 return -ENOMEM; 98 99 return 0; 100 } 101 102 /** 103 * xe_tile_init_early - Initialize the tile and primary GT 104 * @tile: Tile to initialize 105 * @xe: Parent Xe device 106 * @id: Tile ID 107 * 108 * Initializes per-tile resources that don't require any interactions with the 109 * hardware or any knowledge about the Graphics/Media IP version. 110 * 111 * Returns: 0 on success, negative error code on error. 112 */ 113 int xe_tile_init_early(struct xe_tile *tile, struct xe_device *xe, u8 id) 114 { 115 int err; 116 117 tile->xe = xe; 118 tile->id = id; 119 120 err = xe_tile_alloc(tile); 121 if (err) 122 return err; 123 124 tile->primary_gt = xe_gt_alloc(tile); 125 if (IS_ERR(tile->primary_gt)) 126 return PTR_ERR(tile->primary_gt); 127 128 xe_pcode_init(tile); 129 130 return 0; 131 } 132 133 static int tile_ttm_mgr_init(struct xe_tile *tile) 134 { 135 struct xe_device *xe = tile_to_xe(tile); 136 int err; 137 138 if (tile->mem.vram.usable_size) { 139 err = xe_ttm_vram_mgr_init(tile, tile->mem.vram_mgr); 140 if (err) 141 return err; 142 xe->info.mem_region_mask |= BIT(tile->id) << 1; 143 } 144 145 return 0; 146 } 147 148 /** 149 * xe_tile_init_noalloc - Init tile up to the point where allocations can happen. 150 * @tile: The tile to initialize. 151 * 152 * This function prepares the tile to allow memory allocations to VRAM, but is 153 * not allowed to allocate memory itself. This state is useful for display 154 * readout, because the inherited display framebuffer will otherwise be 155 * overwritten as it is usually put at the start of VRAM. 156 * 157 * Note that since this is tile initialization, it should not perform any 158 * GT-specific operations, and thus does not need to hold GT forcewake. 159 * 160 * Returns: 0 on success, negative error code on error. 161 */ 162 int xe_tile_init_noalloc(struct xe_tile *tile) 163 { 164 int err; 165 166 err = tile_ttm_mgr_init(tile); 167 if (err) 168 return err; 169 170 tile->mem.kernel_bb_pool = xe_sa_bo_manager_init(tile, SZ_1M, 16); 171 if (IS_ERR(tile->mem.kernel_bb_pool)) 172 return PTR_ERR(tile->mem.kernel_bb_pool); 173 174 xe_wa_apply_tile_workarounds(tile); 175 176 err = xe_tile_sysfs_init(tile); 177 178 return 0; 179 } 180 181 void xe_tile_migrate_wait(struct xe_tile *tile) 182 { 183 xe_migrate_wait(tile->migrate); 184 } 185