1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #include <drm/drm_managed.h> 7 8 #include "xe_device.h" 9 #include "xe_ggtt.h" 10 #include "xe_migrate.h" 11 #include "xe_sa.h" 12 #include "xe_tile.h" 13 #include "xe_tile_sysfs.h" 14 #include "xe_ttm_vram_mgr.h" 15 #include "xe_wa.h" 16 17 /** 18 * DOC: Multi-tile Design 19 * 20 * Different vendors use the term "tile" a bit differently, but in the Intel 21 * world, a 'tile' is pretty close to what most people would think of as being 22 * a complete GPU. When multiple GPUs are placed behind a single PCI device, 23 * that's what is referred to as a "multi-tile device." In such cases, pretty 24 * much all hardware is replicated per-tile, although certain responsibilities 25 * like PCI communication, reporting of interrupts to the OS, etc. are handled 26 * solely by the "root tile." A multi-tile platform takes care of tying the 27 * tiles together in a way such that interrupt notifications from remote tiles 28 * are forwarded to the root tile, the per-tile vram is combined into a single 29 * address space, etc. 30 * 31 * In contrast, a "GT" (which officially stands for "Graphics Technology") is 32 * the subset of a GPU/tile that is responsible for implementing graphics 33 * and/or media operations. The GT is where a lot of the driver implementation 34 * happens since it's where the hardware engines, the execution units, and the 35 * GuC all reside. 36 * 37 * Historically most Intel devices were single-tile devices that contained a 38 * single GT. PVC is an example of an Intel platform built on a multi-tile 39 * design (i.e., multiple GPUs behind a single PCI device); each PVC tile only 40 * has a single GT. In contrast, platforms like MTL that have separate chips 41 * for render and media IP are still only a single logical GPU, but the 42 * graphics and media IP blocks are each exposed as a separate GT within that 43 * single GPU. This is important from a software perspective because multi-GT 44 * platforms like MTL only replicate a subset of the GPU hardware and behave 45 * differently than multi-tile platforms like PVC where nearly everything is 46 * replicated. 47 * 48 * Per-tile functionality (shared by all GTs within the tile): 49 * - Complete 4MB MMIO space (containing SGunit/SoC registers, GT 50 * registers, display registers, etc.) 51 * - Global GTT 52 * - VRAM (if discrete) 53 * - Interrupt flows 54 * - Migration context 55 * - kernel batchbuffer pool 56 * - Primary GT 57 * - Media GT (if media version >= 13) 58 * 59 * Per-GT functionality: 60 * - GuC 61 * - Hardware engines 62 * - Programmable hardware units (subslices, EUs) 63 * - GSI subset of registers (multiple copies of these registers reside 64 * within the complete MMIO space provided by the tile, but at different 65 * offsets --- 0 for render, 0x380000 for media) 66 * - Multicast register steering 67 * - TLBs to cache page table translations 68 * - Reset capability 69 * - Low-level power management (e.g., C6) 70 * - Clock frequency 71 * - MOCS and PAT programming 72 */ 73 74 /** 75 * xe_tile_alloc - Perform per-tile memory allocation 76 * @tile: Tile to perform allocations for 77 * 78 * Allocates various per-tile data structures using DRM-managed allocations. 79 * Does not touch the hardware. 80 * 81 * Returns -ENOMEM if allocations fail, otherwise 0. 82 */ 83 int xe_tile_alloc(struct xe_tile *tile) 84 { 85 struct drm_device *drm = &tile_to_xe(tile)->drm; 86 87 tile->mem.ggtt = drmm_kzalloc(drm, sizeof(*tile->mem.ggtt), 88 GFP_KERNEL); 89 if (!tile->mem.ggtt) 90 return -ENOMEM; 91 tile->mem.ggtt->tile = tile; 92 93 tile->mem.vram_mgr = drmm_kzalloc(drm, sizeof(*tile->mem.vram_mgr), GFP_KERNEL); 94 if (!tile->mem.vram_mgr) 95 return -ENOMEM; 96 97 return 0; 98 } 99 100 static int tile_ttm_mgr_init(struct xe_tile *tile) 101 { 102 struct xe_device *xe = tile_to_xe(tile); 103 int err; 104 105 if (tile->mem.vram.usable_size) { 106 err = xe_ttm_vram_mgr_init(tile, tile->mem.vram_mgr); 107 if (err) 108 return err; 109 xe->info.mem_region_mask |= BIT(tile->id) << 1; 110 } 111 112 return 0; 113 } 114 115 /** 116 * xe_tile_init_noalloc - Init tile up to the point where allocations can happen. 117 * @tile: The tile to initialize. 118 * 119 * This function prepares the tile to allow memory allocations to VRAM, but is 120 * not allowed to allocate memory itself. This state is useful for display 121 * readout, because the inherited display framebuffer will otherwise be 122 * overwritten as it is usually put at the start of VRAM. 123 * 124 * Note that since this is tile initialization, it should not perform any 125 * GT-specific operations, and thus does not need to hold GT forcewake. 126 * 127 * Returns: 0 on success, negative error code on error. 128 */ 129 int xe_tile_init_noalloc(struct xe_tile *tile) 130 { 131 int err; 132 133 xe_device_mem_access_get(tile_to_xe(tile)); 134 135 err = tile_ttm_mgr_init(tile); 136 if (err) 137 goto err_mem_access; 138 139 err = xe_ggtt_init_noalloc(tile->mem.ggtt); 140 if (err) 141 goto err_mem_access; 142 143 tile->mem.kernel_bb_pool = xe_sa_bo_manager_init(tile, SZ_1M, 16); 144 if (IS_ERR(tile->mem.kernel_bb_pool)) 145 err = PTR_ERR(tile->mem.kernel_bb_pool); 146 147 xe_wa_apply_tile_workarounds(tile); 148 149 xe_tile_sysfs_init(tile); 150 151 err_mem_access: 152 xe_device_mem_access_put(tile_to_xe(tile)); 153 return err; 154 } 155 156 void xe_tile_migrate_wait(struct xe_tile *tile) 157 { 158 xe_migrate_wait(tile->migrate); 159 } 160