1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 #ifndef _XE_SA_H_ 6 #define _XE_SA_H_ 7 8 #include "xe_sa_types.h" 9 10 struct dma_fence; 11 struct xe_bo; 12 struct xe_gt; 13 14 int xe_sa_bo_manager_init(struct xe_gt *gt, 15 struct xe_sa_manager *sa_manager, 16 u32 size, u32 align); 17 18 struct drm_suballoc *xe_sa_bo_new(struct xe_sa_manager *sa_manager, 19 u32 size); 20 void xe_sa_bo_flush_write(struct drm_suballoc *sa_bo); 21 void xe_sa_bo_free(struct drm_suballoc *sa_bo, 22 struct dma_fence *fence); 23 24 static inline struct xe_sa_manager * 25 to_xe_sa_manager(struct drm_suballoc_manager *mng) 26 { 27 return container_of(mng, struct xe_sa_manager, base); 28 } 29 30 static inline u64 xe_sa_bo_gpu_addr(struct drm_suballoc *sa) 31 { 32 return to_xe_sa_manager(sa->manager)->gpu_addr + 33 drm_suballoc_soffset(sa); 34 } 35 36 static inline void *xe_sa_bo_cpu_addr(struct drm_suballoc *sa) 37 { 38 return to_xe_sa_manager(sa->manager)->cpu_ptr + 39 drm_suballoc_soffset(sa); 40 } 41 42 #endif 43