1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 #ifndef _XE_SA_H_ 6 #define _XE_SA_H_ 7 8 #include "xe_sa_types.h" 9 10 struct dma_fence; 11 struct xe_bo; 12 struct xe_tile; 13 14 struct xe_sa_manager *xe_sa_bo_manager_init(struct xe_tile *tile, u32 size, u32 align); 15 16 struct drm_suballoc *xe_sa_bo_new(struct xe_sa_manager *sa_manager, 17 u32 size); 18 void xe_sa_bo_flush_write(struct drm_suballoc *sa_bo); 19 void xe_sa_bo_free(struct drm_suballoc *sa_bo, 20 struct dma_fence *fence); 21 22 static inline struct xe_sa_manager * 23 to_xe_sa_manager(struct drm_suballoc_manager *mng) 24 { 25 return container_of(mng, struct xe_sa_manager, base); 26 } 27 28 static inline u64 xe_sa_bo_gpu_addr(struct drm_suballoc *sa) 29 { 30 return to_xe_sa_manager(sa->manager)->gpu_addr + 31 drm_suballoc_soffset(sa); 32 } 33 34 static inline void *xe_sa_bo_cpu_addr(struct drm_suballoc *sa) 35 { 36 return to_xe_sa_manager(sa->manager)->cpu_ptr + 37 drm_suballoc_soffset(sa); 38 } 39 40 #endif 41