1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_ring_ops.h" 7 8 #include <generated/xe_wa_oob.h> 9 10 #include "instructions/xe_gpu_commands.h" 11 #include "instructions/xe_mi_commands.h" 12 #include "regs/xe_engine_regs.h" 13 #include "regs/xe_gt_regs.h" 14 #include "regs/xe_lrc_layout.h" 15 #include "xe_exec_queue_types.h" 16 #include "xe_gt.h" 17 #include "xe_lrc.h" 18 #include "xe_macros.h" 19 #include "xe_sched_job.h" 20 #include "xe_sriov.h" 21 #include "xe_vm_types.h" 22 #include "xe_vm.h" 23 #include "xe_wa.h" 24 25 /* 26 * 3D-related flags that can't be set on _engines_ that lack access to the 3D 27 * pipeline (i.e., CCS engines). 28 */ 29 #define PIPE_CONTROL_3D_ENGINE_FLAGS (\ 30 PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | \ 31 PIPE_CONTROL_DEPTH_CACHE_FLUSH | \ 32 PIPE_CONTROL_TILE_CACHE_FLUSH | \ 33 PIPE_CONTROL_DEPTH_STALL | \ 34 PIPE_CONTROL_STALL_AT_SCOREBOARD | \ 35 PIPE_CONTROL_PSD_SYNC | \ 36 PIPE_CONTROL_AMFS_FLUSH | \ 37 PIPE_CONTROL_VF_CACHE_INVALIDATE | \ 38 PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET) 39 40 /* 3D-related flags that can't be set on _platforms_ that lack a 3D pipeline */ 41 #define PIPE_CONTROL_3D_ARCH_FLAGS ( \ 42 PIPE_CONTROL_3D_ENGINE_FLAGS | \ 43 PIPE_CONTROL_INDIRECT_STATE_DISABLE | \ 44 PIPE_CONTROL_FLUSH_ENABLE | \ 45 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \ 46 PIPE_CONTROL_DC_FLUSH_ENABLE) 47 48 static u32 preparser_disable(bool state) 49 { 50 return MI_ARB_CHECK | BIT(8) | state; 51 } 52 53 static int emit_aux_table_inv(struct xe_gt *gt, struct xe_reg reg, 54 u32 *dw, int i) 55 { 56 dw[i++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(1) | MI_LRI_MMIO_REMAP_EN; 57 dw[i++] = reg.addr + gt->mmio.adj_offset; 58 dw[i++] = AUX_INV; 59 dw[i++] = MI_NOOP; 60 61 return i; 62 } 63 64 static int emit_user_interrupt(u32 *dw, int i) 65 { 66 dw[i++] = MI_USER_INTERRUPT; 67 dw[i++] = MI_ARB_ON_OFF | MI_ARB_ENABLE; 68 dw[i++] = MI_ARB_CHECK; 69 70 return i; 71 } 72 73 static int emit_store_imm_ggtt(u32 addr, u32 value, u32 *dw, int i) 74 { 75 dw[i++] = MI_STORE_DATA_IMM | MI_SDI_GGTT | MI_SDI_NUM_DW(1); 76 dw[i++] = addr; 77 dw[i++] = 0; 78 dw[i++] = value; 79 80 return i; 81 } 82 83 static int emit_flush_dw(u32 *dw, int i) 84 { 85 dw[i++] = MI_FLUSH_DW | MI_FLUSH_IMM_DW; 86 dw[i++] = 0; 87 dw[i++] = 0; 88 dw[i++] = 0; 89 90 return i; 91 } 92 93 static int emit_flush_imm_ggtt(u32 addr, u32 value, bool invalidate_tlb, 94 u32 *dw, int i) 95 { 96 dw[i++] = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_IMM_DW | 97 (invalidate_tlb ? MI_INVALIDATE_TLB : 0); 98 dw[i++] = addr | MI_FLUSH_DW_USE_GTT; 99 dw[i++] = 0; 100 dw[i++] = value; 101 102 return i; 103 } 104 105 static int emit_bb_start(u64 batch_addr, u32 ppgtt_flag, u32 *dw, int i) 106 { 107 dw[i++] = MI_BATCH_BUFFER_START | ppgtt_flag | XE_INSTR_NUM_DW(3); 108 dw[i++] = lower_32_bits(batch_addr); 109 dw[i++] = upper_32_bits(batch_addr); 110 111 return i; 112 } 113 114 static int emit_flush_invalidate(u32 flag, u32 *dw, int i) 115 { 116 dw[i] = MI_FLUSH_DW; 117 dw[i] |= flag; 118 dw[i++] |= MI_INVALIDATE_TLB | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_IMM_DW | 119 MI_FLUSH_DW_STORE_INDEX; 120 121 dw[i++] = LRC_PPHWSP_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; 122 dw[i++] = 0; 123 dw[i++] = ~0U; 124 125 return i; 126 } 127 128 static int 129 emit_pipe_control(u32 *dw, int i, u32 bit_group_0, u32 bit_group_1, u32 offset, u32 value) 130 { 131 dw[i++] = GFX_OP_PIPE_CONTROL(6) | bit_group_0; 132 dw[i++] = bit_group_1; 133 dw[i++] = offset; 134 dw[i++] = 0; 135 dw[i++] = value; 136 dw[i++] = 0; 137 138 return i; 139 } 140 141 static int emit_pipe_invalidate(u32 mask_flags, bool invalidate_tlb, u32 *dw, 142 int i) 143 { 144 u32 flags = PIPE_CONTROL_CS_STALL | 145 PIPE_CONTROL_COMMAND_CACHE_INVALIDATE | 146 PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE | 147 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | 148 PIPE_CONTROL_VF_CACHE_INVALIDATE | 149 PIPE_CONTROL_CONST_CACHE_INVALIDATE | 150 PIPE_CONTROL_STATE_CACHE_INVALIDATE | 151 PIPE_CONTROL_QW_WRITE | 152 PIPE_CONTROL_STORE_DATA_INDEX; 153 154 if (invalidate_tlb) 155 flags |= PIPE_CONTROL_TLB_INVALIDATE; 156 157 flags &= ~mask_flags; 158 159 return emit_pipe_control(dw, i, 0, flags, LRC_PPHWSP_SCRATCH_ADDR, 0); 160 } 161 162 static int emit_store_imm_ppgtt_posted(u64 addr, u64 value, 163 u32 *dw, int i) 164 { 165 dw[i++] = MI_STORE_DATA_IMM | MI_SDI_NUM_QW(1); 166 dw[i++] = lower_32_bits(addr); 167 dw[i++] = upper_32_bits(addr); 168 dw[i++] = lower_32_bits(value); 169 dw[i++] = upper_32_bits(value); 170 171 return i; 172 } 173 174 static int emit_render_cache_flush(struct xe_sched_job *job, u32 *dw, int i) 175 { 176 struct xe_gt *gt = job->q->gt; 177 bool lacks_render = !(gt->info.engine_mask & XE_HW_ENGINE_RCS_MASK); 178 u32 flags; 179 180 flags = (PIPE_CONTROL_CS_STALL | 181 PIPE_CONTROL_TILE_CACHE_FLUSH | 182 PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | 183 PIPE_CONTROL_DEPTH_CACHE_FLUSH | 184 PIPE_CONTROL_DC_FLUSH_ENABLE | 185 PIPE_CONTROL_FLUSH_ENABLE); 186 187 if (XE_WA(gt, 1409600907)) 188 flags |= PIPE_CONTROL_DEPTH_STALL; 189 190 if (lacks_render) 191 flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS; 192 else if (job->q->class == XE_ENGINE_CLASS_COMPUTE) 193 flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS; 194 195 return emit_pipe_control(dw, i, PIPE_CONTROL0_HDC_PIPELINE_FLUSH, flags, 0, 0); 196 } 197 198 static int emit_pipe_control_to_ring_end(struct xe_hw_engine *hwe, u32 *dw, int i) 199 { 200 if (hwe->class != XE_ENGINE_CLASS_RENDER) 201 return i; 202 203 if (XE_WA(hwe->gt, 16020292621)) 204 i = emit_pipe_control(dw, i, 0, PIPE_CONTROL_LRI_POST_SYNC, 205 RING_NOPID(hwe->mmio_base).addr, 0); 206 207 return i; 208 } 209 210 static int emit_pipe_imm_ggtt(u32 addr, u32 value, bool stall_only, u32 *dw, 211 int i) 212 { 213 u32 flags = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_GLOBAL_GTT_IVB | 214 PIPE_CONTROL_QW_WRITE; 215 216 if (!stall_only) 217 flags |= PIPE_CONTROL_FLUSH_ENABLE; 218 219 return emit_pipe_control(dw, i, 0, flags, addr, value); 220 } 221 222 static u32 get_ppgtt_flag(struct xe_sched_job *job) 223 { 224 return job->q->vm ? BIT(8) : 0; 225 } 226 227 /* for engines that don't require any special HW handling (no EUs, no aux inval, etc) */ 228 static void __emit_job_gen12_simple(struct xe_sched_job *job, struct xe_lrc *lrc, 229 u64 batch_addr, u32 seqno) 230 { 231 u32 dw[MAX_JOB_SIZE_DW], i = 0; 232 u32 ppgtt_flag = get_ppgtt_flag(job); 233 struct xe_gt *gt = job->q->gt; 234 235 if (job->ring_ops_flush_tlb) { 236 dw[i++] = preparser_disable(true); 237 i = emit_flush_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc), 238 seqno, true, dw, i); 239 dw[i++] = preparser_disable(false); 240 } else { 241 i = emit_store_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc), 242 seqno, dw, i); 243 } 244 245 i = emit_bb_start(batch_addr, ppgtt_flag, dw, i); 246 247 if (job->user_fence.used) { 248 i = emit_flush_dw(dw, i); 249 i = emit_store_imm_ppgtt_posted(job->user_fence.addr, 250 job->user_fence.value, 251 dw, i); 252 } 253 254 i = emit_flush_imm_ggtt(xe_lrc_seqno_ggtt_addr(lrc), seqno, false, dw, i); 255 256 i = emit_user_interrupt(dw, i); 257 258 xe_gt_assert(gt, i <= MAX_JOB_SIZE_DW); 259 260 xe_lrc_write_ring(lrc, dw, i * sizeof(*dw)); 261 } 262 263 static bool has_aux_ccs(struct xe_device *xe) 264 { 265 /* 266 * PVC is a special case that has no compression of either type 267 * (FlatCCS or AuxCCS). Also, AuxCCS is no longer used from Xe2 268 * onward, so any future platforms with no FlatCCS will not have 269 * AuxCCS either. 270 */ 271 if (GRAPHICS_VER(xe) >= 20 || xe->info.platform == XE_PVC) 272 return false; 273 274 return !xe->info.has_flat_ccs; 275 } 276 277 static void __emit_job_gen12_video(struct xe_sched_job *job, struct xe_lrc *lrc, 278 u64 batch_addr, u32 seqno) 279 { 280 u32 dw[MAX_JOB_SIZE_DW], i = 0; 281 u32 ppgtt_flag = get_ppgtt_flag(job); 282 struct xe_gt *gt = job->q->gt; 283 struct xe_device *xe = gt_to_xe(gt); 284 bool decode = job->q->class == XE_ENGINE_CLASS_VIDEO_DECODE; 285 286 dw[i++] = preparser_disable(true); 287 288 /* hsdes: 1809175790 */ 289 if (has_aux_ccs(xe)) { 290 if (decode) 291 i = emit_aux_table_inv(gt, VD0_AUX_INV, dw, i); 292 else 293 i = emit_aux_table_inv(gt, VE0_AUX_INV, dw, i); 294 } 295 296 if (job->ring_ops_flush_tlb) 297 i = emit_flush_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc), 298 seqno, true, dw, i); 299 300 dw[i++] = preparser_disable(false); 301 302 if (!job->ring_ops_flush_tlb) 303 i = emit_store_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc), 304 seqno, dw, i); 305 306 i = emit_bb_start(batch_addr, ppgtt_flag, dw, i); 307 308 if (job->user_fence.used) { 309 i = emit_flush_dw(dw, i); 310 i = emit_store_imm_ppgtt_posted(job->user_fence.addr, 311 job->user_fence.value, 312 dw, i); 313 } 314 315 i = emit_flush_imm_ggtt(xe_lrc_seqno_ggtt_addr(lrc), seqno, false, dw, i); 316 317 i = emit_user_interrupt(dw, i); 318 319 xe_gt_assert(gt, i <= MAX_JOB_SIZE_DW); 320 321 xe_lrc_write_ring(lrc, dw, i * sizeof(*dw)); 322 } 323 324 static void __emit_job_gen12_render_compute(struct xe_sched_job *job, 325 struct xe_lrc *lrc, 326 u64 batch_addr, u32 seqno) 327 { 328 u32 dw[MAX_JOB_SIZE_DW], i = 0; 329 u32 ppgtt_flag = get_ppgtt_flag(job); 330 struct xe_gt *gt = job->q->gt; 331 struct xe_device *xe = gt_to_xe(gt); 332 bool lacks_render = !(gt->info.engine_mask & XE_HW_ENGINE_RCS_MASK); 333 u32 mask_flags = 0; 334 335 dw[i++] = preparser_disable(true); 336 if (lacks_render) 337 mask_flags = PIPE_CONTROL_3D_ARCH_FLAGS; 338 else if (job->q->class == XE_ENGINE_CLASS_COMPUTE) 339 mask_flags = PIPE_CONTROL_3D_ENGINE_FLAGS; 340 341 /* See __xe_pt_bind_vma() for a discussion on TLB invalidations. */ 342 i = emit_pipe_invalidate(mask_flags, job->ring_ops_flush_tlb, dw, i); 343 344 /* hsdes: 1809175790 */ 345 if (has_aux_ccs(xe)) 346 i = emit_aux_table_inv(gt, CCS_AUX_INV, dw, i); 347 348 dw[i++] = preparser_disable(false); 349 350 i = emit_store_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc), 351 seqno, dw, i); 352 353 i = emit_bb_start(batch_addr, ppgtt_flag, dw, i); 354 355 i = emit_render_cache_flush(job, dw, i); 356 357 if (job->user_fence.used) 358 i = emit_store_imm_ppgtt_posted(job->user_fence.addr, 359 job->user_fence.value, 360 dw, i); 361 362 i = emit_pipe_imm_ggtt(xe_lrc_seqno_ggtt_addr(lrc), seqno, lacks_render, dw, i); 363 364 i = emit_user_interrupt(dw, i); 365 366 i = emit_pipe_control_to_ring_end(job->q->hwe, dw, i); 367 368 xe_gt_assert(gt, i <= MAX_JOB_SIZE_DW); 369 370 xe_lrc_write_ring(lrc, dw, i * sizeof(*dw)); 371 } 372 373 static void emit_migration_job_gen12(struct xe_sched_job *job, 374 struct xe_lrc *lrc, u32 seqno) 375 { 376 u32 dw[MAX_JOB_SIZE_DW], i = 0; 377 378 i = emit_store_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc), 379 seqno, dw, i); 380 381 dw[i++] = MI_ARB_ON_OFF | MI_ARB_DISABLE; /* Enabled again below */ 382 383 i = emit_bb_start(job->ptrs[0].batch_addr, BIT(8), dw, i); 384 385 if (!IS_SRIOV_VF(gt_to_xe(job->q->gt))) { 386 /* XXX: Do we need this? Leaving for now. */ 387 dw[i++] = preparser_disable(true); 388 i = emit_flush_invalidate(0, dw, i); 389 dw[i++] = preparser_disable(false); 390 } 391 392 i = emit_bb_start(job->ptrs[1].batch_addr, BIT(8), dw, i); 393 394 dw[i++] = MI_FLUSH_DW | MI_INVALIDATE_TLB | job->migrate_flush_flags | 395 MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_IMM_DW; 396 dw[i++] = xe_lrc_seqno_ggtt_addr(lrc) | MI_FLUSH_DW_USE_GTT; 397 dw[i++] = 0; 398 dw[i++] = seqno; /* value */ 399 400 i = emit_user_interrupt(dw, i); 401 402 xe_gt_assert(job->q->gt, i <= MAX_JOB_SIZE_DW); 403 404 xe_lrc_write_ring(lrc, dw, i * sizeof(*dw)); 405 } 406 407 static void emit_job_gen12_gsc(struct xe_sched_job *job) 408 { 409 struct xe_gt *gt = job->q->gt; 410 411 xe_gt_assert(gt, job->q->width <= 1); /* no parallel submission for GSCCS */ 412 413 __emit_job_gen12_simple(job, job->q->lrc[0], 414 job->ptrs[0].batch_addr, 415 xe_sched_job_lrc_seqno(job)); 416 } 417 418 static void emit_job_gen12_copy(struct xe_sched_job *job) 419 { 420 int i; 421 422 if (xe_sched_job_is_migration(job->q)) { 423 emit_migration_job_gen12(job, job->q->lrc[0], 424 xe_sched_job_lrc_seqno(job)); 425 return; 426 } 427 428 for (i = 0; i < job->q->width; ++i) 429 __emit_job_gen12_simple(job, job->q->lrc[i], 430 job->ptrs[i].batch_addr, 431 xe_sched_job_lrc_seqno(job)); 432 } 433 434 static void emit_job_gen12_video(struct xe_sched_job *job) 435 { 436 int i; 437 438 /* FIXME: Not doing parallel handshake for now */ 439 for (i = 0; i < job->q->width; ++i) 440 __emit_job_gen12_video(job, job->q->lrc[i], 441 job->ptrs[i].batch_addr, 442 xe_sched_job_lrc_seqno(job)); 443 } 444 445 static void emit_job_gen12_render_compute(struct xe_sched_job *job) 446 { 447 int i; 448 449 for (i = 0; i < job->q->width; ++i) 450 __emit_job_gen12_render_compute(job, job->q->lrc[i], 451 job->ptrs[i].batch_addr, 452 xe_sched_job_lrc_seqno(job)); 453 } 454 455 static const struct xe_ring_ops ring_ops_gen12_gsc = { 456 .emit_job = emit_job_gen12_gsc, 457 }; 458 459 static const struct xe_ring_ops ring_ops_gen12_copy = { 460 .emit_job = emit_job_gen12_copy, 461 }; 462 463 static const struct xe_ring_ops ring_ops_gen12_video = { 464 .emit_job = emit_job_gen12_video, 465 }; 466 467 static const struct xe_ring_ops ring_ops_gen12_render_compute = { 468 .emit_job = emit_job_gen12_render_compute, 469 }; 470 471 const struct xe_ring_ops * 472 xe_ring_ops_get(struct xe_gt *gt, enum xe_engine_class class) 473 { 474 switch (class) { 475 case XE_ENGINE_CLASS_OTHER: 476 return &ring_ops_gen12_gsc; 477 case XE_ENGINE_CLASS_COPY: 478 return &ring_ops_gen12_copy; 479 case XE_ENGINE_CLASS_VIDEO_DECODE: 480 case XE_ENGINE_CLASS_VIDEO_ENHANCE: 481 return &ring_ops_gen12_video; 482 case XE_ENGINE_CLASS_RENDER: 483 case XE_ENGINE_CLASS_COMPUTE: 484 return &ring_ops_gen12_render_compute; 485 default: 486 return NULL; 487 } 488 } 489