1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #include "xe_reg_whitelist.h" 7 8 #include "regs/xe_engine_regs.h" 9 #include "regs/xe_gt_regs.h" 10 #include "regs/xe_oa_regs.h" 11 #include "xe_device.h" 12 #include "xe_gt_types.h" 13 #include "xe_gt_printk.h" 14 #include "xe_platform_types.h" 15 #include "xe_reg_sr.h" 16 #include "xe_rtp.h" 17 #include "xe_step.h" 18 19 #undef XE_REG_MCR 20 #define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1) 21 22 static bool match_not_render(const struct xe_device *xe, 23 const struct xe_gt *gt, 24 const struct xe_hw_engine *hwe) 25 { 26 return hwe->class != XE_ENGINE_CLASS_RENDER; 27 } 28 29 static bool match_has_mert(const struct xe_device *xe, 30 const struct xe_gt *gt, 31 const struct xe_hw_engine *hwe) 32 { 33 return xe_device_has_mert((struct xe_device *)xe); 34 } 35 36 static const struct xe_rtp_entry_sr register_whitelist[] = { 37 { XE_RTP_NAME("WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865"), 38 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 39 XE_RTP_ACTIONS(WHITELIST(PS_INVOCATION_COUNT, 40 RING_FORCE_TO_NONPRIV_ACCESS_RD | 41 RING_FORCE_TO_NONPRIV_RANGE_4)) 42 }, 43 { XE_RTP_NAME("1508744258, 14012131227, 1808121037"), 44 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 45 XE_RTP_ACTIONS(WHITELIST(COMMON_SLICE_CHICKEN1, 0)) 46 }, 47 { XE_RTP_NAME("1806527549"), 48 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 49 XE_RTP_ACTIONS(WHITELIST(HIZ_CHICKEN, 0)) 50 }, 51 { XE_RTP_NAME("allow_read_ctx_timestamp"), 52 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1260), FUNC(match_not_render)), 53 XE_RTP_ACTIONS(WHITELIST(RING_CTX_TIMESTAMP(0), 54 RING_FORCE_TO_NONPRIV_ACCESS_RD, 55 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 56 }, 57 { XE_RTP_NAME("16014440446"), 58 XE_RTP_RULES(PLATFORM(PVC)), 59 XE_RTP_ACTIONS(WHITELIST(XE_REG(0x4400), 60 RING_FORCE_TO_NONPRIV_DENY | 61 RING_FORCE_TO_NONPRIV_RANGE_64), 62 WHITELIST(XE_REG(0x4500), 63 RING_FORCE_TO_NONPRIV_DENY | 64 RING_FORCE_TO_NONPRIV_RANGE_64)) 65 }, 66 { XE_RTP_NAME("16017236439"), 67 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COPY)), 68 XE_RTP_ACTIONS(WHITELIST(BCS_SWCTRL(0), 69 RING_FORCE_TO_NONPRIV_DENY, 70 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 71 }, 72 { XE_RTP_NAME("16020183090"), 73 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 74 ENGINE_CLASS(RENDER)), 75 XE_RTP_ACTIONS(WHITELIST(CSBE_DEBUG_STATUS(RENDER_RING_BASE), 0)) 76 }, 77 { XE_RTP_NAME("14024997852"), 78 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005), ENGINE_CLASS(RENDER)), 79 XE_RTP_ACTIONS(WHITELIST(FF_MODE, 80 RING_FORCE_TO_NONPRIV_ACCESS_RW), 81 WHITELIST(VFLSKPD, 82 RING_FORCE_TO_NONPRIV_ACCESS_RW)) 83 }, 84 85 #define WHITELIST_OA_MMIO_TRG(trg, status, head) \ 86 WHITELIST(trg, RING_FORCE_TO_NONPRIV_ACCESS_RW), \ 87 WHITELIST(status, RING_FORCE_TO_NONPRIV_ACCESS_RD), \ 88 WHITELIST(head, RING_FORCE_TO_NONPRIV_ACCESS_RD | RING_FORCE_TO_NONPRIV_RANGE_4) 89 90 #define WHITELIST_OAG_MMIO_TRG \ 91 WHITELIST_OA_MMIO_TRG(OAG_MMIOTRIGGER, OAG_OASTATUS, OAG_OAHEADPTR) 92 93 #define WHITELIST_OAM_MMIO_TRG \ 94 WHITELIST_OA_MMIO_TRG(OAM_MMIO_TRG(XE_OAM_SAG_BASE_ADJ), \ 95 OAM_STATUS(XE_OAM_SAG_BASE_ADJ), \ 96 OAM_HEAD_POINTER(XE_OAM_SAG_BASE_ADJ)), \ 97 WHITELIST_OA_MMIO_TRG(OAM_MMIO_TRG(XE_OAM_SCMI_0_BASE_ADJ), \ 98 OAM_STATUS(XE_OAM_SCMI_0_BASE_ADJ), \ 99 OAM_HEAD_POINTER(XE_OAM_SCMI_0_BASE_ADJ)), \ 100 WHITELIST_OA_MMIO_TRG(OAM_MMIO_TRG(XE_OAM_SCMI_1_BASE_ADJ), \ 101 OAM_STATUS(XE_OAM_SCMI_1_BASE_ADJ), \ 102 OAM_HEAD_POINTER(XE_OAM_SCMI_1_BASE_ADJ)) 103 104 #define WHITELIST_OA_MERT_MMIO_TRG \ 105 WHITELIST_OA_MMIO_TRG(OAMERT_MMIO_TRG, OAMERT_STATUS, OAMERT_HEAD_POINTER) 106 107 { XE_RTP_NAME("oag_mmio_trg_rcs"), 108 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, XE_RTP_END_VERSION_UNDEFINED), 109 ENGINE_CLASS(RENDER)), 110 XE_RTP_ACTIONS(WHITELIST_OAG_MMIO_TRG) 111 }, 112 { XE_RTP_NAME("oag_mmio_trg_ccs"), 113 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, XE_RTP_END_VERSION_UNDEFINED), 114 ENGINE_CLASS(COMPUTE)), 115 XE_RTP_ACTIONS(WHITELIST_OAG_MMIO_TRG) 116 }, 117 { XE_RTP_NAME("oam_mmio_trg_vcs"), 118 XE_RTP_RULES(MEDIA_VERSION_RANGE(1300, XE_RTP_END_VERSION_UNDEFINED), 119 ENGINE_CLASS(VIDEO_DECODE)), 120 XE_RTP_ACTIONS(WHITELIST_OAM_MMIO_TRG) 121 }, 122 { XE_RTP_NAME("oam_mmio_trg_vecs"), 123 XE_RTP_RULES(MEDIA_VERSION_RANGE(1300, XE_RTP_END_VERSION_UNDEFINED), 124 ENGINE_CLASS(VIDEO_ENHANCE)), 125 XE_RTP_ACTIONS(WHITELIST_OAM_MMIO_TRG) 126 }, 127 { XE_RTP_NAME("oa_mert_mmio_trg_ccs"), 128 XE_RTP_RULES(FUNC(match_has_mert), ENGINE_CLASS(COMPUTE)), 129 XE_RTP_ACTIONS(WHITELIST_OA_MERT_MMIO_TRG) 130 }, 131 { XE_RTP_NAME("oa_mert_mmio_trg_bcs"), 132 XE_RTP_RULES(FUNC(match_has_mert), ENGINE_CLASS(COPY)), 133 XE_RTP_ACTIONS(WHITELIST_OA_MERT_MMIO_TRG) 134 }, 135 }; 136 137 static void whitelist_apply_to_hwe(struct xe_hw_engine *hwe) 138 { 139 struct xe_reg_sr *sr = &hwe->reg_whitelist; 140 struct xe_reg_sr_entry *entry; 141 struct drm_printer p; 142 unsigned long reg; 143 unsigned int slot; 144 145 xe_gt_dbg(hwe->gt, "Add %s whitelist to engine\n", sr->name); 146 p = xe_gt_dbg_printer(hwe->gt); 147 148 slot = 0; 149 xa_for_each(&sr->xa, reg, entry) { 150 struct xe_reg_sr_entry hwe_entry = { 151 .reg = RING_FORCE_TO_NONPRIV(hwe->mmio_base, slot), 152 .set_bits = entry->reg.addr | entry->set_bits, 153 .clr_bits = ~0u, 154 .read_mask = entry->read_mask, 155 }; 156 157 if (slot == RING_MAX_NONPRIV_SLOTS) { 158 xe_gt_err(hwe->gt, 159 "hwe %s: maximum register whitelist slots (%d) reached, refusing to add more\n", 160 hwe->name, RING_MAX_NONPRIV_SLOTS); 161 break; 162 } 163 164 xe_reg_whitelist_print_entry(&p, 0, reg, entry); 165 xe_reg_sr_add(&hwe->reg_sr, &hwe_entry, hwe->gt); 166 167 slot++; 168 } 169 } 170 171 /** 172 * xe_reg_whitelist_process_engine - process table of registers to whitelist 173 * @hwe: engine instance to process whitelist for 174 * 175 * Process wwhitelist table for this platform, saving in @hwe all the 176 * registers that need to be whitelisted by the hardware so they can be accessed 177 * by userspace. 178 */ 179 void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe) 180 { 181 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); 182 183 xe_rtp_process_to_sr(&ctx, register_whitelist, ARRAY_SIZE(register_whitelist), 184 &hwe->reg_whitelist); 185 whitelist_apply_to_hwe(hwe); 186 } 187 188 /** 189 * xe_reg_whitelist_print_entry - print one whitelist entry 190 * @p: DRM printer 191 * @indent: indent level 192 * @reg: register allowed/denied 193 * @entry: save-restore entry 194 * 195 * Print details about the entry added to allow/deny access 196 */ 197 void xe_reg_whitelist_print_entry(struct drm_printer *p, unsigned int indent, 198 u32 reg, struct xe_reg_sr_entry *entry) 199 { 200 u32 val = entry->set_bits; 201 const char *access_str = "(invalid)"; 202 unsigned int range_bit = 2; 203 u32 range_start, range_end; 204 bool deny; 205 206 deny = val & RING_FORCE_TO_NONPRIV_DENY; 207 208 switch (val & RING_FORCE_TO_NONPRIV_RANGE_MASK) { 209 case RING_FORCE_TO_NONPRIV_RANGE_4: 210 range_bit = 4; 211 break; 212 case RING_FORCE_TO_NONPRIV_RANGE_16: 213 range_bit = 6; 214 break; 215 case RING_FORCE_TO_NONPRIV_RANGE_64: 216 range_bit = 8; 217 break; 218 } 219 220 range_start = reg & REG_GENMASK(25, range_bit); 221 range_end = range_start | REG_GENMASK(range_bit, 0); 222 223 switch (val & RING_FORCE_TO_NONPRIV_ACCESS_MASK) { 224 case RING_FORCE_TO_NONPRIV_ACCESS_RW: 225 access_str = "rw"; 226 break; 227 case RING_FORCE_TO_NONPRIV_ACCESS_RD: 228 access_str = "read"; 229 break; 230 case RING_FORCE_TO_NONPRIV_ACCESS_WR: 231 access_str = "write"; 232 break; 233 } 234 235 drm_printf_indent(p, indent, "REG[0x%x-0x%x]: %s %s access\n", 236 range_start, range_end, 237 deny ? "deny" : "allow", 238 access_str); 239 } 240 241 /** 242 * xe_reg_whitelist_dump - print all whitelist entries 243 * @sr: Save/restore entries 244 * @p: DRM printer 245 */ 246 void xe_reg_whitelist_dump(struct xe_reg_sr *sr, struct drm_printer *p) 247 { 248 struct xe_reg_sr_entry *entry; 249 unsigned long reg; 250 251 if (!sr->name || xa_empty(&sr->xa)) 252 return; 253 254 drm_printf(p, "%s\n", sr->name); 255 xa_for_each(&sr->xa, reg, entry) 256 xe_reg_whitelist_print_entry(p, 1, reg, entry); 257 } 258