1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_reg_sr.h" 7 8 #include <kunit/visibility.h> 9 #include <linux/align.h> 10 #include <linux/string_helpers.h> 11 #include <linux/xarray.h> 12 13 #include <drm/drm_managed.h> 14 #include <drm/drm_print.h> 15 16 #include "xe_assert.h" 17 #include "xe_device.h" 18 #include "xe_device_types.h" 19 #include "xe_force_wake.h" 20 #include "xe_gt_mcr.h" 21 #include "xe_gt_printk.h" 22 #include "xe_gt_types.h" 23 #include "xe_hw_engine_types.h" 24 #include "xe_lrc.h" 25 #include "xe_mmio.h" 26 #include "xe_rtp_types.h" 27 28 static void reg_sr_fini(struct drm_device *drm, void *arg) 29 { 30 struct xe_reg_sr *sr = arg; 31 struct xe_reg_sr_entry *entry; 32 unsigned long reg; 33 34 xa_for_each(&sr->xa, reg, entry) 35 kfree(entry); 36 37 xa_destroy(&sr->xa); 38 } 39 40 int xe_reg_sr_init(struct xe_reg_sr *sr, const char *name, struct xe_device *xe) 41 { 42 xa_init(&sr->xa); 43 sr->name = name; 44 45 return drmm_add_action_or_reset(&xe->drm, reg_sr_fini, sr); 46 } 47 EXPORT_SYMBOL_IF_KUNIT(xe_reg_sr_init); 48 49 static bool compatible_entries(const struct xe_reg_sr_entry *e1, 50 const struct xe_reg_sr_entry *e2) 51 { 52 /* 53 * Don't allow overwriting values: clr_bits/set_bits should be disjoint 54 * when operating in the same register 55 */ 56 if (e1->clr_bits & e2->clr_bits || e1->set_bits & e2->set_bits || 57 e1->clr_bits & e2->set_bits || e1->set_bits & e2->clr_bits) 58 return false; 59 60 if (e1->reg.raw != e2->reg.raw) 61 return false; 62 63 return true; 64 } 65 66 static void reg_sr_inc_error(struct xe_reg_sr *sr) 67 { 68 #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST) 69 sr->errors++; 70 #endif 71 } 72 73 int xe_reg_sr_add(struct xe_reg_sr *sr, 74 const struct xe_reg_sr_entry *e, 75 struct xe_gt *gt) 76 { 77 unsigned long idx = e->reg.addr; 78 struct xe_reg_sr_entry *pentry = xa_load(&sr->xa, idx); 79 int ret; 80 81 if (pentry) { 82 if (!compatible_entries(pentry, e)) { 83 ret = -EINVAL; 84 goto fail; 85 } 86 87 pentry->clr_bits |= e->clr_bits; 88 pentry->set_bits |= e->set_bits; 89 pentry->read_mask |= e->read_mask; 90 91 return 0; 92 } 93 94 pentry = kmalloc_obj(*pentry); 95 if (!pentry) { 96 ret = -ENOMEM; 97 goto fail; 98 } 99 100 *pentry = *e; 101 ret = xa_err(xa_store(&sr->xa, idx, pentry, GFP_KERNEL)); 102 if (ret) 103 goto fail_free; 104 105 return 0; 106 107 fail_free: 108 kfree(pentry); 109 fail: 110 xe_gt_err(gt, 111 "discarding save-restore reg %04lx (clear: %08x, set: %08x, masked: %s, mcr: %s): ret=%d\n", 112 idx, e->clr_bits, e->set_bits, 113 str_yes_no(e->reg.masked), 114 str_yes_no(e->reg.mcr), 115 ret); 116 reg_sr_inc_error(sr); 117 118 return ret; 119 } 120 121 /* 122 * Convert back from encoded value to type-safe, only to be used when reg.mcr 123 * is true 124 */ 125 static struct xe_reg_mcr to_xe_reg_mcr(const struct xe_reg reg) 126 { 127 return (const struct xe_reg_mcr){.__reg.raw = reg.raw }; 128 } 129 130 static void apply_one_mmio(struct xe_gt *gt, struct xe_reg_sr_entry *entry) 131 { 132 struct xe_reg reg = entry->reg; 133 struct xe_reg_mcr reg_mcr = to_xe_reg_mcr(reg); 134 u32 val; 135 136 /* 137 * If this is a masked register, need to set the upper 16 bits. 138 * Set them to clr_bits since that is always a superset of the bits 139 * being modified. 140 * 141 * When it's not masked, we have to read it from hardware, unless we are 142 * supposed to set all bits. 143 */ 144 if (reg.masked) 145 val = entry->clr_bits << 16; 146 else if (entry->clr_bits + 1) 147 val = (reg.mcr ? 148 xe_gt_mcr_unicast_read_any(gt, reg_mcr) : 149 xe_mmio_read32(>->mmio, reg)) & (~entry->clr_bits); 150 else 151 val = 0; 152 153 /* 154 * TODO: add selftest to validate all tables, regardless of platform: 155 * - Masked registers can't have set_bits with upper bits set 156 * - set_bits must be contained in clr_bits 157 */ 158 val |= entry->set_bits; 159 160 xe_gt_dbg(gt, "REG[0x%x] = 0x%08x", reg.addr, val); 161 162 if (entry->reg.mcr) 163 xe_gt_mcr_multicast_write(gt, reg_mcr, val); 164 else 165 xe_mmio_write32(>->mmio, reg, val); 166 } 167 168 void xe_reg_sr_apply_mmio(struct xe_reg_sr *sr, struct xe_gt *gt) 169 { 170 struct xe_reg_sr_entry *entry; 171 unsigned long reg; 172 173 if (xa_empty(&sr->xa)) 174 return; 175 176 /* 177 * We don't process non-LRC reg_sr lists in VF, so they should have 178 * been empty in the check above. 179 */ 180 xe_gt_assert(gt, !IS_SRIOV_VF(gt_to_xe(gt))); 181 182 xe_gt_dbg(gt, "Applying %s save-restore MMIOs\n", sr->name); 183 184 CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FORCEWAKE_ALL); 185 if (!xe_force_wake_ref_has_domain(fw_ref.domains, XE_FORCEWAKE_ALL)) { 186 xe_gt_err(gt, "Failed to apply, err=-ETIMEDOUT\n"); 187 return; 188 } 189 190 xa_for_each(&sr->xa, reg, entry) 191 apply_one_mmio(gt, entry); 192 } 193 194 /** 195 * xe_reg_sr_dump - print all save/restore entries 196 * @sr: Save/restore entries 197 * @p: DRM printer 198 */ 199 void xe_reg_sr_dump(struct xe_reg_sr *sr, struct drm_printer *p) 200 { 201 struct xe_reg_sr_entry *entry; 202 unsigned long reg; 203 204 if (!sr->name || xa_empty(&sr->xa)) 205 return; 206 207 drm_printf(p, "%s\n", sr->name); 208 xa_for_each(&sr->xa, reg, entry) 209 drm_printf(p, "\tREG[0x%lx] clr=0x%08x set=0x%08x masked=%s mcr=%s\n", 210 reg, entry->clr_bits, entry->set_bits, 211 str_yes_no(entry->reg.masked), 212 str_yes_no(entry->reg.mcr)); 213 } 214 215 static u32 readback_reg(struct xe_gt *gt, struct xe_reg reg) 216 { 217 struct xe_reg_mcr mcr_reg = to_xe_reg_mcr(reg); 218 219 if (reg.mcr) 220 return xe_gt_mcr_unicast_read_any(gt, mcr_reg); 221 else 222 return xe_mmio_read32(>->mmio, reg); 223 } 224 225 /** 226 * xe_reg_sr_readback_check() - Readback registers referenced in save/restore 227 * entries and check whether the programming is in place. 228 * @sr: Save/restore entries 229 * @gt: GT to read register from 230 * @p: DRM printer to report discrepancies on 231 */ 232 void xe_reg_sr_readback_check(struct xe_reg_sr *sr, 233 struct xe_gt *gt, 234 struct drm_printer *p) 235 { 236 struct xe_reg_sr_entry *entry; 237 unsigned long offset; 238 239 xa_for_each(&sr->xa, offset, entry) { 240 u32 val = readback_reg(gt, entry->reg); 241 u32 mask = entry->clr_bits | entry->set_bits; 242 243 if ((val & mask) != entry->set_bits) 244 drm_printf(p, "%#8lx & %#10x :: expected %#10x got %#10x\n", 245 offset, mask, entry->set_bits, val & mask); 246 } 247 } 248 249 /** 250 * xe_reg_sr_lrc_check() - Check LRC for registers referenced in save/restore 251 * entries and check whether the programming is in place. 252 * @sr: Save/restore entries 253 * @gt: GT to read register from 254 * @hwe: Hardware engine type to check LRC for 255 * @p: DRM printer to report discrepancies on 256 */ 257 void xe_reg_sr_lrc_check(struct xe_reg_sr *sr, 258 struct xe_gt *gt, 259 struct xe_hw_engine *hwe, 260 struct drm_printer *p) 261 { 262 struct xe_reg_sr_entry *entry; 263 unsigned long offset; 264 265 xa_for_each(&sr->xa, offset, entry) { 266 u32 val; 267 int ret = xe_lrc_lookup_default_reg_value(gt, hwe->class, offset, &val); 268 u32 mask = entry->clr_bits | entry->set_bits; 269 270 if (ret == -ENOENT) 271 drm_printf(p, "%#8lx :: not found in LRC for %s\n", offset, hwe->name); 272 else if ((val & mask) != entry->set_bits) 273 drm_printf(p, "%#8lx & %#10x :: expected %#10x got %#10x\n", 274 offset, mask, entry->set_bits, val & mask); 275 } 276 } 277