1*d34b42ffSRaag Jadav // SPDX-License-Identifier: MIT 2*d34b42ffSRaag Jadav /* 3*d34b42ffSRaag Jadav * Copyright © 2026 Intel Corporation 4*d34b42ffSRaag Jadav */ 5*d34b42ffSRaag Jadav 6*d34b42ffSRaag Jadav #include "xe_device.h" 7*d34b42ffSRaag Jadav #include "xe_printk.h" 8*d34b42ffSRaag Jadav #include "xe_ras.h" 9*d34b42ffSRaag Jadav #include "xe_ras_types.h" 10*d34b42ffSRaag Jadav #include "xe_sysctrl.h" 11*d34b42ffSRaag Jadav #include "xe_sysctrl_event_types.h" 12*d34b42ffSRaag Jadav 13*d34b42ffSRaag Jadav /* Severity of detected errors */ 14*d34b42ffSRaag Jadav enum xe_ras_severity { 15*d34b42ffSRaag Jadav XE_RAS_SEV_NOT_SUPPORTED = 0, 16*d34b42ffSRaag Jadav XE_RAS_SEV_CORRECTABLE, 17*d34b42ffSRaag Jadav XE_RAS_SEV_UNCORRECTABLE, 18*d34b42ffSRaag Jadav XE_RAS_SEV_INFORMATIONAL, 19*d34b42ffSRaag Jadav XE_RAS_SEV_MAX 20*d34b42ffSRaag Jadav }; 21*d34b42ffSRaag Jadav 22*d34b42ffSRaag Jadav /* Major IP blocks/components where errors can originate */ 23*d34b42ffSRaag Jadav enum xe_ras_component { 24*d34b42ffSRaag Jadav XE_RAS_COMP_NOT_SUPPORTED = 0, 25*d34b42ffSRaag Jadav XE_RAS_COMP_DEVICE_MEMORY, 26*d34b42ffSRaag Jadav XE_RAS_COMP_CORE_COMPUTE, 27*d34b42ffSRaag Jadav XE_RAS_COMP_RESERVED, 28*d34b42ffSRaag Jadav XE_RAS_COMP_PCIE, 29*d34b42ffSRaag Jadav XE_RAS_COMP_FABRIC, 30*d34b42ffSRaag Jadav XE_RAS_COMP_SOC_INTERNAL, 31*d34b42ffSRaag Jadav XE_RAS_COMP_MAX 32*d34b42ffSRaag Jadav }; 33*d34b42ffSRaag Jadav 34*d34b42ffSRaag Jadav static const char *const xe_ras_severities[] = { 35*d34b42ffSRaag Jadav [XE_RAS_SEV_NOT_SUPPORTED] = "Not Supported", 36*d34b42ffSRaag Jadav [XE_RAS_SEV_CORRECTABLE] = "Correctable Error", 37*d34b42ffSRaag Jadav [XE_RAS_SEV_UNCORRECTABLE] = "Uncorrectable Error", 38*d34b42ffSRaag Jadav [XE_RAS_SEV_INFORMATIONAL] = "Informational Error", 39*d34b42ffSRaag Jadav }; 40*d34b42ffSRaag Jadav static_assert(ARRAY_SIZE(xe_ras_severities) == XE_RAS_SEV_MAX); 41*d34b42ffSRaag Jadav 42*d34b42ffSRaag Jadav static const char *const xe_ras_components[] = { 43*d34b42ffSRaag Jadav [XE_RAS_COMP_NOT_SUPPORTED] = "Not Supported", 44*d34b42ffSRaag Jadav [XE_RAS_COMP_DEVICE_MEMORY] = "Device Memory", 45*d34b42ffSRaag Jadav [XE_RAS_COMP_CORE_COMPUTE] = "Core Compute", 46*d34b42ffSRaag Jadav [XE_RAS_COMP_RESERVED] = "Reserved", 47*d34b42ffSRaag Jadav [XE_RAS_COMP_PCIE] = "PCIe", 48*d34b42ffSRaag Jadav [XE_RAS_COMP_FABRIC] = "Fabric", 49*d34b42ffSRaag Jadav [XE_RAS_COMP_SOC_INTERNAL] = "SoC Internal", 50*d34b42ffSRaag Jadav }; 51*d34b42ffSRaag Jadav static_assert(ARRAY_SIZE(xe_ras_components) == XE_RAS_COMP_MAX); 52*d34b42ffSRaag Jadav 53*d34b42ffSRaag Jadav static inline const char *sev_to_str(u8 severity) 54*d34b42ffSRaag Jadav { 55*d34b42ffSRaag Jadav if (severity >= XE_RAS_SEV_MAX) 56*d34b42ffSRaag Jadav severity = XE_RAS_SEV_NOT_SUPPORTED; 57*d34b42ffSRaag Jadav 58*d34b42ffSRaag Jadav return xe_ras_severities[severity]; 59*d34b42ffSRaag Jadav } 60*d34b42ffSRaag Jadav 61*d34b42ffSRaag Jadav static inline const char *comp_to_str(u8 component) 62*d34b42ffSRaag Jadav { 63*d34b42ffSRaag Jadav if (component >= XE_RAS_COMP_MAX) 64*d34b42ffSRaag Jadav component = XE_RAS_COMP_NOT_SUPPORTED; 65*d34b42ffSRaag Jadav 66*d34b42ffSRaag Jadav return xe_ras_components[component]; 67*d34b42ffSRaag Jadav } 68*d34b42ffSRaag Jadav 69*d34b42ffSRaag Jadav void xe_ras_counter_threshold_crossed(struct xe_device *xe, 70*d34b42ffSRaag Jadav struct xe_sysctrl_event_response *response) 71*d34b42ffSRaag Jadav { 72*d34b42ffSRaag Jadav struct xe_ras_threshold_crossed *pending = (void *)&response->data; 73*d34b42ffSRaag Jadav struct xe_ras_error_class *errors = pending->counters; 74*d34b42ffSRaag Jadav u32 id, ncounters = pending->ncounters; 75*d34b42ffSRaag Jadav 76*d34b42ffSRaag Jadav BUILD_BUG_ON(sizeof(response->data) < sizeof(*pending)); 77*d34b42ffSRaag Jadav xe_device_assert_mem_access(xe); 78*d34b42ffSRaag Jadav 79*d34b42ffSRaag Jadav if (!ncounters || ncounters > XE_RAS_NUM_COUNTERS) 80*d34b42ffSRaag Jadav xe_err(xe, "sysctrl: unexpected counter threshold crossed %u\n", ncounters); 81*d34b42ffSRaag Jadav else 82*d34b42ffSRaag Jadav xe_warn(xe, "[RAS]: counter threshold crossed, %u new errors\n", ncounters); 83*d34b42ffSRaag Jadav 84*d34b42ffSRaag Jadav for (id = 0; id < ncounters && id < XE_RAS_NUM_COUNTERS; id++) { 85*d34b42ffSRaag Jadav u8 severity, component; 86*d34b42ffSRaag Jadav 87*d34b42ffSRaag Jadav severity = errors[id].common.severity; 88*d34b42ffSRaag Jadav component = errors[id].common.component; 89*d34b42ffSRaag Jadav 90*d34b42ffSRaag Jadav xe_warn(xe, "[RAS]: %s %s detected\n", 91*d34b42ffSRaag Jadav comp_to_str(component), sev_to_str(severity)); 92*d34b42ffSRaag Jadav } 93*d34b42ffSRaag Jadav } 94