1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_query.h" 7 8 #include <linux/nospec.h> 9 #include <linux/sched/clock.h> 10 11 #include <drm/ttm/ttm_placement.h> 12 #include <generated/xe_wa_oob.h> 13 #include <uapi/drm/xe_drm.h> 14 15 #include "regs/xe_engine_regs.h" 16 #include "regs/xe_gt_regs.h" 17 #include "xe_bo.h" 18 #include "xe_device.h" 19 #include "xe_exec_queue.h" 20 #include "xe_force_wake.h" 21 #include "xe_ggtt.h" 22 #include "xe_gt.h" 23 #include "xe_guc_hwconfig.h" 24 #include "xe_macros.h" 25 #include "xe_mmio.h" 26 #include "xe_oa.h" 27 #include "xe_ttm_vram_mgr.h" 28 #include "xe_wa.h" 29 30 static const u16 xe_to_user_engine_class[] = { 31 [XE_ENGINE_CLASS_RENDER] = DRM_XE_ENGINE_CLASS_RENDER, 32 [XE_ENGINE_CLASS_COPY] = DRM_XE_ENGINE_CLASS_COPY, 33 [XE_ENGINE_CLASS_VIDEO_DECODE] = DRM_XE_ENGINE_CLASS_VIDEO_DECODE, 34 [XE_ENGINE_CLASS_VIDEO_ENHANCE] = DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE, 35 [XE_ENGINE_CLASS_COMPUTE] = DRM_XE_ENGINE_CLASS_COMPUTE, 36 }; 37 38 static const enum xe_engine_class user_to_xe_engine_class[] = { 39 [DRM_XE_ENGINE_CLASS_RENDER] = XE_ENGINE_CLASS_RENDER, 40 [DRM_XE_ENGINE_CLASS_COPY] = XE_ENGINE_CLASS_COPY, 41 [DRM_XE_ENGINE_CLASS_VIDEO_DECODE] = XE_ENGINE_CLASS_VIDEO_DECODE, 42 [DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE] = XE_ENGINE_CLASS_VIDEO_ENHANCE, 43 [DRM_XE_ENGINE_CLASS_COMPUTE] = XE_ENGINE_CLASS_COMPUTE, 44 }; 45 46 static size_t calc_hw_engine_info_size(struct xe_device *xe) 47 { 48 struct xe_hw_engine *hwe; 49 enum xe_hw_engine_id id; 50 struct xe_gt *gt; 51 u8 gt_id; 52 int i = 0; 53 54 for_each_gt(gt, xe, gt_id) 55 for_each_hw_engine(hwe, gt, id) { 56 if (xe_hw_engine_is_reserved(hwe)) 57 continue; 58 i++; 59 } 60 61 return sizeof(struct drm_xe_query_engines) + 62 i * sizeof(struct drm_xe_engine); 63 } 64 65 typedef u64 (*__ktime_func_t)(void); 66 static __ktime_func_t __clock_id_to_func(clockid_t clk_id) 67 { 68 /* 69 * Use logic same as the perf subsystem to allow user to select the 70 * reference clock id to be used for timestamps. 71 */ 72 switch (clk_id) { 73 case CLOCK_MONOTONIC: 74 return &ktime_get_ns; 75 case CLOCK_MONOTONIC_RAW: 76 return &ktime_get_raw_ns; 77 case CLOCK_REALTIME: 78 return &ktime_get_real_ns; 79 case CLOCK_BOOTTIME: 80 return &ktime_get_boottime_ns; 81 case CLOCK_TAI: 82 return &ktime_get_clocktai_ns; 83 default: 84 return NULL; 85 } 86 } 87 88 static void 89 hwe_read_timestamp(struct xe_hw_engine *hwe, u64 *engine_ts, u64 *cpu_ts, 90 u64 *cpu_delta, __ktime_func_t cpu_clock) 91 { 92 struct xe_mmio *mmio = &hwe->gt->mmio; 93 u32 upper, lower, old_upper, loop = 0; 94 struct xe_reg upper_reg = RING_TIMESTAMP_UDW(hwe->mmio_base), 95 lower_reg = RING_TIMESTAMP(hwe->mmio_base); 96 97 upper = xe_mmio_read32(mmio, upper_reg); 98 do { 99 *cpu_delta = local_clock(); 100 *cpu_ts = cpu_clock(); 101 lower = xe_mmio_read32(mmio, lower_reg); 102 *cpu_delta = local_clock() - *cpu_delta; 103 old_upper = upper; 104 upper = xe_mmio_read32(mmio, upper_reg); 105 } while (upper != old_upper && loop++ < 2); 106 107 *engine_ts = (u64)upper << 32 | lower; 108 } 109 110 static int 111 query_engine_cycles(struct xe_device *xe, 112 struct drm_xe_device_query *query) 113 { 114 struct drm_xe_query_engine_cycles __user *query_ptr; 115 struct drm_xe_engine_class_instance *eci; 116 struct drm_xe_query_engine_cycles resp; 117 size_t size = sizeof(resp); 118 __ktime_func_t cpu_clock; 119 struct xe_hw_engine *hwe; 120 struct xe_gt *gt; 121 unsigned int fw_ref; 122 123 if (query->size == 0) { 124 query->size = size; 125 return 0; 126 } else if (XE_IOCTL_DBG(xe, query->size != size)) { 127 return -EINVAL; 128 } 129 130 query_ptr = u64_to_user_ptr(query->data); 131 if (copy_from_user(&resp, query_ptr, size)) 132 return -EFAULT; 133 134 cpu_clock = __clock_id_to_func(resp.clockid); 135 if (!cpu_clock) 136 return -EINVAL; 137 138 eci = &resp.eci; 139 if (eci->gt_id >= XE_MAX_GT_PER_TILE) 140 return -EINVAL; 141 142 gt = xe_device_get_gt(xe, eci->gt_id); 143 if (!gt) 144 return -EINVAL; 145 146 if (eci->engine_class >= ARRAY_SIZE(user_to_xe_engine_class)) 147 return -EINVAL; 148 149 hwe = xe_gt_hw_engine(gt, user_to_xe_engine_class[eci->engine_class], 150 eci->engine_instance, true); 151 if (!hwe) 152 return -EINVAL; 153 154 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); 155 if (!xe_force_wake_ref_has_domain(fw_ref, XE_FORCEWAKE_ALL)) { 156 xe_force_wake_put(gt_to_fw(gt), fw_ref); 157 return -EIO; 158 } 159 160 hwe_read_timestamp(hwe, &resp.engine_cycles, &resp.cpu_timestamp, 161 &resp.cpu_delta, cpu_clock); 162 163 xe_force_wake_put(gt_to_fw(gt), fw_ref); 164 165 if (GRAPHICS_VER(xe) >= 20) 166 resp.width = 64; 167 else 168 resp.width = 36; 169 170 /* Only write to the output fields of user query */ 171 if (put_user(resp.cpu_timestamp, &query_ptr->cpu_timestamp) || 172 put_user(resp.cpu_delta, &query_ptr->cpu_delta) || 173 put_user(resp.engine_cycles, &query_ptr->engine_cycles) || 174 put_user(resp.width, &query_ptr->width)) 175 return -EFAULT; 176 177 return 0; 178 } 179 180 static int query_engines(struct xe_device *xe, 181 struct drm_xe_device_query *query) 182 { 183 size_t size = calc_hw_engine_info_size(xe); 184 struct drm_xe_query_engines __user *query_ptr = 185 u64_to_user_ptr(query->data); 186 struct drm_xe_query_engines *engines; 187 struct xe_hw_engine *hwe; 188 enum xe_hw_engine_id id; 189 struct xe_gt *gt; 190 u8 gt_id; 191 int i = 0; 192 193 if (query->size == 0) { 194 query->size = size; 195 return 0; 196 } else if (XE_IOCTL_DBG(xe, query->size != size)) { 197 return -EINVAL; 198 } 199 200 engines = kzalloc(size, GFP_KERNEL); 201 if (!engines) 202 return -ENOMEM; 203 204 for_each_gt(gt, xe, gt_id) 205 for_each_hw_engine(hwe, gt, id) { 206 if (xe_hw_engine_is_reserved(hwe)) 207 continue; 208 209 engines->engines[i].instance.engine_class = 210 xe_to_user_engine_class[hwe->class]; 211 engines->engines[i].instance.engine_instance = 212 hwe->logical_instance; 213 engines->engines[i].instance.gt_id = gt->info.id; 214 215 i++; 216 } 217 218 engines->num_engines = i; 219 220 if (copy_to_user(query_ptr, engines, size)) { 221 kfree(engines); 222 return -EFAULT; 223 } 224 kfree(engines); 225 226 return 0; 227 } 228 229 static size_t calc_mem_regions_size(struct xe_device *xe) 230 { 231 u32 num_managers = 1; 232 int i; 233 234 for (i = XE_PL_VRAM0; i <= XE_PL_VRAM1; ++i) 235 if (ttm_manager_type(&xe->ttm, i)) 236 num_managers++; 237 238 return offsetof(struct drm_xe_query_mem_regions, mem_regions[num_managers]); 239 } 240 241 static int query_mem_regions(struct xe_device *xe, 242 struct drm_xe_device_query *query) 243 { 244 size_t size = calc_mem_regions_size(xe); 245 struct drm_xe_query_mem_regions *mem_regions; 246 struct drm_xe_query_mem_regions __user *query_ptr = 247 u64_to_user_ptr(query->data); 248 struct ttm_resource_manager *man; 249 int ret, i; 250 251 if (query->size == 0) { 252 query->size = size; 253 return 0; 254 } else if (XE_IOCTL_DBG(xe, query->size != size)) { 255 return -EINVAL; 256 } 257 258 mem_regions = kzalloc(size, GFP_KERNEL); 259 if (XE_IOCTL_DBG(xe, !mem_regions)) 260 return -ENOMEM; 261 262 man = ttm_manager_type(&xe->ttm, XE_PL_TT); 263 mem_regions->mem_regions[0].mem_class = DRM_XE_MEM_REGION_CLASS_SYSMEM; 264 /* 265 * The instance needs to be a unique number that represents the index 266 * in the placement mask used at xe_gem_create_ioctl() for the 267 * xe_bo_create() placement. 268 */ 269 mem_regions->mem_regions[0].instance = 0; 270 mem_regions->mem_regions[0].min_page_size = PAGE_SIZE; 271 mem_regions->mem_regions[0].total_size = man->size << PAGE_SHIFT; 272 if (perfmon_capable()) 273 mem_regions->mem_regions[0].used = ttm_resource_manager_usage(man); 274 mem_regions->num_mem_regions = 1; 275 276 for (i = XE_PL_VRAM0; i <= XE_PL_VRAM1; ++i) { 277 man = ttm_manager_type(&xe->ttm, i); 278 if (man) { 279 mem_regions->mem_regions[mem_regions->num_mem_regions].mem_class = 280 DRM_XE_MEM_REGION_CLASS_VRAM; 281 mem_regions->mem_regions[mem_regions->num_mem_regions].instance = 282 mem_regions->num_mem_regions; 283 mem_regions->mem_regions[mem_regions->num_mem_regions].min_page_size = 284 xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K ? 285 SZ_64K : PAGE_SIZE; 286 mem_regions->mem_regions[mem_regions->num_mem_regions].total_size = 287 man->size; 288 289 if (perfmon_capable()) { 290 xe_ttm_vram_get_used(man, 291 &mem_regions->mem_regions 292 [mem_regions->num_mem_regions].used, 293 &mem_regions->mem_regions 294 [mem_regions->num_mem_regions].cpu_visible_used); 295 } 296 297 mem_regions->mem_regions[mem_regions->num_mem_regions].cpu_visible_size = 298 xe_ttm_vram_get_cpu_visible_size(man); 299 mem_regions->num_mem_regions++; 300 } 301 } 302 303 if (!copy_to_user(query_ptr, mem_regions, size)) 304 ret = 0; 305 else 306 ret = -ENOSPC; 307 308 kfree(mem_regions); 309 return ret; 310 } 311 312 static int query_config(struct xe_device *xe, struct drm_xe_device_query *query) 313 { 314 const u32 num_params = DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY + 1; 315 size_t size = 316 sizeof(struct drm_xe_query_config) + num_params * sizeof(u64); 317 struct drm_xe_query_config __user *query_ptr = 318 u64_to_user_ptr(query->data); 319 struct drm_xe_query_config *config; 320 321 if (query->size == 0) { 322 query->size = size; 323 return 0; 324 } else if (XE_IOCTL_DBG(xe, query->size != size)) { 325 return -EINVAL; 326 } 327 328 config = kzalloc(size, GFP_KERNEL); 329 if (!config) 330 return -ENOMEM; 331 332 config->num_params = num_params; 333 config->info[DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID] = 334 xe->info.devid | (xe->info.revid << 16); 335 if (xe_device_get_root_tile(xe)->mem.vram.usable_size) 336 config->info[DRM_XE_QUERY_CONFIG_FLAGS] = 337 DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM; 338 config->info[DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT] = 339 xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K ? SZ_64K : SZ_4K; 340 config->info[DRM_XE_QUERY_CONFIG_VA_BITS] = xe->info.va_bits; 341 config->info[DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY] = 342 xe_exec_queue_device_get_max_priority(xe); 343 344 if (copy_to_user(query_ptr, config, size)) { 345 kfree(config); 346 return -EFAULT; 347 } 348 kfree(config); 349 350 return 0; 351 } 352 353 static int query_gt_list(struct xe_device *xe, struct drm_xe_device_query *query) 354 { 355 struct xe_gt *gt; 356 size_t size = sizeof(struct drm_xe_query_gt_list) + 357 xe->info.gt_count * sizeof(struct drm_xe_gt); 358 struct drm_xe_query_gt_list __user *query_ptr = 359 u64_to_user_ptr(query->data); 360 struct drm_xe_query_gt_list *gt_list; 361 u8 id; 362 363 if (query->size == 0) { 364 query->size = size; 365 return 0; 366 } else if (XE_IOCTL_DBG(xe, query->size != size)) { 367 return -EINVAL; 368 } 369 370 gt_list = kzalloc(size, GFP_KERNEL); 371 if (!gt_list) 372 return -ENOMEM; 373 374 gt_list->num_gt = xe->info.gt_count; 375 376 for_each_gt(gt, xe, id) { 377 if (xe_gt_is_media_type(gt)) 378 gt_list->gt_list[id].type = DRM_XE_QUERY_GT_TYPE_MEDIA; 379 else 380 gt_list->gt_list[id].type = DRM_XE_QUERY_GT_TYPE_MAIN; 381 gt_list->gt_list[id].tile_id = gt_to_tile(gt)->id; 382 gt_list->gt_list[id].gt_id = gt->info.id; 383 gt_list->gt_list[id].reference_clock = gt->info.reference_clock; 384 /* 385 * The mem_regions indexes in the mask below need to 386 * directly identify the struct 387 * drm_xe_query_mem_regions' instance constructed at 388 * query_mem_regions() 389 * 390 * For our current platforms: 391 * Bit 0 -> System Memory 392 * Bit 1 -> VRAM0 on Tile0 393 * Bit 2 -> VRAM1 on Tile1 394 * However the uAPI is generic and it's userspace's 395 * responsibility to check the mem_class, without any 396 * assumption. 397 */ 398 if (!IS_DGFX(xe)) 399 gt_list->gt_list[id].near_mem_regions = 0x1; 400 else 401 gt_list->gt_list[id].near_mem_regions = 402 BIT(gt_to_tile(gt)->id) << 1; 403 gt_list->gt_list[id].far_mem_regions = xe->info.mem_region_mask ^ 404 gt_list->gt_list[id].near_mem_regions; 405 406 gt_list->gt_list[id].ip_ver_major = 407 REG_FIELD_GET(GMD_ID_ARCH_MASK, gt->info.gmdid); 408 gt_list->gt_list[id].ip_ver_minor = 409 REG_FIELD_GET(GMD_ID_RELEASE_MASK, gt->info.gmdid); 410 gt_list->gt_list[id].ip_ver_rev = 411 REG_FIELD_GET(GMD_ID_REVID, gt->info.gmdid); 412 } 413 414 if (copy_to_user(query_ptr, gt_list, size)) { 415 kfree(gt_list); 416 return -EFAULT; 417 } 418 kfree(gt_list); 419 420 return 0; 421 } 422 423 static int query_hwconfig(struct xe_device *xe, 424 struct drm_xe_device_query *query) 425 { 426 struct xe_gt *gt = xe_root_mmio_gt(xe); 427 size_t size = xe_guc_hwconfig_size(>->uc.guc); 428 void __user *query_ptr = u64_to_user_ptr(query->data); 429 void *hwconfig; 430 431 if (query->size == 0) { 432 query->size = size; 433 return 0; 434 } else if (XE_IOCTL_DBG(xe, query->size != size)) { 435 return -EINVAL; 436 } 437 438 hwconfig = kzalloc(size, GFP_KERNEL); 439 if (!hwconfig) 440 return -ENOMEM; 441 442 xe_guc_hwconfig_copy(>->uc.guc, hwconfig); 443 444 if (copy_to_user(query_ptr, hwconfig, size)) { 445 kfree(hwconfig); 446 return -EFAULT; 447 } 448 kfree(hwconfig); 449 450 return 0; 451 } 452 453 static size_t calc_topo_query_size(struct xe_device *xe) 454 { 455 struct xe_gt *gt; 456 size_t query_size = 0; 457 int id; 458 459 for_each_gt(gt, xe, id) { 460 query_size += 3 * sizeof(struct drm_xe_query_topology_mask) + 461 sizeof_field(struct xe_gt, fuse_topo.g_dss_mask) + 462 sizeof_field(struct xe_gt, fuse_topo.c_dss_mask) + 463 sizeof_field(struct xe_gt, fuse_topo.eu_mask_per_dss); 464 465 /* L3bank mask may not be available for some GTs */ 466 if (!XE_WA(gt, no_media_l3)) 467 query_size += sizeof(struct drm_xe_query_topology_mask) + 468 sizeof_field(struct xe_gt, fuse_topo.l3_bank_mask); 469 } 470 471 return query_size; 472 } 473 474 static int copy_mask(void __user **ptr, 475 struct drm_xe_query_topology_mask *topo, 476 void *mask, size_t mask_size) 477 { 478 topo->num_bytes = mask_size; 479 480 if (copy_to_user(*ptr, topo, sizeof(*topo))) 481 return -EFAULT; 482 *ptr += sizeof(topo); 483 484 if (copy_to_user(*ptr, mask, mask_size)) 485 return -EFAULT; 486 *ptr += mask_size; 487 488 return 0; 489 } 490 491 static int query_gt_topology(struct xe_device *xe, 492 struct drm_xe_device_query *query) 493 { 494 void __user *query_ptr = u64_to_user_ptr(query->data); 495 size_t size = calc_topo_query_size(xe); 496 struct drm_xe_query_topology_mask topo; 497 struct xe_gt *gt; 498 int id; 499 500 if (query->size == 0) { 501 query->size = size; 502 return 0; 503 } else if (XE_IOCTL_DBG(xe, query->size != size)) { 504 return -EINVAL; 505 } 506 507 for_each_gt(gt, xe, id) { 508 int err; 509 510 topo.gt_id = id; 511 512 topo.type = DRM_XE_TOPO_DSS_GEOMETRY; 513 err = copy_mask(&query_ptr, &topo, gt->fuse_topo.g_dss_mask, 514 sizeof(gt->fuse_topo.g_dss_mask)); 515 if (err) 516 return err; 517 518 topo.type = DRM_XE_TOPO_DSS_COMPUTE; 519 err = copy_mask(&query_ptr, &topo, gt->fuse_topo.c_dss_mask, 520 sizeof(gt->fuse_topo.c_dss_mask)); 521 if (err) 522 return err; 523 524 /* 525 * If the kernel doesn't have a way to obtain a correct L3bank 526 * mask, then it's better to omit L3 from the query rather than 527 * reporting bogus or zeroed information to userspace. 528 */ 529 if (!XE_WA(gt, no_media_l3)) { 530 topo.type = DRM_XE_TOPO_L3_BANK; 531 err = copy_mask(&query_ptr, &topo, gt->fuse_topo.l3_bank_mask, 532 sizeof(gt->fuse_topo.l3_bank_mask)); 533 if (err) 534 return err; 535 } 536 537 topo.type = gt->fuse_topo.eu_type == XE_GT_EU_TYPE_SIMD16 ? 538 DRM_XE_TOPO_SIMD16_EU_PER_DSS : 539 DRM_XE_TOPO_EU_PER_DSS; 540 err = copy_mask(&query_ptr, &topo, 541 gt->fuse_topo.eu_mask_per_dss, 542 sizeof(gt->fuse_topo.eu_mask_per_dss)); 543 if (err) 544 return err; 545 } 546 547 return 0; 548 } 549 550 static int 551 query_uc_fw_version(struct xe_device *xe, struct drm_xe_device_query *query) 552 { 553 struct drm_xe_query_uc_fw_version __user *query_ptr = u64_to_user_ptr(query->data); 554 size_t size = sizeof(struct drm_xe_query_uc_fw_version); 555 struct drm_xe_query_uc_fw_version resp; 556 struct xe_uc_fw_version *version = NULL; 557 558 if (query->size == 0) { 559 query->size = size; 560 return 0; 561 } else if (XE_IOCTL_DBG(xe, query->size != size)) { 562 return -EINVAL; 563 } 564 565 if (copy_from_user(&resp, query_ptr, size)) 566 return -EFAULT; 567 568 if (XE_IOCTL_DBG(xe, resp.pad || resp.pad2 || resp.reserved)) 569 return -EINVAL; 570 571 switch (resp.uc_type) { 572 case XE_QUERY_UC_TYPE_GUC_SUBMISSION: { 573 struct xe_guc *guc = &xe->tiles[0].primary_gt->uc.guc; 574 575 version = &guc->fw.versions.found[XE_UC_FW_VER_COMPATIBILITY]; 576 break; 577 } 578 case XE_QUERY_UC_TYPE_HUC: { 579 struct xe_gt *media_gt = NULL; 580 struct xe_huc *huc; 581 582 if (MEDIA_VER(xe) >= 13) { 583 struct xe_tile *tile; 584 u8 gt_id; 585 586 for_each_tile(tile, xe, gt_id) { 587 if (tile->media_gt) { 588 media_gt = tile->media_gt; 589 break; 590 } 591 } 592 } else { 593 media_gt = xe->tiles[0].primary_gt; 594 } 595 596 if (!media_gt) 597 break; 598 599 huc = &media_gt->uc.huc; 600 if (huc->fw.status == XE_UC_FIRMWARE_RUNNING) 601 version = &huc->fw.versions.found[XE_UC_FW_VER_RELEASE]; 602 break; 603 } 604 default: 605 return -EINVAL; 606 } 607 608 if (version) { 609 resp.branch_ver = 0; 610 resp.major_ver = version->major; 611 resp.minor_ver = version->minor; 612 resp.patch_ver = version->patch; 613 } else { 614 return -ENODEV; 615 } 616 617 if (copy_to_user(query_ptr, &resp, size)) 618 return -EFAULT; 619 620 return 0; 621 } 622 623 static size_t calc_oa_unit_query_size(struct xe_device *xe) 624 { 625 size_t size = sizeof(struct drm_xe_query_oa_units); 626 struct xe_gt *gt; 627 int i, id; 628 629 for_each_gt(gt, xe, id) { 630 for (i = 0; i < gt->oa.num_oa_units; i++) { 631 size += sizeof(struct drm_xe_oa_unit); 632 size += gt->oa.oa_unit[i].num_engines * 633 sizeof(struct drm_xe_engine_class_instance); 634 } 635 } 636 637 return size; 638 } 639 640 static int query_oa_units(struct xe_device *xe, 641 struct drm_xe_device_query *query) 642 { 643 void __user *query_ptr = u64_to_user_ptr(query->data); 644 size_t size = calc_oa_unit_query_size(xe); 645 struct drm_xe_query_oa_units *qoa; 646 enum xe_hw_engine_id hwe_id; 647 struct drm_xe_oa_unit *du; 648 struct xe_hw_engine *hwe; 649 struct xe_oa_unit *u; 650 int gt_id, i, j, ret; 651 struct xe_gt *gt; 652 u8 *pdu; 653 654 if (query->size == 0) { 655 query->size = size; 656 return 0; 657 } else if (XE_IOCTL_DBG(xe, query->size != size)) { 658 return -EINVAL; 659 } 660 661 qoa = kzalloc(size, GFP_KERNEL); 662 if (!qoa) 663 return -ENOMEM; 664 665 pdu = (u8 *)&qoa->oa_units[0]; 666 for_each_gt(gt, xe, gt_id) { 667 for (i = 0; i < gt->oa.num_oa_units; i++) { 668 u = >->oa.oa_unit[i]; 669 du = (struct drm_xe_oa_unit *)pdu; 670 671 du->oa_unit_id = u->oa_unit_id; 672 du->oa_unit_type = u->type; 673 du->oa_timestamp_freq = xe_oa_timestamp_frequency(gt); 674 du->capabilities = DRM_XE_OA_CAPS_BASE | DRM_XE_OA_CAPS_SYNCS | 675 DRM_XE_OA_CAPS_OA_BUFFER_SIZE | 676 DRM_XE_OA_CAPS_WAIT_NUM_REPORTS; 677 678 j = 0; 679 for_each_hw_engine(hwe, gt, hwe_id) { 680 if (!xe_hw_engine_is_reserved(hwe) && 681 xe_oa_unit_id(hwe) == u->oa_unit_id) { 682 du->eci[j].engine_class = 683 xe_to_user_engine_class[hwe->class]; 684 du->eci[j].engine_instance = hwe->logical_instance; 685 du->eci[j].gt_id = gt->info.id; 686 j++; 687 } 688 } 689 du->num_engines = j; 690 pdu += sizeof(*du) + j * sizeof(du->eci[0]); 691 qoa->num_oa_units++; 692 } 693 } 694 695 ret = copy_to_user(query_ptr, qoa, size); 696 kfree(qoa); 697 698 return ret ? -EFAULT : 0; 699 } 700 701 static int (* const xe_query_funcs[])(struct xe_device *xe, 702 struct drm_xe_device_query *query) = { 703 query_engines, 704 query_mem_regions, 705 query_config, 706 query_gt_list, 707 query_hwconfig, 708 query_gt_topology, 709 query_engine_cycles, 710 query_uc_fw_version, 711 query_oa_units, 712 }; 713 714 int xe_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file) 715 { 716 struct xe_device *xe = to_xe_device(dev); 717 struct drm_xe_device_query *query = data; 718 u32 idx; 719 720 if (XE_IOCTL_DBG(xe, query->extensions) || 721 XE_IOCTL_DBG(xe, query->reserved[0] || query->reserved[1])) 722 return -EINVAL; 723 724 if (XE_IOCTL_DBG(xe, query->query >= ARRAY_SIZE(xe_query_funcs))) 725 return -EINVAL; 726 727 idx = array_index_nospec(query->query, ARRAY_SIZE(xe_query_funcs)); 728 if (XE_IOCTL_DBG(xe, !xe_query_funcs[idx])) 729 return -EINVAL; 730 731 return xe_query_funcs[idx](xe, query); 732 } 733