1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_query.h" 7 8 #include <linux/nospec.h> 9 #include <linux/sched/clock.h> 10 11 #include <drm/ttm/ttm_placement.h> 12 #include <generated/xe_wa_oob.h> 13 #include <uapi/drm/xe_drm.h> 14 15 #include "regs/xe_engine_regs.h" 16 #include "regs/xe_gt_regs.h" 17 #include "xe_bo.h" 18 #include "xe_device.h" 19 #include "xe_exec_queue.h" 20 #include "xe_force_wake.h" 21 #include "xe_ggtt.h" 22 #include "xe_gt.h" 23 #include "xe_guc_hwconfig.h" 24 #include "xe_macros.h" 25 #include "xe_mmio.h" 26 #include "xe_ttm_vram_mgr.h" 27 #include "xe_wa.h" 28 29 static const u16 xe_to_user_engine_class[] = { 30 [XE_ENGINE_CLASS_RENDER] = DRM_XE_ENGINE_CLASS_RENDER, 31 [XE_ENGINE_CLASS_COPY] = DRM_XE_ENGINE_CLASS_COPY, 32 [XE_ENGINE_CLASS_VIDEO_DECODE] = DRM_XE_ENGINE_CLASS_VIDEO_DECODE, 33 [XE_ENGINE_CLASS_VIDEO_ENHANCE] = DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE, 34 [XE_ENGINE_CLASS_COMPUTE] = DRM_XE_ENGINE_CLASS_COMPUTE, 35 }; 36 37 static const enum xe_engine_class user_to_xe_engine_class[] = { 38 [DRM_XE_ENGINE_CLASS_RENDER] = XE_ENGINE_CLASS_RENDER, 39 [DRM_XE_ENGINE_CLASS_COPY] = XE_ENGINE_CLASS_COPY, 40 [DRM_XE_ENGINE_CLASS_VIDEO_DECODE] = XE_ENGINE_CLASS_VIDEO_DECODE, 41 [DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE] = XE_ENGINE_CLASS_VIDEO_ENHANCE, 42 [DRM_XE_ENGINE_CLASS_COMPUTE] = XE_ENGINE_CLASS_COMPUTE, 43 }; 44 45 static size_t calc_hw_engine_info_size(struct xe_device *xe) 46 { 47 struct xe_hw_engine *hwe; 48 enum xe_hw_engine_id id; 49 struct xe_gt *gt; 50 u8 gt_id; 51 int i = 0; 52 53 for_each_gt(gt, xe, gt_id) 54 for_each_hw_engine(hwe, gt, id) { 55 if (xe_hw_engine_is_reserved(hwe)) 56 continue; 57 i++; 58 } 59 60 return sizeof(struct drm_xe_query_engines) + 61 i * sizeof(struct drm_xe_engine); 62 } 63 64 typedef u64 (*__ktime_func_t)(void); 65 static __ktime_func_t __clock_id_to_func(clockid_t clk_id) 66 { 67 /* 68 * Use logic same as the perf subsystem to allow user to select the 69 * reference clock id to be used for timestamps. 70 */ 71 switch (clk_id) { 72 case CLOCK_MONOTONIC: 73 return &ktime_get_ns; 74 case CLOCK_MONOTONIC_RAW: 75 return &ktime_get_raw_ns; 76 case CLOCK_REALTIME: 77 return &ktime_get_real_ns; 78 case CLOCK_BOOTTIME: 79 return &ktime_get_boottime_ns; 80 case CLOCK_TAI: 81 return &ktime_get_clocktai_ns; 82 default: 83 return NULL; 84 } 85 } 86 87 static void 88 hwe_read_timestamp(struct xe_hw_engine *hwe, u64 *engine_ts, u64 *cpu_ts, 89 u64 *cpu_delta, __ktime_func_t cpu_clock) 90 { 91 struct xe_mmio *mmio = &hwe->gt->mmio; 92 u32 upper, lower, old_upper, loop = 0; 93 struct xe_reg upper_reg = RING_TIMESTAMP_UDW(hwe->mmio_base), 94 lower_reg = RING_TIMESTAMP(hwe->mmio_base); 95 96 upper = xe_mmio_read32(mmio, upper_reg); 97 do { 98 *cpu_delta = local_clock(); 99 *cpu_ts = cpu_clock(); 100 lower = xe_mmio_read32(mmio, lower_reg); 101 *cpu_delta = local_clock() - *cpu_delta; 102 old_upper = upper; 103 upper = xe_mmio_read32(mmio, upper_reg); 104 } while (upper != old_upper && loop++ < 2); 105 106 *engine_ts = (u64)upper << 32 | lower; 107 } 108 109 static int 110 query_engine_cycles(struct xe_device *xe, 111 struct drm_xe_device_query *query) 112 { 113 struct drm_xe_query_engine_cycles __user *query_ptr; 114 struct drm_xe_engine_class_instance *eci; 115 struct drm_xe_query_engine_cycles resp; 116 size_t size = sizeof(resp); 117 __ktime_func_t cpu_clock; 118 struct xe_hw_engine *hwe; 119 struct xe_gt *gt; 120 121 if (query->size == 0) { 122 query->size = size; 123 return 0; 124 } else if (XE_IOCTL_DBG(xe, query->size != size)) { 125 return -EINVAL; 126 } 127 128 query_ptr = u64_to_user_ptr(query->data); 129 if (copy_from_user(&resp, query_ptr, size)) 130 return -EFAULT; 131 132 cpu_clock = __clock_id_to_func(resp.clockid); 133 if (!cpu_clock) 134 return -EINVAL; 135 136 eci = &resp.eci; 137 if (eci->gt_id >= XE_MAX_GT_PER_TILE) 138 return -EINVAL; 139 140 gt = xe_device_get_gt(xe, eci->gt_id); 141 if (!gt) 142 return -EINVAL; 143 144 if (eci->engine_class >= ARRAY_SIZE(user_to_xe_engine_class)) 145 return -EINVAL; 146 147 hwe = xe_gt_hw_engine(gt, user_to_xe_engine_class[eci->engine_class], 148 eci->engine_instance, true); 149 if (!hwe) 150 return -EINVAL; 151 152 if (xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL)) 153 return -EIO; 154 155 hwe_read_timestamp(hwe, &resp.engine_cycles, &resp.cpu_timestamp, 156 &resp.cpu_delta, cpu_clock); 157 158 xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL); 159 160 if (GRAPHICS_VER(xe) >= 20) 161 resp.width = 64; 162 else 163 resp.width = 36; 164 165 /* Only write to the output fields of user query */ 166 if (put_user(resp.cpu_timestamp, &query_ptr->cpu_timestamp) || 167 put_user(resp.cpu_delta, &query_ptr->cpu_delta) || 168 put_user(resp.engine_cycles, &query_ptr->engine_cycles) || 169 put_user(resp.width, &query_ptr->width)) 170 return -EFAULT; 171 172 return 0; 173 } 174 175 static int query_engines(struct xe_device *xe, 176 struct drm_xe_device_query *query) 177 { 178 size_t size = calc_hw_engine_info_size(xe); 179 struct drm_xe_query_engines __user *query_ptr = 180 u64_to_user_ptr(query->data); 181 struct drm_xe_query_engines *engines; 182 struct xe_hw_engine *hwe; 183 enum xe_hw_engine_id id; 184 struct xe_gt *gt; 185 u8 gt_id; 186 int i = 0; 187 188 if (query->size == 0) { 189 query->size = size; 190 return 0; 191 } else if (XE_IOCTL_DBG(xe, query->size != size)) { 192 return -EINVAL; 193 } 194 195 engines = kzalloc(size, GFP_KERNEL); 196 if (!engines) 197 return -ENOMEM; 198 199 for_each_gt(gt, xe, gt_id) 200 for_each_hw_engine(hwe, gt, id) { 201 if (xe_hw_engine_is_reserved(hwe)) 202 continue; 203 204 engines->engines[i].instance.engine_class = 205 xe_to_user_engine_class[hwe->class]; 206 engines->engines[i].instance.engine_instance = 207 hwe->logical_instance; 208 engines->engines[i].instance.gt_id = gt->info.id; 209 210 i++; 211 } 212 213 engines->num_engines = i; 214 215 if (copy_to_user(query_ptr, engines, size)) { 216 kfree(engines); 217 return -EFAULT; 218 } 219 kfree(engines); 220 221 return 0; 222 } 223 224 static size_t calc_mem_regions_size(struct xe_device *xe) 225 { 226 u32 num_managers = 1; 227 int i; 228 229 for (i = XE_PL_VRAM0; i <= XE_PL_VRAM1; ++i) 230 if (ttm_manager_type(&xe->ttm, i)) 231 num_managers++; 232 233 return offsetof(struct drm_xe_query_mem_regions, mem_regions[num_managers]); 234 } 235 236 static int query_mem_regions(struct xe_device *xe, 237 struct drm_xe_device_query *query) 238 { 239 size_t size = calc_mem_regions_size(xe); 240 struct drm_xe_query_mem_regions *mem_regions; 241 struct drm_xe_query_mem_regions __user *query_ptr = 242 u64_to_user_ptr(query->data); 243 struct ttm_resource_manager *man; 244 int ret, i; 245 246 if (query->size == 0) { 247 query->size = size; 248 return 0; 249 } else if (XE_IOCTL_DBG(xe, query->size != size)) { 250 return -EINVAL; 251 } 252 253 mem_regions = kzalloc(size, GFP_KERNEL); 254 if (XE_IOCTL_DBG(xe, !mem_regions)) 255 return -ENOMEM; 256 257 man = ttm_manager_type(&xe->ttm, XE_PL_TT); 258 mem_regions->mem_regions[0].mem_class = DRM_XE_MEM_REGION_CLASS_SYSMEM; 259 /* 260 * The instance needs to be a unique number that represents the index 261 * in the placement mask used at xe_gem_create_ioctl() for the 262 * xe_bo_create() placement. 263 */ 264 mem_regions->mem_regions[0].instance = 0; 265 mem_regions->mem_regions[0].min_page_size = PAGE_SIZE; 266 mem_regions->mem_regions[0].total_size = man->size << PAGE_SHIFT; 267 if (perfmon_capable()) 268 mem_regions->mem_regions[0].used = ttm_resource_manager_usage(man); 269 mem_regions->num_mem_regions = 1; 270 271 for (i = XE_PL_VRAM0; i <= XE_PL_VRAM1; ++i) { 272 man = ttm_manager_type(&xe->ttm, i); 273 if (man) { 274 mem_regions->mem_regions[mem_regions->num_mem_regions].mem_class = 275 DRM_XE_MEM_REGION_CLASS_VRAM; 276 mem_regions->mem_regions[mem_regions->num_mem_regions].instance = 277 mem_regions->num_mem_regions; 278 mem_regions->mem_regions[mem_regions->num_mem_regions].min_page_size = 279 xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K ? 280 SZ_64K : PAGE_SIZE; 281 mem_regions->mem_regions[mem_regions->num_mem_regions].total_size = 282 man->size; 283 284 if (perfmon_capable()) { 285 xe_ttm_vram_get_used(man, 286 &mem_regions->mem_regions 287 [mem_regions->num_mem_regions].used, 288 &mem_regions->mem_regions 289 [mem_regions->num_mem_regions].cpu_visible_used); 290 } 291 292 mem_regions->mem_regions[mem_regions->num_mem_regions].cpu_visible_size = 293 xe_ttm_vram_get_cpu_visible_size(man); 294 mem_regions->num_mem_regions++; 295 } 296 } 297 298 if (!copy_to_user(query_ptr, mem_regions, size)) 299 ret = 0; 300 else 301 ret = -ENOSPC; 302 303 kfree(mem_regions); 304 return ret; 305 } 306 307 static int query_config(struct xe_device *xe, struct drm_xe_device_query *query) 308 { 309 const u32 num_params = DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY + 1; 310 size_t size = 311 sizeof(struct drm_xe_query_config) + num_params * sizeof(u64); 312 struct drm_xe_query_config __user *query_ptr = 313 u64_to_user_ptr(query->data); 314 struct drm_xe_query_config *config; 315 316 if (query->size == 0) { 317 query->size = size; 318 return 0; 319 } else if (XE_IOCTL_DBG(xe, query->size != size)) { 320 return -EINVAL; 321 } 322 323 config = kzalloc(size, GFP_KERNEL); 324 if (!config) 325 return -ENOMEM; 326 327 config->num_params = num_params; 328 config->info[DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID] = 329 xe->info.devid | (xe->info.revid << 16); 330 if (xe_device_get_root_tile(xe)->mem.vram.usable_size) 331 config->info[DRM_XE_QUERY_CONFIG_FLAGS] = 332 DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM; 333 config->info[DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT] = 334 xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K ? SZ_64K : SZ_4K; 335 config->info[DRM_XE_QUERY_CONFIG_VA_BITS] = xe->info.va_bits; 336 config->info[DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY] = 337 xe_exec_queue_device_get_max_priority(xe); 338 339 if (copy_to_user(query_ptr, config, size)) { 340 kfree(config); 341 return -EFAULT; 342 } 343 kfree(config); 344 345 return 0; 346 } 347 348 static int query_gt_list(struct xe_device *xe, struct drm_xe_device_query *query) 349 { 350 struct xe_gt *gt; 351 size_t size = sizeof(struct drm_xe_query_gt_list) + 352 xe->info.gt_count * sizeof(struct drm_xe_gt); 353 struct drm_xe_query_gt_list __user *query_ptr = 354 u64_to_user_ptr(query->data); 355 struct drm_xe_query_gt_list *gt_list; 356 u8 id; 357 358 if (query->size == 0) { 359 query->size = size; 360 return 0; 361 } else if (XE_IOCTL_DBG(xe, query->size != size)) { 362 return -EINVAL; 363 } 364 365 gt_list = kzalloc(size, GFP_KERNEL); 366 if (!gt_list) 367 return -ENOMEM; 368 369 gt_list->num_gt = xe->info.gt_count; 370 371 for_each_gt(gt, xe, id) { 372 if (xe_gt_is_media_type(gt)) 373 gt_list->gt_list[id].type = DRM_XE_QUERY_GT_TYPE_MEDIA; 374 else 375 gt_list->gt_list[id].type = DRM_XE_QUERY_GT_TYPE_MAIN; 376 gt_list->gt_list[id].tile_id = gt_to_tile(gt)->id; 377 gt_list->gt_list[id].gt_id = gt->info.id; 378 gt_list->gt_list[id].reference_clock = gt->info.reference_clock; 379 /* 380 * The mem_regions indexes in the mask below need to 381 * directly identify the struct 382 * drm_xe_query_mem_regions' instance constructed at 383 * query_mem_regions() 384 * 385 * For our current platforms: 386 * Bit 0 -> System Memory 387 * Bit 1 -> VRAM0 on Tile0 388 * Bit 2 -> VRAM1 on Tile1 389 * However the uAPI is generic and it's userspace's 390 * responsibility to check the mem_class, without any 391 * assumption. 392 */ 393 if (!IS_DGFX(xe)) 394 gt_list->gt_list[id].near_mem_regions = 0x1; 395 else 396 gt_list->gt_list[id].near_mem_regions = 397 BIT(gt_to_tile(gt)->id) << 1; 398 gt_list->gt_list[id].far_mem_regions = xe->info.mem_region_mask ^ 399 gt_list->gt_list[id].near_mem_regions; 400 401 gt_list->gt_list[id].ip_ver_major = 402 REG_FIELD_GET(GMD_ID_ARCH_MASK, gt->info.gmdid); 403 gt_list->gt_list[id].ip_ver_minor = 404 REG_FIELD_GET(GMD_ID_RELEASE_MASK, gt->info.gmdid); 405 gt_list->gt_list[id].ip_ver_rev = 406 REG_FIELD_GET(GMD_ID_REVID, gt->info.gmdid); 407 } 408 409 if (copy_to_user(query_ptr, gt_list, size)) { 410 kfree(gt_list); 411 return -EFAULT; 412 } 413 kfree(gt_list); 414 415 return 0; 416 } 417 418 static int query_hwconfig(struct xe_device *xe, 419 struct drm_xe_device_query *query) 420 { 421 struct xe_gt *gt = xe_root_mmio_gt(xe); 422 size_t size = xe_guc_hwconfig_size(>->uc.guc); 423 void __user *query_ptr = u64_to_user_ptr(query->data); 424 void *hwconfig; 425 426 if (query->size == 0) { 427 query->size = size; 428 return 0; 429 } else if (XE_IOCTL_DBG(xe, query->size != size)) { 430 return -EINVAL; 431 } 432 433 hwconfig = kzalloc(size, GFP_KERNEL); 434 if (!hwconfig) 435 return -ENOMEM; 436 437 xe_guc_hwconfig_copy(>->uc.guc, hwconfig); 438 439 if (copy_to_user(query_ptr, hwconfig, size)) { 440 kfree(hwconfig); 441 return -EFAULT; 442 } 443 kfree(hwconfig); 444 445 return 0; 446 } 447 448 static size_t calc_topo_query_size(struct xe_device *xe) 449 { 450 struct xe_gt *gt; 451 size_t query_size = 0; 452 int id; 453 454 for_each_gt(gt, xe, id) { 455 query_size += 3 * sizeof(struct drm_xe_query_topology_mask) + 456 sizeof_field(struct xe_gt, fuse_topo.g_dss_mask) + 457 sizeof_field(struct xe_gt, fuse_topo.c_dss_mask) + 458 sizeof_field(struct xe_gt, fuse_topo.eu_mask_per_dss); 459 460 /* L3bank mask may not be available for some GTs */ 461 if (!XE_WA(gt, no_media_l3)) 462 query_size += sizeof(struct drm_xe_query_topology_mask) + 463 sizeof_field(struct xe_gt, fuse_topo.l3_bank_mask); 464 } 465 466 return query_size; 467 } 468 469 static int copy_mask(void __user **ptr, 470 struct drm_xe_query_topology_mask *topo, 471 void *mask, size_t mask_size) 472 { 473 topo->num_bytes = mask_size; 474 475 if (copy_to_user(*ptr, topo, sizeof(*topo))) 476 return -EFAULT; 477 *ptr += sizeof(topo); 478 479 if (copy_to_user(*ptr, mask, mask_size)) 480 return -EFAULT; 481 *ptr += mask_size; 482 483 return 0; 484 } 485 486 static int query_gt_topology(struct xe_device *xe, 487 struct drm_xe_device_query *query) 488 { 489 void __user *query_ptr = u64_to_user_ptr(query->data); 490 size_t size = calc_topo_query_size(xe); 491 struct drm_xe_query_topology_mask topo; 492 struct xe_gt *gt; 493 int id; 494 495 if (query->size == 0) { 496 query->size = size; 497 return 0; 498 } else if (XE_IOCTL_DBG(xe, query->size != size)) { 499 return -EINVAL; 500 } 501 502 for_each_gt(gt, xe, id) { 503 int err; 504 505 topo.gt_id = id; 506 507 topo.type = DRM_XE_TOPO_DSS_GEOMETRY; 508 err = copy_mask(&query_ptr, &topo, gt->fuse_topo.g_dss_mask, 509 sizeof(gt->fuse_topo.g_dss_mask)); 510 if (err) 511 return err; 512 513 topo.type = DRM_XE_TOPO_DSS_COMPUTE; 514 err = copy_mask(&query_ptr, &topo, gt->fuse_topo.c_dss_mask, 515 sizeof(gt->fuse_topo.c_dss_mask)); 516 if (err) 517 return err; 518 519 /* 520 * If the kernel doesn't have a way to obtain a correct L3bank 521 * mask, then it's better to omit L3 from the query rather than 522 * reporting bogus or zeroed information to userspace. 523 */ 524 if (!XE_WA(gt, no_media_l3)) { 525 topo.type = DRM_XE_TOPO_L3_BANK; 526 err = copy_mask(&query_ptr, &topo, gt->fuse_topo.l3_bank_mask, 527 sizeof(gt->fuse_topo.l3_bank_mask)); 528 if (err) 529 return err; 530 } 531 532 topo.type = gt->fuse_topo.eu_type == XE_GT_EU_TYPE_SIMD16 ? 533 DRM_XE_TOPO_SIMD16_EU_PER_DSS : 534 DRM_XE_TOPO_EU_PER_DSS; 535 err = copy_mask(&query_ptr, &topo, 536 gt->fuse_topo.eu_mask_per_dss, 537 sizeof(gt->fuse_topo.eu_mask_per_dss)); 538 if (err) 539 return err; 540 } 541 542 return 0; 543 } 544 545 static int 546 query_uc_fw_version(struct xe_device *xe, struct drm_xe_device_query *query) 547 { 548 struct drm_xe_query_uc_fw_version __user *query_ptr = u64_to_user_ptr(query->data); 549 size_t size = sizeof(struct drm_xe_query_uc_fw_version); 550 struct drm_xe_query_uc_fw_version resp; 551 struct xe_uc_fw_version *version = NULL; 552 553 if (query->size == 0) { 554 query->size = size; 555 return 0; 556 } else if (XE_IOCTL_DBG(xe, query->size != size)) { 557 return -EINVAL; 558 } 559 560 if (copy_from_user(&resp, query_ptr, size)) 561 return -EFAULT; 562 563 if (XE_IOCTL_DBG(xe, resp.pad || resp.pad2 || resp.reserved)) 564 return -EINVAL; 565 566 switch (resp.uc_type) { 567 case XE_QUERY_UC_TYPE_GUC_SUBMISSION: { 568 struct xe_guc *guc = &xe->tiles[0].primary_gt->uc.guc; 569 570 version = &guc->fw.versions.found[XE_UC_FW_VER_COMPATIBILITY]; 571 break; 572 } 573 case XE_QUERY_UC_TYPE_HUC: { 574 struct xe_gt *media_gt = NULL; 575 struct xe_huc *huc; 576 577 if (MEDIA_VER(xe) >= 13) { 578 struct xe_tile *tile; 579 u8 gt_id; 580 581 for_each_tile(tile, xe, gt_id) { 582 if (tile->media_gt) { 583 media_gt = tile->media_gt; 584 break; 585 } 586 } 587 } else { 588 media_gt = xe->tiles[0].primary_gt; 589 } 590 591 if (!media_gt) 592 break; 593 594 huc = &media_gt->uc.huc; 595 if (huc->fw.status == XE_UC_FIRMWARE_RUNNING) 596 version = &huc->fw.versions.found[XE_UC_FW_VER_RELEASE]; 597 break; 598 } 599 default: 600 return -EINVAL; 601 } 602 603 if (version) { 604 resp.branch_ver = 0; 605 resp.major_ver = version->major; 606 resp.minor_ver = version->minor; 607 resp.patch_ver = version->patch; 608 } else { 609 return -ENODEV; 610 } 611 612 if (copy_to_user(query_ptr, &resp, size)) 613 return -EFAULT; 614 615 return 0; 616 } 617 618 static size_t calc_oa_unit_query_size(struct xe_device *xe) 619 { 620 size_t size = sizeof(struct drm_xe_query_oa_units); 621 struct xe_gt *gt; 622 int i, id; 623 624 for_each_gt(gt, xe, id) { 625 for (i = 0; i < gt->oa.num_oa_units; i++) { 626 size += sizeof(struct drm_xe_oa_unit); 627 size += gt->oa.oa_unit[i].num_engines * 628 sizeof(struct drm_xe_engine_class_instance); 629 } 630 } 631 632 return size; 633 } 634 635 static int query_oa_units(struct xe_device *xe, 636 struct drm_xe_device_query *query) 637 { 638 void __user *query_ptr = u64_to_user_ptr(query->data); 639 size_t size = calc_oa_unit_query_size(xe); 640 struct drm_xe_query_oa_units *qoa; 641 enum xe_hw_engine_id hwe_id; 642 struct drm_xe_oa_unit *du; 643 struct xe_hw_engine *hwe; 644 struct xe_oa_unit *u; 645 int gt_id, i, j, ret; 646 struct xe_gt *gt; 647 u8 *pdu; 648 649 if (query->size == 0) { 650 query->size = size; 651 return 0; 652 } else if (XE_IOCTL_DBG(xe, query->size != size)) { 653 return -EINVAL; 654 } 655 656 qoa = kzalloc(size, GFP_KERNEL); 657 if (!qoa) 658 return -ENOMEM; 659 660 pdu = (u8 *)&qoa->oa_units[0]; 661 for_each_gt(gt, xe, gt_id) { 662 for (i = 0; i < gt->oa.num_oa_units; i++) { 663 u = >->oa.oa_unit[i]; 664 du = (struct drm_xe_oa_unit *)pdu; 665 666 du->oa_unit_id = u->oa_unit_id; 667 du->oa_unit_type = u->type; 668 du->oa_timestamp_freq = xe_oa_timestamp_frequency(gt); 669 du->capabilities = DRM_XE_OA_CAPS_BASE; 670 671 j = 0; 672 for_each_hw_engine(hwe, gt, hwe_id) { 673 if (!xe_hw_engine_is_reserved(hwe) && 674 xe_oa_unit_id(hwe) == u->oa_unit_id) { 675 du->eci[j].engine_class = 676 xe_to_user_engine_class[hwe->class]; 677 du->eci[j].engine_instance = hwe->logical_instance; 678 du->eci[j].gt_id = gt->info.id; 679 j++; 680 } 681 } 682 du->num_engines = j; 683 pdu += sizeof(*du) + j * sizeof(du->eci[0]); 684 qoa->num_oa_units++; 685 } 686 } 687 688 ret = copy_to_user(query_ptr, qoa, size); 689 kfree(qoa); 690 691 return ret ? -EFAULT : 0; 692 } 693 694 static int (* const xe_query_funcs[])(struct xe_device *xe, 695 struct drm_xe_device_query *query) = { 696 query_engines, 697 query_mem_regions, 698 query_config, 699 query_gt_list, 700 query_hwconfig, 701 query_gt_topology, 702 query_engine_cycles, 703 query_uc_fw_version, 704 query_oa_units, 705 }; 706 707 int xe_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file) 708 { 709 struct xe_device *xe = to_xe_device(dev); 710 struct drm_xe_device_query *query = data; 711 u32 idx; 712 713 if (XE_IOCTL_DBG(xe, query->extensions) || 714 XE_IOCTL_DBG(xe, query->reserved[0] || query->reserved[1])) 715 return -EINVAL; 716 717 if (XE_IOCTL_DBG(xe, query->query >= ARRAY_SIZE(xe_query_funcs))) 718 return -EINVAL; 719 720 idx = array_index_nospec(query->query, ARRAY_SIZE(xe_query_funcs)); 721 if (XE_IOCTL_DBG(xe, !xe_query_funcs[idx])) 722 return -EINVAL; 723 724 return xe_query_funcs[idx](xe, query); 725 } 726