xref: /linux/drivers/gpu/drm/xe/xe_pt.h (revision 68a052239fc4b351e961f698b824f7654a346091)
1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2022 Intel Corporation
4  */
5 #ifndef _XE_PT_H_
6 #define _XE_PT_H_
7 
8 #include <linux/types.h>
9 
10 #include "xe_pt_types.h"
11 
12 struct dma_fence;
13 struct drm_exec;
14 struct xe_bo;
15 struct xe_device;
16 struct xe_exec_queue;
17 struct xe_svm_range;
18 struct xe_sync_entry;
19 struct xe_tile;
20 struct xe_vm;
21 struct xe_vma;
22 struct xe_vma_ops;
23 
24 /* Largest huge pte is currently 1GiB. May become device dependent. */
25 #define MAX_HUGEPTE_LEVEL 2
26 
27 #define xe_pt_write(xe, map, idx, data) \
28 	xe_map_wr(xe, map, (idx) * sizeof(u64), u64, data)
29 
30 unsigned int xe_pt_shift(unsigned int level);
31 
32 struct xe_pt *xe_pt_create(struct xe_vm *vm, struct xe_tile *tile,
33 			   unsigned int level, struct drm_exec *exec);
34 
35 void xe_pt_populate_empty(struct xe_tile *tile, struct xe_vm *vm,
36 			  struct xe_pt *pt);
37 
38 void xe_pt_destroy(struct xe_pt *pt, u32 flags, struct llist_head *deferred);
39 
40 void xe_pt_clear(struct xe_device *xe, struct xe_pt *pt);
41 
42 int xe_pt_update_ops_prepare(struct xe_tile *tile, struct xe_vma_ops *vops);
43 struct dma_fence *xe_pt_update_ops_run(struct xe_tile *tile,
44 				       struct xe_vma_ops *vops);
45 void xe_pt_update_ops_fini(struct xe_tile *tile, struct xe_vma_ops *vops);
46 void xe_pt_update_ops_abort(struct xe_tile *tile, struct xe_vma_ops *vops);
47 
48 bool xe_pt_zap_ptes(struct xe_tile *tile, struct xe_vma *vma);
49 bool xe_pt_zap_ptes_range(struct xe_tile *tile, struct xe_vm *vm,
50 			  struct xe_svm_range *range);
51 
52 #endif
53