1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #ifndef _XE_PCODE_API_H_ 7 #define _XE_PCODE_API_H_ 8 9 /* Internal to xe_pcode */ 10 11 #include "regs/xe_reg_defs.h" 12 13 #define PCODE_MAILBOX XE_REG(0x138124) 14 #define PCODE_READY REG_BIT(31) 15 #define PCODE_MB_PARAM2 REG_GENMASK(23, 16) 16 #define PCODE_MB_PARAM1 REG_GENMASK(15, 8) 17 #define PCODE_MB_COMMAND REG_GENMASK(7, 0) 18 #define PCODE_ERROR_MASK 0xFF 19 #define PCODE_SUCCESS 0x0 20 #define PCODE_ILLEGAL_CMD 0x1 21 #define PCODE_TIMEOUT 0x2 22 #define PCODE_ILLEGAL_DATA 0x3 23 #define PCODE_ILLEGAL_SUBCOMMAND 0x4 24 #define PCODE_LOCKED 0x6 25 #define PCODE_GT_RATIO_OUT_OF_RANGE 0x10 26 #define PCODE_REJECTED 0x11 27 28 #define PCODE_DATA0 XE_REG(0x138128) 29 #define PCODE_DATA1 XE_REG(0x13812C) 30 31 /* Min Freq QOS Table */ 32 #define PCODE_WRITE_MIN_FREQ_TABLE 0x8 33 #define PCODE_READ_MIN_FREQ_TABLE 0x9 34 #define PCODE_FREQ_RING_RATIO_SHIFT 16 35 36 /* PCODE Init */ 37 #define DGFX_PCODE_STATUS 0x7E 38 #define DGFX_GET_INIT_STATUS 0x0 39 #define DGFX_INIT_STATUS_COMPLETE 0x1 40 #define DGFX_LINK_DOWNGRADE_STATUS REG_BIT(31) 41 42 #define PCODE_POWER_SETUP 0x7C 43 #define POWER_SETUP_SUBCOMMAND_READ_I1 0x4 44 #define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5 45 #define POWER_SETUP_I1_WATTS REG_BIT(31) 46 #define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */ 47 #define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0) 48 49 #define READ_PSYSGPU_POWER_LIMIT 0x6 50 #define WRITE_PSYSGPU_POWER_LIMIT 0x7 51 #define READ_PACKAGE_POWER_LIMIT 0x8 52 #define WRITE_PACKAGE_POWER_LIMIT 0x9 53 #define READ_PL_FROM_PCODE 0x0 54 #define READ_PL_FROM_FW 0x1 55 #define READ_PL_ACCEPTED 0x2 56 57 #define PCODE_THERMAL_INFO 0x25 58 #define READ_THERMAL_LIMITS 0x0 59 #define READ_THERMAL_CONFIG 0x1 60 #define READ_THERMAL_DATA 0x2 61 #define PCIE_SENSOR_GROUP_ID 0x2 62 #define PCIE_SENSOR_MASK REG_GENMASK(31, 16) 63 64 #define PCODE_LATE_BINDING 0x5C 65 #define GET_CAPABILITY_STATUS 0x0 66 #define V1_FAN_SUPPORTED REG_BIT(0) 67 #define VR_PARAMS_SUPPORTED REG_BIT(3) 68 #define V1_FAN_PROVISIONED REG_BIT(16) 69 #define VR_PARAMS_PROVISIONED REG_BIT(19) 70 #define GET_VERSION_LOW 0x1 71 #define GET_VERSION_HIGH 0x2 72 #define MAJOR_VERSION_MASK REG_GENMASK(31, 16) 73 #define MINOR_VERSION_MASK REG_GENMASK(15, 0) 74 #define HOTFIX_VERSION_MASK REG_GENMASK(31, 16) 75 #define BUILD_VERSION_MASK REG_GENMASK(15, 0) 76 #define FAN_TABLE 1 77 #define VR_CONFIG 2 78 79 #define PCODE_FREQUENCY_CONFIG 0x6e 80 /* Frequency Config Sub Commands (param1) */ 81 #define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0 82 #define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1 83 /* Domain IDs (param2) */ 84 #define PCODE_MBOX_DOMAIN_HBM 0x2 85 86 #define FAN_SPEED_CONTROL 0x7D 87 #define FSC_READ_NUM_FANS 0x4 88 89 #define PCODE_SCRATCH(x) XE_REG(0x138320 + ((x) * 4)) 90 /* PCODE_SCRATCH0 */ 91 #define BREADCRUMB_VERSION REG_GENMASK(31, 29) 92 #define AUXINFO_REG_OFFSET REG_GENMASK(17, 15) 93 #define OVERFLOW_REG_OFFSET REG_GENMASK(14, 12) 94 #define HISTORY_TRACKING REG_BIT(11) 95 #define OVERFLOW_SUPPORT REG_BIT(10) 96 #define AUXINFO_SUPPORT REG_BIT(9) 97 #define FDO_MODE REG_BIT(4) 98 #define BOOT_STATUS REG_GENMASK(3, 1) 99 #define CRITICAL_FAILURE 4 100 #define NON_CRITICAL_FAILURE 7 101 102 /* Auxiliary info bits */ 103 #define AUXINFO_HISTORY_OFFSET REG_GENMASK(31, 29) 104 105 #define BMG_PCIE_CAP XE_REG(0x138340) 106 #define LINK_DOWNGRADE REG_GENMASK(1, 0) 107 #define DOWNGRADE_CAPABLE 2 108 109 #endif 110