xref: /linux/drivers/gpu/drm/xe/xe_pcode.h (revision 5b0764a53235d3c77e1ed674e836e1b3fe1a4b1f)
1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2022 Intel Corporation
4  */
5 
6 #ifndef _XE_PCODE_H_
7 #define _XE_PCODE_H_
8 
9 #include <linux/types.h>
10 
11 struct drm_device;
12 struct xe_device;
13 struct xe_tile;
14 
15 struct xe_pcode_version {
16 	u16 minor;
17 	u16 major;
18 	u32 engg;
19 };
20 
21 #define PCODE_DEFAULT_TIMEOUT_MS	10
22 
23 int xe_pcode_init_early(struct xe_tile *tile);
24 int xe_pcode_probe_early(struct xe_device *xe);
25 int xe_pcode_ready(struct xe_device *xe, bool locked);
26 int xe_pcode_init_min_freq_table(struct xe_tile *tile, u32 min_gt_freq,
27 				 u32 max_gt_freq);
28 int xe_pcode_read(struct xe_tile *tile, u32 mbox, u32 *val0, u32 *val1);
29 int xe_pcode_write_timeout(struct xe_tile *tile, u32 mbox, u32 val,
30 			   int timeout_ms);
31 int xe_pcode_write64_timeout(struct xe_tile *tile, u32 mbox, u32 data0,
32 			     u32 data1, int timeout);
33 int xe_get_pcode_version(struct xe_device *xe, struct xe_pcode_version *version);
34 
35 #define xe_pcode_write(tile, mbox, val) \
36 	xe_pcode_write_timeout(tile, mbox, val, PCODE_DEFAULT_TIMEOUT_MS)
37 
38 int xe_pcode_request(struct xe_tile *tile, u32 mbox, u32 request,
39 		     u32 reply_mask, u32 reply, int timeout_ms);
40 
41 #define PCODE_MBOX(mbcmd, param1, param2)\
42 	(FIELD_PREP(PCODE_MB_COMMAND, mbcmd)\
43 	| FIELD_PREP(PCODE_MB_PARAM1, param1)\
44 	| FIELD_PREP(PCODE_MB_PARAM2, param2))
45 
46 #endif
47