xref: /linux/drivers/gpu/drm/xe/xe_pcode.h (revision 570f7e331f5febb30f1384817463c7e42b65ca7d)
1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2022 Intel Corporation
4  */
5 
6 #ifndef _XE_PCODE_H_
7 #define _XE_PCODE_H_
8 
9 #include <linux/types.h>
10 
11 struct drm_device;
12 struct xe_device;
13 struct xe_tile;
14 
15 struct xe_pcode_version {
16 	u16 minor;
17 	u16 major;
18 	u32 engg;
19 };
20 
21 int xe_pcode_init_early(struct xe_tile *tile);
22 int xe_pcode_probe_early(struct xe_device *xe);
23 int xe_pcode_ready(struct xe_device *xe, bool locked);
24 int xe_pcode_init_min_freq_table(struct xe_tile *tile, u32 min_gt_freq,
25 				 u32 max_gt_freq);
26 int xe_pcode_read(struct xe_tile *tile, u32 mbox, u32 *val, u32 *val1);
27 int xe_pcode_write_timeout(struct xe_tile *tile, u32 mbox, u32 val,
28 			   int timeout_ms);
29 int xe_pcode_write64_timeout(struct xe_tile *tile, u32 mbox, u32 data0,
30 			     u32 data1, int timeout);
31 int xe_get_pcode_version(struct xe_device *xe, struct xe_pcode_version *version);
32 
33 #define xe_pcode_write(tile, mbox, val) \
34 	xe_pcode_write_timeout(tile, mbox, val, 1)
35 
36 int xe_pcode_request(struct xe_tile *tile, u32 mbox, u32 request,
37 		     u32 reply_mask, u32 reply, int timeout_ms);
38 
39 #define PCODE_MBOX(mbcmd, param1, param2)\
40 	(FIELD_PREP(PCODE_MB_COMMAND, mbcmd)\
41 	| FIELD_PREP(PCODE_MB_PARAM1, param1)\
42 	| FIELD_PREP(PCODE_MB_PARAM2, param2))
43 
44 #endif
45