xref: /linux/drivers/gpu/drm/xe/xe_pcode.h (revision dd08ebf6c3525a7ea2186e636df064ea47281987)
1*dd08ebf6SMatthew Brost /* SPDX-License-Identifier: MIT */
2*dd08ebf6SMatthew Brost /*
3*dd08ebf6SMatthew Brost  * Copyright © 2022 Intel Corporation
4*dd08ebf6SMatthew Brost  */
5*dd08ebf6SMatthew Brost 
6*dd08ebf6SMatthew Brost #ifndef _XE_PCODE_H_
7*dd08ebf6SMatthew Brost #define _XE_PCODE_H_
8*dd08ebf6SMatthew Brost 
9*dd08ebf6SMatthew Brost #include <linux/types.h>
10*dd08ebf6SMatthew Brost struct xe_gt;
11*dd08ebf6SMatthew Brost 
12*dd08ebf6SMatthew Brost int xe_pcode_probe(struct xe_gt *gt);
13*dd08ebf6SMatthew Brost int xe_pcode_init(struct xe_gt *gt);
14*dd08ebf6SMatthew Brost int xe_pcode_init_min_freq_table(struct xe_gt *gt, u32 min_gt_freq,
15*dd08ebf6SMatthew Brost 				 u32 max_gt_freq);
16*dd08ebf6SMatthew Brost int xe_pcode_read(struct xe_gt *gt, u32 mbox, u32 *val, u32 *val1);
17*dd08ebf6SMatthew Brost int xe_pcode_write_timeout(struct xe_gt *gt, u32 mbox, u32 val,
18*dd08ebf6SMatthew Brost 			   int timeout_ms);
19*dd08ebf6SMatthew Brost #define xe_pcode_write(gt, mbox, val) \
20*dd08ebf6SMatthew Brost 	xe_pcode_write_timeout(gt, mbox, val, 1)
21*dd08ebf6SMatthew Brost 
22*dd08ebf6SMatthew Brost int xe_pcode_request(struct xe_gt *gt, u32 mbox, u32 request,
23*dd08ebf6SMatthew Brost 		     u32 reply_mask, u32 reply, int timeout_ms);
24*dd08ebf6SMatthew Brost 
25*dd08ebf6SMatthew Brost #endif
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