1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_pcode.h" 7 8 #include <linux/delay.h> 9 #include <linux/errno.h> 10 #include <linux/error-injection.h> 11 12 #include <drm/drm_managed.h> 13 14 #include "xe_assert.h" 15 #include "xe_device.h" 16 #include "xe_mmio.h" 17 #include "xe_pcode_api.h" 18 19 /** 20 * DOC: PCODE 21 * 22 * Xe PCODE is the component responsible for interfacing with the PCODE 23 * firmware. 24 * It shall provide a very simple ABI to other Xe components, but be the 25 * single and consolidated place that will communicate with PCODE. All read 26 * and write operations to PCODE will be internal and private to this component. 27 * 28 * What's next: 29 * - PCODE hw metrics 30 * - PCODE for display operations 31 */ 32 33 static int pcode_mailbox_status(struct xe_tile *tile) 34 { 35 u32 err; 36 static const struct pcode_err_decode err_decode[] = { 37 [PCODE_ILLEGAL_CMD] = {-ENXIO, "Illegal Command"}, 38 [PCODE_TIMEOUT] = {-ETIMEDOUT, "Timed out"}, 39 [PCODE_ILLEGAL_DATA] = {-EINVAL, "Illegal Data"}, 40 [PCODE_ILLEGAL_SUBCOMMAND] = {-ENXIO, "Illegal Subcommand"}, 41 [PCODE_LOCKED] = {-EBUSY, "PCODE Locked"}, 42 [PCODE_GT_RATIO_OUT_OF_RANGE] = {-EOVERFLOW, 43 "GT ratio out of range"}, 44 [PCODE_REJECTED] = {-EACCES, "PCODE Rejected"}, 45 [PCODE_ERROR_MASK] = {-EPROTO, "Unknown"}, 46 }; 47 48 err = xe_mmio_read32(&tile->mmio, PCODE_MAILBOX) & PCODE_ERROR_MASK; 49 if (err) { 50 drm_err(&tile_to_xe(tile)->drm, "PCODE Mailbox failed: %d %s", err, 51 err_decode[err].str ?: "Unknown"); 52 return err_decode[err].errno ?: -EPROTO; 53 } 54 55 return 0; 56 } 57 58 static int __pcode_mailbox_rw(struct xe_tile *tile, u32 mbox, u32 *data0, u32 *data1, 59 unsigned int timeout_ms, bool return_data, 60 bool atomic) 61 { 62 struct xe_mmio *mmio = &tile->mmio; 63 int err; 64 65 if (tile_to_xe(tile)->info.skip_pcode) 66 return 0; 67 68 if ((xe_mmio_read32(mmio, PCODE_MAILBOX) & PCODE_READY) != 0) 69 return -EAGAIN; 70 71 xe_mmio_write32(mmio, PCODE_DATA0, *data0); 72 xe_mmio_write32(mmio, PCODE_DATA1, data1 ? *data1 : 0); 73 xe_mmio_write32(mmio, PCODE_MAILBOX, PCODE_READY | mbox); 74 75 err = xe_mmio_wait32(mmio, PCODE_MAILBOX, PCODE_READY, 0, 76 timeout_ms * USEC_PER_MSEC, NULL, atomic); 77 if (err) 78 return err; 79 80 if (return_data) { 81 *data0 = xe_mmio_read32(mmio, PCODE_DATA0); 82 if (data1) 83 *data1 = xe_mmio_read32(mmio, PCODE_DATA1); 84 } 85 86 return pcode_mailbox_status(tile); 87 } 88 89 static int pcode_mailbox_rw(struct xe_tile *tile, u32 mbox, u32 *data0, u32 *data1, 90 unsigned int timeout_ms, bool return_data, 91 bool atomic) 92 { 93 if (tile_to_xe(tile)->info.skip_pcode) 94 return 0; 95 96 lockdep_assert_held(&tile->pcode.lock); 97 98 return __pcode_mailbox_rw(tile, mbox, data0, data1, timeout_ms, return_data, atomic); 99 } 100 101 int xe_pcode_write_timeout(struct xe_tile *tile, u32 mbox, u32 data, int timeout) 102 { 103 int err; 104 105 mutex_lock(&tile->pcode.lock); 106 err = pcode_mailbox_rw(tile, mbox, &data, NULL, timeout, false, false); 107 mutex_unlock(&tile->pcode.lock); 108 109 return err; 110 } 111 112 int xe_pcode_read(struct xe_tile *tile, u32 mbox, u32 *val, u32 *val1) 113 { 114 int err; 115 116 mutex_lock(&tile->pcode.lock); 117 err = pcode_mailbox_rw(tile, mbox, val, val1, 1, true, false); 118 mutex_unlock(&tile->pcode.lock); 119 120 return err; 121 } 122 123 static int pcode_try_request(struct xe_tile *tile, u32 mbox, 124 u32 request, u32 reply_mask, u32 reply, 125 u32 *status, bool atomic, int timeout_us, bool locked) 126 { 127 int slept, wait = 10; 128 129 xe_tile_assert(tile, timeout_us > 0); 130 131 for (slept = 0; slept < timeout_us; slept += wait) { 132 if (locked) 133 *status = pcode_mailbox_rw(tile, mbox, &request, NULL, 1, true, 134 atomic); 135 else 136 *status = __pcode_mailbox_rw(tile, mbox, &request, NULL, 1, true, 137 atomic); 138 if ((*status == 0) && ((request & reply_mask) == reply)) 139 return 0; 140 141 if (atomic) 142 udelay(wait); 143 else 144 usleep_range(wait, wait << 1); 145 wait <<= 1; 146 } 147 148 return -ETIMEDOUT; 149 } 150 151 /** 152 * xe_pcode_request - send PCODE request until acknowledgment 153 * @tile: tile 154 * @mbox: PCODE mailbox ID the request is targeted for 155 * @request: request ID 156 * @reply_mask: mask used to check for request acknowledgment 157 * @reply: value used to check for request acknowledgment 158 * @timeout_base_ms: timeout for polling with preemption enabled 159 * 160 * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE 161 * reports an error or an overall timeout of @timeout_base_ms+50 ms expires. 162 * The request is acknowledged once the PCODE reply dword equals @reply after 163 * applying @reply_mask. Polling is first attempted with preemption enabled 164 * for @timeout_base_ms and if this times out for another 50 ms with 165 * preemption disabled. 166 * 167 * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some 168 * other error as reported by PCODE. 169 */ 170 int xe_pcode_request(struct xe_tile *tile, u32 mbox, u32 request, 171 u32 reply_mask, u32 reply, int timeout_base_ms) 172 { 173 u32 status; 174 int ret; 175 176 xe_tile_assert(tile, timeout_base_ms <= 3); 177 178 mutex_lock(&tile->pcode.lock); 179 180 ret = pcode_try_request(tile, mbox, request, reply_mask, reply, &status, 181 false, timeout_base_ms * 1000, true); 182 if (!ret) 183 goto out; 184 185 /* 186 * The above can time out if the number of requests was low (2 in the 187 * worst case) _and_ PCODE was busy for some reason even after a 188 * (queued) request and @timeout_base_ms delay. As a workaround retry 189 * the poll with preemption disabled to maximize the number of 190 * requests. Increase the timeout from @timeout_base_ms to 50ms to 191 * account for interrupts that could reduce the number of these 192 * requests, and for any quirks of the PCODE firmware that delays 193 * the request completion. 194 */ 195 drm_err(&tile_to_xe(tile)->drm, 196 "PCODE timeout, retrying with preemption disabled\n"); 197 preempt_disable(); 198 ret = pcode_try_request(tile, mbox, request, reply_mask, reply, &status, 199 true, 50 * 1000, true); 200 preempt_enable(); 201 202 out: 203 mutex_unlock(&tile->pcode.lock); 204 return status ? status : ret; 205 } 206 /** 207 * xe_pcode_init_min_freq_table - Initialize PCODE's QOS frequency table 208 * @tile: tile instance 209 * @min_gt_freq: Minimal (RPn) GT frequency in units of 50MHz. 210 * @max_gt_freq: Maximal (RP0) GT frequency in units of 50MHz. 211 * 212 * This function initialize PCODE's QOS frequency table for a proper minimal 213 * frequency/power steering decision, depending on the current requested GT 214 * frequency. For older platforms this was a more complete table including 215 * the IA freq. However for the latest platforms this table become a simple 216 * 1-1 Ring vs GT frequency. Even though, without setting it, PCODE might 217 * not take the right decisions for some memory frequencies and affect latency. 218 * 219 * It returns 0 on success, and -ERROR number on failure, -EINVAL if max 220 * frequency is higher then the minimal, and other errors directly translated 221 * from the PCODE Error returns: 222 * - -ENXIO: "Illegal Command" 223 * - -ETIMEDOUT: "Timed out" 224 * - -EINVAL: "Illegal Data" 225 * - -ENXIO, "Illegal Subcommand" 226 * - -EBUSY: "PCODE Locked" 227 * - -EOVERFLOW, "GT ratio out of range" 228 * - -EACCES, "PCODE Rejected" 229 * - -EPROTO, "Unknown" 230 */ 231 int xe_pcode_init_min_freq_table(struct xe_tile *tile, u32 min_gt_freq, 232 u32 max_gt_freq) 233 { 234 int ret; 235 u32 freq; 236 237 if (!tile_to_xe(tile)->info.has_llc) 238 return 0; 239 240 if (max_gt_freq <= min_gt_freq) 241 return -EINVAL; 242 243 mutex_lock(&tile->pcode.lock); 244 for (freq = min_gt_freq; freq <= max_gt_freq; freq++) { 245 u32 data = freq << PCODE_FREQ_RING_RATIO_SHIFT | freq; 246 247 ret = pcode_mailbox_rw(tile, PCODE_WRITE_MIN_FREQ_TABLE, 248 &data, NULL, 1, false, false); 249 if (ret) 250 goto unlock; 251 } 252 253 unlock: 254 mutex_unlock(&tile->pcode.lock); 255 return ret; 256 } 257 258 /** 259 * xe_pcode_ready - Ensure PCODE is initialized 260 * @xe: xe instance 261 * @locked: true if lock held, false otherwise 262 * 263 * PCODE init mailbox is polled only on root gt of root tile 264 * as the root tile provides the initialization is complete only 265 * after all the tiles have completed the initialization. 266 * Called only on early probe without locks and with locks in 267 * resume path. 268 * 269 * Returns 0 on success, and -error number on failure. 270 */ 271 int xe_pcode_ready(struct xe_device *xe, bool locked) 272 { 273 u32 status, request = DGFX_GET_INIT_STATUS; 274 struct xe_tile *tile = xe_device_get_root_tile(xe); 275 int timeout_us = 180000000; /* 3 min */ 276 int ret; 277 278 if (xe->info.skip_pcode) 279 return 0; 280 281 if (!IS_DGFX(xe)) 282 return 0; 283 284 if (locked) 285 mutex_lock(&tile->pcode.lock); 286 287 ret = pcode_try_request(tile, DGFX_PCODE_STATUS, request, 288 DGFX_INIT_STATUS_COMPLETE, 289 DGFX_INIT_STATUS_COMPLETE, 290 &status, false, timeout_us, locked); 291 292 if (locked) 293 mutex_unlock(&tile->pcode.lock); 294 295 if (ret) 296 drm_err(&xe->drm, 297 "PCODE initialization timedout after: 3 min\n"); 298 299 return ret; 300 } 301 302 /** 303 * xe_pcode_init: initialize components of PCODE 304 * @tile: tile instance 305 * 306 * This function initializes the xe_pcode component. 307 * To be called once only during probe. 308 */ 309 void xe_pcode_init(struct xe_tile *tile) 310 { 311 drmm_mutex_init(&tile_to_xe(tile)->drm, &tile->pcode.lock); 312 } 313 314 /** 315 * xe_pcode_probe_early: initializes PCODE 316 * @xe: xe instance 317 * 318 * This function checks the initialization status of PCODE 319 * To be called once only during early probe without locks. 320 * 321 * Returns 0 on success, error code otherwise 322 */ 323 int xe_pcode_probe_early(struct xe_device *xe) 324 { 325 return xe_pcode_ready(xe, false); 326 } 327 ALLOW_ERROR_INJECTION(xe_pcode_probe_early, ERRNO); /* See xe_pci_probe */ 328