1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 #include "xe_pci.h" 7 8 #include <kunit/static_stub.h> 9 #include <linux/device/driver.h> 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/pm_runtime.h> 13 14 #include <drm/drm_color_mgmt.h> 15 #include <drm/drm_drv.h> 16 #include <drm/intel/pciids.h> 17 18 #include "display/xe_display.h" 19 #include "regs/xe_gt_regs.h" 20 #include "regs/xe_regs.h" 21 #include "xe_configfs.h" 22 #include "xe_device.h" 23 #include "xe_drv.h" 24 #include "xe_gt.h" 25 #include "xe_gt_sriov_vf.h" 26 #include "xe_guc.h" 27 #include "xe_macros.h" 28 #include "xe_mmio.h" 29 #include "xe_module.h" 30 #include "xe_pci_sriov.h" 31 #include "xe_pci_types.h" 32 #include "xe_pm.h" 33 #include "xe_printk.h" 34 #include "xe_sriov.h" 35 #include "xe_step.h" 36 #include "xe_survivability_mode.h" 37 #include "xe_tile.h" 38 39 enum toggle_d3cold { 40 D3COLD_DISABLE, 41 D3COLD_ENABLE, 42 }; 43 44 __diag_push(); 45 __diag_ignore_all("-Woverride-init", "Allow field overrides in table"); 46 47 #define PLATFORM(x) \ 48 .platform = XE_##x, \ 49 .platform_name = #x 50 51 #define NOP(x) x 52 53 static const struct xe_graphics_desc graphics_xelp = { 54 .hw_engine_mask = BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0), 55 }; 56 57 #define XE_HP_FEATURES \ 58 .has_range_tlb_inval = true 59 60 static const struct xe_graphics_desc graphics_xehpg = { 61 .hw_engine_mask = 62 BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) | 63 BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) | 64 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3), 65 66 XE_HP_FEATURES, 67 }; 68 69 static const struct xe_graphics_desc graphics_xehpc = { 70 .hw_engine_mask = 71 BIT(XE_HW_ENGINE_BCS0) | BIT(XE_HW_ENGINE_BCS1) | 72 BIT(XE_HW_ENGINE_BCS2) | BIT(XE_HW_ENGINE_BCS3) | 73 BIT(XE_HW_ENGINE_BCS4) | BIT(XE_HW_ENGINE_BCS5) | 74 BIT(XE_HW_ENGINE_BCS6) | BIT(XE_HW_ENGINE_BCS7) | 75 BIT(XE_HW_ENGINE_BCS8) | 76 BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) | 77 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3), 78 79 XE_HP_FEATURES, 80 81 .has_asid = 1, 82 .has_atomic_enable_pte_bit = 1, 83 .has_usm = 1, 84 }; 85 86 static const struct xe_graphics_desc graphics_xelpg = { 87 .hw_engine_mask = 88 BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) | 89 BIT(XE_HW_ENGINE_CCS0), 90 91 XE_HP_FEATURES, 92 }; 93 94 #define XE2_GFX_FEATURES \ 95 .has_asid = 1, \ 96 .has_atomic_enable_pte_bit = 1, \ 97 .has_range_tlb_inval = 1, \ 98 .has_usm = 1, \ 99 .has_64bit_timestamp = 1, \ 100 .hw_engine_mask = \ 101 BIT(XE_HW_ENGINE_RCS0) | \ 102 BIT(XE_HW_ENGINE_BCS8) | BIT(XE_HW_ENGINE_BCS0) | \ 103 GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0) 104 105 static const struct xe_graphics_desc graphics_xe2 = { 106 XE2_GFX_FEATURES, 107 }; 108 109 static const struct xe_graphics_desc graphics_xe3p_xpc = { 110 XE2_GFX_FEATURES, 111 .hw_engine_mask = 112 GENMASK(XE_HW_ENGINE_BCS8, XE_HW_ENGINE_BCS1) | 113 GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0), 114 }; 115 116 static const struct xe_media_desc media_xem = { 117 .hw_engine_mask = 118 GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) | 119 GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0), 120 }; 121 122 static const struct xe_media_desc media_xelpmp = { 123 .hw_engine_mask = 124 GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) | 125 GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0) | 126 BIT(XE_HW_ENGINE_GSCCS0) 127 }; 128 129 /* Pre-GMDID Graphics IPs */ 130 static const struct xe_ip graphics_ip_xelp = { 1200, "Xe_LP", &graphics_xelp }; 131 static const struct xe_ip graphics_ip_xelpp = { 1210, "Xe_LP+", &graphics_xelp }; 132 static const struct xe_ip graphics_ip_xehpg = { 1255, "Xe_HPG", &graphics_xehpg }; 133 static const struct xe_ip graphics_ip_xehpc = { 1260, "Xe_HPC", &graphics_xehpc }; 134 135 /* GMDID-based Graphics IPs */ 136 static const struct xe_ip graphics_ips[] = { 137 { 1270, "Xe_LPG", &graphics_xelpg }, 138 { 1271, "Xe_LPG", &graphics_xelpg }, 139 { 1274, "Xe_LPG+", &graphics_xelpg }, 140 { 2001, "Xe2_HPG", &graphics_xe2 }, 141 { 2002, "Xe2_HPG", &graphics_xe2 }, 142 { 2004, "Xe2_LPG", &graphics_xe2 }, 143 { 3000, "Xe3_LPG", &graphics_xe2 }, 144 { 3001, "Xe3_LPG", &graphics_xe2 }, 145 { 3003, "Xe3_LPG", &graphics_xe2 }, 146 { 3004, "Xe3_LPG", &graphics_xe2 }, 147 { 3005, "Xe3_LPG", &graphics_xe2 }, 148 { 3511, "Xe3p_XPC", &graphics_xe3p_xpc }, 149 }; 150 151 /* Pre-GMDID Media IPs */ 152 static const struct xe_ip media_ip_xem = { 1200, "Xe_M", &media_xem }; 153 static const struct xe_ip media_ip_xehpm = { 1255, "Xe_HPM", &media_xem }; 154 155 /* GMDID-based Media IPs */ 156 static const struct xe_ip media_ips[] = { 157 { 1300, "Xe_LPM+", &media_xelpmp }, 158 { 1301, "Xe2_HPM", &media_xelpmp }, 159 { 2000, "Xe2_LPM", &media_xelpmp }, 160 { 3000, "Xe3_LPM", &media_xelpmp }, 161 { 3002, "Xe3_LPM", &media_xelpmp }, 162 { 3500, "Xe3p_LPM", &media_xelpmp }, 163 { 3503, "Xe3p_HPM", &media_xelpmp }, 164 }; 165 166 static const struct xe_device_desc tgl_desc = { 167 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 168 .pre_gmdid_media_ip = &media_ip_xem, 169 PLATFORM(TIGERLAKE), 170 .dma_mask_size = 39, 171 .has_display = true, 172 .has_llc = true, 173 .has_sriov = true, 174 .max_gt_per_tile = 1, 175 .require_force_probe = true, 176 .va_bits = 48, 177 .vm_max_level = 3, 178 }; 179 180 static const struct xe_device_desc rkl_desc = { 181 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 182 .pre_gmdid_media_ip = &media_ip_xem, 183 PLATFORM(ROCKETLAKE), 184 .dma_mask_size = 39, 185 .has_display = true, 186 .has_llc = true, 187 .max_gt_per_tile = 1, 188 .require_force_probe = true, 189 .va_bits = 48, 190 .vm_max_level = 3, 191 }; 192 193 static const u16 adls_rpls_ids[] = { INTEL_RPLS_IDS(NOP), 0 }; 194 195 static const struct xe_device_desc adl_s_desc = { 196 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 197 .pre_gmdid_media_ip = &media_ip_xem, 198 PLATFORM(ALDERLAKE_S), 199 .dma_mask_size = 39, 200 .has_display = true, 201 .has_llc = true, 202 .has_sriov = true, 203 .max_gt_per_tile = 1, 204 .require_force_probe = true, 205 .subplatforms = (const struct xe_subplatform_desc[]) { 206 { XE_SUBPLATFORM_ALDERLAKE_S_RPLS, "RPLS", adls_rpls_ids }, 207 {}, 208 }, 209 .va_bits = 48, 210 .vm_max_level = 3, 211 }; 212 213 static const u16 adlp_rplu_ids[] = { INTEL_RPLU_IDS(NOP), 0 }; 214 215 static const struct xe_device_desc adl_p_desc = { 216 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 217 .pre_gmdid_media_ip = &media_ip_xem, 218 PLATFORM(ALDERLAKE_P), 219 .dma_mask_size = 39, 220 .has_display = true, 221 .has_llc = true, 222 .has_sriov = true, 223 .max_gt_per_tile = 1, 224 .require_force_probe = true, 225 .subplatforms = (const struct xe_subplatform_desc[]) { 226 { XE_SUBPLATFORM_ALDERLAKE_P_RPLU, "RPLU", adlp_rplu_ids }, 227 {}, 228 }, 229 .va_bits = 48, 230 .vm_max_level = 3, 231 }; 232 233 static const struct xe_device_desc adl_n_desc = { 234 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 235 .pre_gmdid_media_ip = &media_ip_xem, 236 PLATFORM(ALDERLAKE_N), 237 .dma_mask_size = 39, 238 .has_display = true, 239 .has_llc = true, 240 .has_sriov = true, 241 .max_gt_per_tile = 1, 242 .require_force_probe = true, 243 .va_bits = 48, 244 .vm_max_level = 3, 245 }; 246 247 #define DGFX_FEATURES \ 248 .is_dgfx = 1 249 250 static const struct xe_device_desc dg1_desc = { 251 .pre_gmdid_graphics_ip = &graphics_ip_xelpp, 252 .pre_gmdid_media_ip = &media_ip_xem, 253 DGFX_FEATURES, 254 PLATFORM(DG1), 255 .dma_mask_size = 39, 256 .has_display = true, 257 .has_gsc_nvm = 1, 258 .has_heci_gscfi = 1, 259 .max_gt_per_tile = 1, 260 .require_force_probe = true, 261 .va_bits = 48, 262 .vm_max_level = 3, 263 }; 264 265 static const u16 dg2_g10_ids[] = { INTEL_DG2_G10_IDS(NOP), INTEL_ATS_M150_IDS(NOP), 0 }; 266 static const u16 dg2_g11_ids[] = { INTEL_DG2_G11_IDS(NOP), INTEL_ATS_M75_IDS(NOP), 0 }; 267 static const u16 dg2_g12_ids[] = { INTEL_DG2_G12_IDS(NOP), 0 }; 268 269 #define DG2_FEATURES \ 270 DGFX_FEATURES, \ 271 PLATFORM(DG2), \ 272 .has_flat_ccs = 1, \ 273 .has_gsc_nvm = 1, \ 274 .has_heci_gscfi = 1, \ 275 .subplatforms = (const struct xe_subplatform_desc[]) { \ 276 { XE_SUBPLATFORM_DG2_G10, "G10", dg2_g10_ids }, \ 277 { XE_SUBPLATFORM_DG2_G11, "G11", dg2_g11_ids }, \ 278 { XE_SUBPLATFORM_DG2_G12, "G12", dg2_g12_ids }, \ 279 { } \ 280 }, \ 281 .va_bits = 48, \ 282 .vm_max_level = 3, \ 283 .vram_flags = XE_VRAM_FLAGS_NEED64K 284 285 static const struct xe_device_desc ats_m_desc = { 286 .pre_gmdid_graphics_ip = &graphics_ip_xehpg, 287 .pre_gmdid_media_ip = &media_ip_xehpm, 288 .dma_mask_size = 46, 289 .max_gt_per_tile = 1, 290 .require_force_probe = true, 291 292 DG2_FEATURES, 293 .has_display = false, 294 .has_sriov = true, 295 }; 296 297 static const struct xe_device_desc dg2_desc = { 298 .pre_gmdid_graphics_ip = &graphics_ip_xehpg, 299 .pre_gmdid_media_ip = &media_ip_xehpm, 300 .dma_mask_size = 46, 301 .max_gt_per_tile = 1, 302 .require_force_probe = true, 303 304 DG2_FEATURES, 305 .has_display = true, 306 .has_fan_control = true, 307 .has_mbx_power_limits = false, 308 }; 309 310 static const __maybe_unused struct xe_device_desc pvc_desc = { 311 .pre_gmdid_graphics_ip = &graphics_ip_xehpc, 312 DGFX_FEATURES, 313 PLATFORM(PVC), 314 .dma_mask_size = 52, 315 .has_display = false, 316 .has_gsc_nvm = 1, 317 .has_heci_gscfi = 1, 318 .max_gt_per_tile = 1, 319 .max_remote_tiles = 1, 320 .require_force_probe = true, 321 .va_bits = 57, 322 .vm_max_level = 4, 323 .vram_flags = XE_VRAM_FLAGS_NEED64K, 324 .has_mbx_power_limits = false, 325 }; 326 327 static const struct xe_device_desc mtl_desc = { 328 /* .graphics and .media determined via GMD_ID */ 329 .require_force_probe = true, 330 PLATFORM(METEORLAKE), 331 .dma_mask_size = 46, 332 .has_display = true, 333 .has_pxp = true, 334 .max_gt_per_tile = 2, 335 .va_bits = 48, 336 .vm_max_level = 4, 337 }; 338 339 static const struct xe_device_desc lnl_desc = { 340 PLATFORM(LUNARLAKE), 341 .dma_mask_size = 46, 342 .has_display = true, 343 .has_flat_ccs = 1, 344 .has_pxp = true, 345 .has_mem_copy_instr = true, 346 .max_gt_per_tile = 2, 347 .needs_scratch = true, 348 .va_bits = 48, 349 .vm_max_level = 4, 350 }; 351 352 static const u16 bmg_g21_ids[] = { INTEL_BMG_G21_IDS(NOP), 0 }; 353 354 static const struct xe_device_desc bmg_desc = { 355 DGFX_FEATURES, 356 PLATFORM(BATTLEMAGE), 357 .dma_mask_size = 46, 358 .has_display = true, 359 .has_fan_control = true, 360 .has_flat_ccs = 1, 361 .has_mbx_power_limits = true, 362 .has_gsc_nvm = 1, 363 .has_heci_cscfi = 1, 364 .has_late_bind = true, 365 .has_sriov = true, 366 .has_mem_copy_instr = true, 367 .max_gt_per_tile = 2, 368 .needs_scratch = true, 369 .subplatforms = (const struct xe_subplatform_desc[]) { 370 { XE_SUBPLATFORM_BATTLEMAGE_G21, "G21", bmg_g21_ids }, 371 { } 372 }, 373 .va_bits = 48, 374 .vm_max_level = 4, 375 }; 376 377 static const struct xe_device_desc ptl_desc = { 378 PLATFORM(PANTHERLAKE), 379 .dma_mask_size = 46, 380 .has_display = true, 381 .has_flat_ccs = 1, 382 .has_sriov = true, 383 .has_mem_copy_instr = true, 384 .max_gt_per_tile = 2, 385 .needs_scratch = true, 386 .needs_shared_vf_gt_wq = true, 387 .va_bits = 48, 388 .vm_max_level = 4, 389 }; 390 391 static const struct xe_device_desc nvls_desc = { 392 PLATFORM(NOVALAKE_S), 393 .dma_mask_size = 46, 394 .has_display = true, 395 .has_flat_ccs = 1, 396 .has_mem_copy_instr = true, 397 .max_gt_per_tile = 2, 398 .require_force_probe = true, 399 .va_bits = 48, 400 .vm_max_level = 4, 401 }; 402 403 static const struct xe_device_desc cri_desc = { 404 DGFX_FEATURES, 405 PLATFORM(CRESCENTISLAND), 406 .dma_mask_size = 52, 407 .has_display = false, 408 .has_flat_ccs = false, 409 .has_mbx_power_limits = true, 410 .has_sriov = true, 411 .max_gt_per_tile = 2, 412 .require_force_probe = true, 413 .va_bits = 57, 414 .vm_max_level = 4, 415 }; 416 417 #undef PLATFORM 418 __diag_pop(); 419 420 /* 421 * Make sure any device matches here are from most specific to most 422 * general. For example, since the Quanta match is based on the subsystem 423 * and subvendor IDs, we need it to come before the more general IVB 424 * PCI ID matches, otherwise we'll use the wrong info struct above. 425 */ 426 static const struct pci_device_id pciidlist[] = { 427 INTEL_TGL_IDS(INTEL_VGA_DEVICE, &tgl_desc), 428 INTEL_RKL_IDS(INTEL_VGA_DEVICE, &rkl_desc), 429 INTEL_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc), 430 INTEL_ADLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 431 INTEL_ADLN_IDS(INTEL_VGA_DEVICE, &adl_n_desc), 432 INTEL_RPLU_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 433 INTEL_RPLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 434 INTEL_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc), 435 INTEL_DG1_IDS(INTEL_VGA_DEVICE, &dg1_desc), 436 INTEL_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_desc), 437 INTEL_ARL_IDS(INTEL_VGA_DEVICE, &mtl_desc), 438 INTEL_DG2_IDS(INTEL_VGA_DEVICE, &dg2_desc), 439 INTEL_MTL_IDS(INTEL_VGA_DEVICE, &mtl_desc), 440 INTEL_LNL_IDS(INTEL_VGA_DEVICE, &lnl_desc), 441 INTEL_BMG_IDS(INTEL_VGA_DEVICE, &bmg_desc), 442 INTEL_PTL_IDS(INTEL_VGA_DEVICE, &ptl_desc), 443 INTEL_NVLS_IDS(INTEL_VGA_DEVICE, &nvls_desc), 444 INTEL_CRI_IDS(INTEL_PCI_DEVICE, &cri_desc), 445 { } 446 }; 447 MODULE_DEVICE_TABLE(pci, pciidlist); 448 449 /* is device_id present in comma separated list of ids */ 450 static bool device_id_in_list(u16 device_id, const char *devices, bool negative) 451 { 452 char *s, *p, *tok; 453 bool ret; 454 455 if (!devices || !*devices) 456 return false; 457 458 /* match everything */ 459 if (negative && strcmp(devices, "!*") == 0) 460 return true; 461 if (!negative && strcmp(devices, "*") == 0) 462 return true; 463 464 s = kstrdup(devices, GFP_KERNEL); 465 if (!s) 466 return false; 467 468 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) { 469 u16 val; 470 471 if (negative && tok[0] == '!') 472 tok++; 473 else if ((negative && tok[0] != '!') || 474 (!negative && tok[0] == '!')) 475 continue; 476 477 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) { 478 ret = true; 479 break; 480 } 481 } 482 483 kfree(s); 484 485 return ret; 486 } 487 488 static bool id_forced(u16 device_id) 489 { 490 return device_id_in_list(device_id, xe_modparam.force_probe, false); 491 } 492 493 static bool id_blocked(u16 device_id) 494 { 495 return device_id_in_list(device_id, xe_modparam.force_probe, true); 496 } 497 498 static const struct xe_subplatform_desc * 499 find_subplatform(const struct xe_device *xe, const struct xe_device_desc *desc) 500 { 501 const struct xe_subplatform_desc *sp; 502 const u16 *id; 503 504 for (sp = desc->subplatforms; sp && sp->subplatform; sp++) 505 for (id = sp->pciidlist; *id; id++) 506 if (*id == xe->info.devid) 507 return sp; 508 509 return NULL; 510 } 511 512 enum xe_gmdid_type { 513 GMDID_GRAPHICS, 514 GMDID_MEDIA 515 }; 516 517 static int read_gmdid(struct xe_device *xe, enum xe_gmdid_type type, u32 *ver, u32 *revid) 518 { 519 struct xe_mmio *mmio = xe_root_tile_mmio(xe); 520 struct xe_reg gmdid_reg = GMD_ID; 521 u32 val; 522 523 KUNIT_STATIC_STUB_REDIRECT(read_gmdid, xe, type, ver, revid); 524 525 if (IS_SRIOV_VF(xe)) { 526 /* 527 * To get the value of the GMDID register, VFs must obtain it 528 * from the GuC using MMIO communication. 529 * 530 * Note that at this point the GTs are not initialized and only 531 * tile-level access to MMIO registers is possible. To use our 532 * existing GuC communication functions we must create a dummy 533 * GT structure and perform at least basic xe_gt and xe_guc 534 * initialization. 535 */ 536 struct xe_gt *gt __free(kfree) = NULL; 537 int err; 538 539 gt = kzalloc(sizeof(*gt), GFP_KERNEL); 540 if (!gt) 541 return -ENOMEM; 542 543 gt->tile = &xe->tiles[0]; 544 if (type == GMDID_MEDIA) { 545 gt->info.id = 1; 546 gt->info.type = XE_GT_TYPE_MEDIA; 547 } else { 548 gt->info.id = 0; 549 gt->info.type = XE_GT_TYPE_MAIN; 550 } 551 552 xe_gt_mmio_init(gt); 553 xe_guc_comm_init_early(>->uc.guc); 554 555 err = xe_gt_sriov_vf_bootstrap(gt); 556 if (err) 557 return err; 558 559 val = xe_gt_sriov_vf_gmdid(gt); 560 } else { 561 /* 562 * GMD_ID is a GT register, but at this point in the driver 563 * init we haven't fully initialized the GT yet so we need to 564 * read the register with the tile's MMIO accessor. That means 565 * we need to apply the GSI offset manually since it won't get 566 * automatically added as it would if we were using a GT mmio 567 * accessor. 568 */ 569 if (type == GMDID_MEDIA) 570 gmdid_reg.addr += MEDIA_GT_GSI_OFFSET; 571 572 val = xe_mmio_read32(mmio, gmdid_reg); 573 } 574 575 *ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val) * 100 + REG_FIELD_GET(GMD_ID_RELEASE_MASK, val); 576 *revid = REG_FIELD_GET(GMD_ID_REVID, val); 577 578 return 0; 579 } 580 581 static const struct xe_ip *find_graphics_ip(unsigned int verx100) 582 { 583 KUNIT_STATIC_STUB_REDIRECT(find_graphics_ip, verx100); 584 585 for (int i = 0; i < ARRAY_SIZE(graphics_ips); i++) 586 if (graphics_ips[i].verx100 == verx100) 587 return &graphics_ips[i]; 588 return NULL; 589 } 590 591 static const struct xe_ip *find_media_ip(unsigned int verx100) 592 { 593 KUNIT_STATIC_STUB_REDIRECT(find_media_ip, verx100); 594 595 for (int i = 0; i < ARRAY_SIZE(media_ips); i++) 596 if (media_ips[i].verx100 == verx100) 597 return &media_ips[i]; 598 return NULL; 599 } 600 601 /* 602 * Read IP version from hardware and select graphics/media IP descriptors 603 * based on the result. 604 */ 605 static int handle_gmdid(struct xe_device *xe, 606 const struct xe_ip **graphics_ip, 607 const struct xe_ip **media_ip, 608 u32 *graphics_revid, 609 u32 *media_revid) 610 { 611 u32 ver; 612 int ret; 613 614 *graphics_ip = NULL; 615 *media_ip = NULL; 616 617 ret = read_gmdid(xe, GMDID_GRAPHICS, &ver, graphics_revid); 618 if (ret) 619 return ret; 620 621 *graphics_ip = find_graphics_ip(ver); 622 if (!*graphics_ip) { 623 drm_err(&xe->drm, "Hardware reports unknown graphics version %u.%02u\n", 624 ver / 100, ver % 100); 625 } 626 627 ret = read_gmdid(xe, GMDID_MEDIA, &ver, media_revid); 628 if (ret) 629 return ret; 630 631 /* Media may legitimately be fused off / not present */ 632 if (ver == 0) 633 return 0; 634 635 *media_ip = find_media_ip(ver); 636 if (!*media_ip) { 637 drm_err(&xe->drm, "Hardware reports unknown media version %u.%02u\n", 638 ver / 100, ver % 100); 639 } 640 641 return 0; 642 } 643 644 /* 645 * Initialize device info content that only depends on static driver_data 646 * passed to the driver at probe time from PCI ID table. 647 */ 648 static int xe_info_init_early(struct xe_device *xe, 649 const struct xe_device_desc *desc, 650 const struct xe_subplatform_desc *subplatform_desc) 651 { 652 int err; 653 654 xe->info.platform_name = desc->platform_name; 655 xe->info.platform = desc->platform; 656 xe->info.subplatform = subplatform_desc ? 657 subplatform_desc->subplatform : XE_SUBPLATFORM_NONE; 658 659 xe->info.dma_mask_size = desc->dma_mask_size; 660 xe->info.va_bits = desc->va_bits; 661 xe->info.vm_max_level = desc->vm_max_level; 662 xe->info.vram_flags = desc->vram_flags; 663 664 xe->info.is_dgfx = desc->is_dgfx; 665 xe->info.has_fan_control = desc->has_fan_control; 666 /* runtime fusing may force flat_ccs to disabled later */ 667 xe->info.has_flat_ccs = desc->has_flat_ccs; 668 xe->info.has_mbx_power_limits = desc->has_mbx_power_limits; 669 xe->info.has_gsc_nvm = desc->has_gsc_nvm; 670 xe->info.has_heci_gscfi = desc->has_heci_gscfi; 671 xe->info.has_heci_cscfi = desc->has_heci_cscfi; 672 xe->info.has_late_bind = desc->has_late_bind; 673 xe->info.has_llc = desc->has_llc; 674 xe->info.has_pxp = desc->has_pxp; 675 xe->info.has_sriov = xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev)) && 676 desc->has_sriov; 677 xe->info.has_mem_copy_instr = desc->has_mem_copy_instr; 678 xe->info.skip_guc_pc = desc->skip_guc_pc; 679 xe->info.skip_mtcfg = desc->skip_mtcfg; 680 xe->info.skip_pcode = desc->skip_pcode; 681 xe->info.needs_scratch = desc->needs_scratch; 682 xe->info.needs_shared_vf_gt_wq = desc->needs_shared_vf_gt_wq; 683 684 xe->info.probe_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) && 685 xe_modparam.probe_display && 686 desc->has_display; 687 688 xe_assert(xe, desc->max_gt_per_tile > 0); 689 xe_assert(xe, desc->max_gt_per_tile <= XE_MAX_GT_PER_TILE); 690 xe->info.max_gt_per_tile = desc->max_gt_per_tile; 691 xe->info.tile_count = 1 + desc->max_remote_tiles; 692 693 err = xe_tile_init_early(xe_device_get_root_tile(xe), xe, 0); 694 if (err) 695 return err; 696 697 return 0; 698 } 699 700 /* 701 * Possibly override number of tile based on configuration register. 702 */ 703 static void xe_info_probe_tile_count(struct xe_device *xe) 704 { 705 struct xe_mmio *mmio; 706 u8 tile_count; 707 u32 mtcfg; 708 709 KUNIT_STATIC_STUB_REDIRECT(xe_info_probe_tile_count, xe); 710 711 /* 712 * Probe for tile count only for platforms that support multiple 713 * tiles. 714 */ 715 if (xe->info.tile_count == 1) 716 return; 717 718 if (xe->info.skip_mtcfg) 719 return; 720 721 mmio = xe_root_tile_mmio(xe); 722 723 /* 724 * Although the per-tile mmio regs are not yet initialized, this 725 * is fine as it's going to the root tile's mmio, that's 726 * guaranteed to be initialized earlier in xe_mmio_probe_early() 727 */ 728 mtcfg = xe_mmio_read32(mmio, XEHP_MTCFG_ADDR); 729 tile_count = REG_FIELD_GET(TILE_COUNT, mtcfg) + 1; 730 731 if (tile_count < xe->info.tile_count) { 732 drm_info(&xe->drm, "tile_count: %d, reduced_tile_count %d\n", 733 xe->info.tile_count, tile_count); 734 xe->info.tile_count = tile_count; 735 } 736 } 737 738 static struct xe_gt *alloc_primary_gt(struct xe_tile *tile, 739 const struct xe_graphics_desc *graphics_desc, 740 const struct xe_media_desc *media_desc) 741 { 742 struct xe_device *xe = tile_to_xe(tile); 743 struct xe_gt *gt; 744 745 if (!xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev))) { 746 xe_info(xe, "Primary GT disabled via configfs\n"); 747 return NULL; 748 } 749 750 gt = xe_gt_alloc(tile); 751 if (IS_ERR(gt)) 752 return gt; 753 754 gt->info.type = XE_GT_TYPE_MAIN; 755 gt->info.id = tile->id * xe->info.max_gt_per_tile; 756 gt->info.has_indirect_ring_state = graphics_desc->has_indirect_ring_state; 757 gt->info.engine_mask = graphics_desc->hw_engine_mask; 758 759 /* 760 * Before media version 13, the media IP was part of the primary GT 761 * so we need to add the media engines to the primary GT's engine list. 762 */ 763 if (MEDIA_VER(xe) < 13 && media_desc) 764 gt->info.engine_mask |= media_desc->hw_engine_mask; 765 766 return gt; 767 } 768 769 static struct xe_gt *alloc_media_gt(struct xe_tile *tile, 770 const struct xe_media_desc *media_desc) 771 { 772 struct xe_device *xe = tile_to_xe(tile); 773 struct xe_gt *gt; 774 775 if (!xe_configfs_media_gt_allowed(to_pci_dev(xe->drm.dev))) { 776 xe_info(xe, "Media GT disabled via configfs\n"); 777 return NULL; 778 } 779 780 if (MEDIA_VER(xe) < 13 || !media_desc) 781 return NULL; 782 783 gt = xe_gt_alloc(tile); 784 if (IS_ERR(gt)) 785 return gt; 786 787 gt->info.type = XE_GT_TYPE_MEDIA; 788 gt->info.id = tile->id * xe->info.max_gt_per_tile + 1; 789 gt->info.has_indirect_ring_state = media_desc->has_indirect_ring_state; 790 gt->info.engine_mask = media_desc->hw_engine_mask; 791 792 return gt; 793 } 794 795 /* 796 * Initialize device info content that does require knowledge about 797 * graphics / media IP version. 798 * Make sure that GT / tile structures allocated by the driver match the data 799 * present in device info. 800 */ 801 static int xe_info_init(struct xe_device *xe, 802 const struct xe_device_desc *desc) 803 { 804 u32 graphics_gmdid_revid = 0, media_gmdid_revid = 0; 805 const struct xe_ip *graphics_ip; 806 const struct xe_ip *media_ip; 807 const struct xe_graphics_desc *graphics_desc; 808 const struct xe_media_desc *media_desc; 809 struct xe_tile *tile; 810 struct xe_gt *gt; 811 int ret; 812 u8 id; 813 814 /* 815 * If this platform supports GMD_ID, we'll detect the proper IP 816 * descriptor to use from hardware registers. 817 * desc->pre_gmdid_graphics_ip will only ever be set at this point for 818 * platforms before GMD_ID. In that case the IP descriptions and 819 * versions are simply derived from that. 820 */ 821 if (desc->pre_gmdid_graphics_ip) { 822 graphics_ip = desc->pre_gmdid_graphics_ip; 823 media_ip = desc->pre_gmdid_media_ip; 824 xe->info.step = xe_step_pre_gmdid_get(xe); 825 } else { 826 xe_assert(xe, !desc->pre_gmdid_media_ip); 827 ret = handle_gmdid(xe, &graphics_ip, &media_ip, 828 &graphics_gmdid_revid, &media_gmdid_revid); 829 if (ret) 830 return ret; 831 832 xe->info.step = xe_step_gmdid_get(xe, 833 graphics_gmdid_revid, 834 media_gmdid_revid); 835 } 836 837 /* 838 * If we couldn't detect the graphics IP, that's considered a fatal 839 * error and we should abort driver load. Failing to detect media 840 * IP is non-fatal; we'll just proceed without enabling media support. 841 */ 842 if (!graphics_ip) 843 return -ENODEV; 844 845 xe->info.graphics_verx100 = graphics_ip->verx100; 846 xe->info.graphics_name = graphics_ip->name; 847 graphics_desc = graphics_ip->desc; 848 849 if (media_ip) { 850 xe->info.media_verx100 = media_ip->verx100; 851 xe->info.media_name = media_ip->name; 852 media_desc = media_ip->desc; 853 } else { 854 xe->info.media_name = "none"; 855 media_desc = NULL; 856 } 857 858 xe->info.has_asid = graphics_desc->has_asid; 859 xe->info.has_atomic_enable_pte_bit = graphics_desc->has_atomic_enable_pte_bit; 860 if (xe->info.platform != XE_PVC) 861 xe->info.has_device_atomics_on_smem = 1; 862 863 xe->info.has_range_tlb_inval = graphics_desc->has_range_tlb_inval; 864 xe->info.has_usm = graphics_desc->has_usm; 865 xe->info.has_64bit_timestamp = graphics_desc->has_64bit_timestamp; 866 867 xe_info_probe_tile_count(xe); 868 869 for_each_remote_tile(tile, xe, id) { 870 int err; 871 872 err = xe_tile_init_early(tile, xe, id); 873 if (err) 874 return err; 875 } 876 877 /* Allocate any GT and VRAM structures necessary for the platform. */ 878 for_each_tile(tile, xe, id) { 879 int err; 880 881 err = xe_tile_alloc_vram(tile); 882 if (err) 883 return err; 884 885 tile->primary_gt = alloc_primary_gt(tile, graphics_desc, media_desc); 886 if (IS_ERR(tile->primary_gt)) 887 return PTR_ERR(tile->primary_gt); 888 889 /* 890 * It's not currently possible to probe a device with the 891 * primary GT disabled. With some work, this may be future in 892 * the possible for igpu platforms (although probably not for 893 * dgpu's since access to the primary GT's BCS engines is 894 * required for VRAM management). 895 */ 896 if (!tile->primary_gt) { 897 drm_err(&xe->drm, "Cannot probe device with without a primary GT\n"); 898 return -ENODEV; 899 } 900 901 tile->media_gt = alloc_media_gt(tile, media_desc); 902 if (IS_ERR(tile->media_gt)) 903 return PTR_ERR(tile->media_gt); 904 } 905 906 /* 907 * Now that we have tiles and GTs defined, let's loop over valid GTs 908 * in order to define gt_count. 909 */ 910 for_each_gt(gt, xe, id) 911 xe->info.gt_count++; 912 913 return 0; 914 } 915 916 static void xe_pci_remove(struct pci_dev *pdev) 917 { 918 struct xe_device *xe = pdev_to_xe_device(pdev); 919 920 if (IS_SRIOV_PF(xe)) 921 xe_pci_sriov_configure(pdev, 0); 922 923 if (xe_survivability_mode_is_boot_enabled(xe)) 924 return; 925 926 xe_device_remove(xe); 927 xe_pm_fini(xe); 928 } 929 930 /* 931 * Probe the PCI device, initialize various parts of the driver. 932 * 933 * Fault injection is used to test the error paths of some initialization 934 * functions called either directly from xe_pci_probe() or indirectly for 935 * example through xe_device_probe(). Those functions use the kernel fault 936 * injection capabilities infrastructure, see 937 * Documentation/fault-injection/fault-injection.rst for details. The macro 938 * ALLOW_ERROR_INJECTION() is used to conditionally skip function execution 939 * at runtime and use a provided return value. The first requirement for 940 * error injectable functions is proper handling of the error code by the 941 * caller for recovery, which is always the case here. The second 942 * requirement is that no state is changed before the first error return. 943 * It is not strictly fulfilled for all initialization functions using the 944 * ALLOW_ERROR_INJECTION() macro but this is acceptable because for those 945 * error cases at probe time, the error code is simply propagated up by the 946 * caller. Therefore there is no consequence on those specific callers when 947 * function error injection skips the whole function. 948 */ 949 static int xe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 950 { 951 const struct xe_device_desc *desc = (const void *)ent->driver_data; 952 const struct xe_subplatform_desc *subplatform_desc; 953 struct xe_device *xe; 954 int err; 955 956 xe_configfs_check_device(pdev); 957 958 if (desc->require_force_probe && !id_forced(pdev->device)) { 959 dev_info(&pdev->dev, 960 "Your graphics device %04x is not officially supported\n" 961 "by xe driver in this kernel version. To force Xe probe,\n" 962 "use xe.force_probe='%04x' and i915.force_probe='!%04x'\n" 963 "module parameters or CONFIG_DRM_XE_FORCE_PROBE='%04x' and\n" 964 "CONFIG_DRM_I915_FORCE_PROBE='!%04x' configuration options.\n", 965 pdev->device, pdev->device, pdev->device, 966 pdev->device, pdev->device); 967 return -ENODEV; 968 } 969 970 if (id_blocked(pdev->device)) { 971 dev_info(&pdev->dev, "Probe blocked for device [%04x:%04x].\n", 972 pdev->vendor, pdev->device); 973 return -ENODEV; 974 } 975 976 if (xe_display_driver_probe_defer(pdev)) 977 return -EPROBE_DEFER; 978 979 err = pcim_enable_device(pdev); 980 if (err) 981 return err; 982 983 xe = xe_device_create(pdev, ent); 984 if (IS_ERR(xe)) 985 return PTR_ERR(xe); 986 987 pci_set_drvdata(pdev, &xe->drm); 988 989 xe_pm_assert_unbounded_bridge(xe); 990 subplatform_desc = find_subplatform(xe, desc); 991 992 pci_set_master(pdev); 993 994 err = xe_info_init_early(xe, desc, subplatform_desc); 995 if (err) 996 return err; 997 998 xe_vram_resize_bar(xe); 999 1000 err = xe_device_probe_early(xe); 1001 /* 1002 * In Boot Survivability mode, no drm card is exposed and driver 1003 * is loaded with bare minimum to allow for firmware to be 1004 * flashed through mei. Return success, if survivability mode 1005 * is enabled due to pcode failure or configfs being set 1006 */ 1007 if (xe_survivability_mode_is_boot_enabled(xe)) 1008 return 0; 1009 1010 if (err) 1011 return err; 1012 1013 err = xe_info_init(xe, desc); 1014 if (err) 1015 return err; 1016 1017 err = xe_display_probe(xe); 1018 if (err) 1019 return err; 1020 1021 drm_dbg(&xe->drm, "%s %s %04x:%04x dgfx:%d gfx:%s (%d.%02d) media:%s (%d.%02d) display:%s dma_m_s:%d tc:%d gscfi:%d cscfi:%d", 1022 desc->platform_name, 1023 subplatform_desc ? subplatform_desc->name : "", 1024 xe->info.devid, xe->info.revid, 1025 xe->info.is_dgfx, 1026 xe->info.graphics_name, 1027 xe->info.graphics_verx100 / 100, 1028 xe->info.graphics_verx100 % 100, 1029 xe->info.media_name, 1030 xe->info.media_verx100 / 100, 1031 xe->info.media_verx100 % 100, 1032 str_yes_no(xe->info.probe_display), 1033 xe->info.dma_mask_size, xe->info.tile_count, 1034 xe->info.has_heci_gscfi, xe->info.has_heci_cscfi); 1035 1036 drm_dbg(&xe->drm, "Stepping = (G:%s, M:%s, B:%s)\n", 1037 xe_step_name(xe->info.step.graphics), 1038 xe_step_name(xe->info.step.media), 1039 xe_step_name(xe->info.step.basedie)); 1040 1041 drm_dbg(&xe->drm, "SR-IOV support: %s (mode: %s)\n", 1042 str_yes_no(xe_device_has_sriov(xe)), 1043 xe_sriov_mode_to_string(xe_device_sriov_mode(xe))); 1044 1045 err = xe_pm_init_early(xe); 1046 if (err) 1047 return err; 1048 1049 err = xe_device_probe(xe); 1050 if (err) 1051 return err; 1052 1053 err = xe_pm_init(xe); 1054 if (err) 1055 goto err_driver_cleanup; 1056 1057 drm_dbg(&xe->drm, "d3cold: capable=%s\n", 1058 str_yes_no(xe->d3cold.capable)); 1059 1060 return 0; 1061 1062 err_driver_cleanup: 1063 xe_pci_remove(pdev); 1064 return err; 1065 } 1066 1067 static void xe_pci_shutdown(struct pci_dev *pdev) 1068 { 1069 xe_device_shutdown(pdev_to_xe_device(pdev)); 1070 } 1071 1072 #ifdef CONFIG_PM_SLEEP 1073 static void d3cold_toggle(struct pci_dev *pdev, enum toggle_d3cold toggle) 1074 { 1075 struct xe_device *xe = pdev_to_xe_device(pdev); 1076 struct pci_dev *root_pdev; 1077 1078 if (!xe->d3cold.capable) 1079 return; 1080 1081 root_pdev = pcie_find_root_port(pdev); 1082 if (!root_pdev) 1083 return; 1084 1085 switch (toggle) { 1086 case D3COLD_DISABLE: 1087 pci_d3cold_disable(root_pdev); 1088 break; 1089 case D3COLD_ENABLE: 1090 pci_d3cold_enable(root_pdev); 1091 break; 1092 } 1093 } 1094 1095 static int xe_pci_suspend(struct device *dev) 1096 { 1097 struct pci_dev *pdev = to_pci_dev(dev); 1098 struct xe_device *xe = pdev_to_xe_device(pdev); 1099 int err; 1100 1101 if (xe_survivability_mode_is_boot_enabled(xe)) 1102 return -EBUSY; 1103 1104 err = xe_pm_suspend(xe); 1105 if (err) 1106 return err; 1107 1108 /* 1109 * Enabling D3Cold is needed for S2Idle/S0ix. 1110 * It is save to allow here since xe_pm_suspend has evicted 1111 * the local memory and the direct complete optimization is disabled. 1112 */ 1113 d3cold_toggle(pdev, D3COLD_ENABLE); 1114 1115 pci_save_state(pdev); 1116 pci_disable_device(pdev); 1117 pci_set_power_state(pdev, PCI_D3cold); 1118 1119 return 0; 1120 } 1121 1122 static int xe_pci_resume(struct device *dev) 1123 { 1124 struct pci_dev *pdev = to_pci_dev(dev); 1125 int err; 1126 1127 /* Give back the D3Cold decision to the runtime P M*/ 1128 d3cold_toggle(pdev, D3COLD_DISABLE); 1129 1130 err = pci_set_power_state(pdev, PCI_D0); 1131 if (err) 1132 return err; 1133 1134 pci_restore_state(pdev); 1135 1136 err = pci_enable_device(pdev); 1137 if (err) 1138 return err; 1139 1140 pci_set_master(pdev); 1141 1142 err = xe_pm_resume(pdev_to_xe_device(pdev)); 1143 if (err) 1144 return err; 1145 1146 return 0; 1147 } 1148 1149 static int xe_pci_runtime_suspend(struct device *dev) 1150 { 1151 struct pci_dev *pdev = to_pci_dev(dev); 1152 struct xe_device *xe = pdev_to_xe_device(pdev); 1153 int err; 1154 1155 err = xe_pm_runtime_suspend(xe); 1156 if (err) 1157 return err; 1158 1159 pci_save_state(pdev); 1160 1161 if (xe->d3cold.allowed) { 1162 d3cold_toggle(pdev, D3COLD_ENABLE); 1163 pci_disable_device(pdev); 1164 pci_ignore_hotplug(pdev); 1165 pci_set_power_state(pdev, PCI_D3cold); 1166 } else { 1167 d3cold_toggle(pdev, D3COLD_DISABLE); 1168 pci_set_power_state(pdev, PCI_D3hot); 1169 } 1170 1171 return 0; 1172 } 1173 1174 static int xe_pci_runtime_resume(struct device *dev) 1175 { 1176 struct pci_dev *pdev = to_pci_dev(dev); 1177 struct xe_device *xe = pdev_to_xe_device(pdev); 1178 int err; 1179 1180 err = pci_set_power_state(pdev, PCI_D0); 1181 if (err) 1182 return err; 1183 1184 pci_restore_state(pdev); 1185 1186 if (xe->d3cold.allowed) { 1187 err = pci_enable_device(pdev); 1188 if (err) 1189 return err; 1190 1191 pci_set_master(pdev); 1192 } 1193 1194 return xe_pm_runtime_resume(xe); 1195 } 1196 1197 static int xe_pci_runtime_idle(struct device *dev) 1198 { 1199 struct pci_dev *pdev = to_pci_dev(dev); 1200 struct xe_device *xe = pdev_to_xe_device(pdev); 1201 1202 xe_pm_d3cold_allowed_toggle(xe); 1203 1204 return 0; 1205 } 1206 1207 static const struct dev_pm_ops xe_pm_ops = { 1208 SET_SYSTEM_SLEEP_PM_OPS(xe_pci_suspend, xe_pci_resume) 1209 SET_RUNTIME_PM_OPS(xe_pci_runtime_suspend, xe_pci_runtime_resume, xe_pci_runtime_idle) 1210 }; 1211 #endif 1212 1213 static struct pci_driver xe_pci_driver = { 1214 .name = DRIVER_NAME, 1215 .id_table = pciidlist, 1216 .probe = xe_pci_probe, 1217 .remove = xe_pci_remove, 1218 .shutdown = xe_pci_shutdown, 1219 .sriov_configure = xe_pci_sriov_configure, 1220 #ifdef CONFIG_PM_SLEEP 1221 .driver.pm = &xe_pm_ops, 1222 #endif 1223 }; 1224 1225 int xe_register_pci_driver(void) 1226 { 1227 return pci_register_driver(&xe_pci_driver); 1228 } 1229 1230 void xe_unregister_pci_driver(void) 1231 { 1232 pci_unregister_driver(&xe_pci_driver); 1233 } 1234 1235 #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST) 1236 #include "tests/xe_pci.c" 1237 #endif 1238