1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 #include "xe_pci.h" 7 8 #include <kunit/static_stub.h> 9 #include <linux/device/driver.h> 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/pm_runtime.h> 13 14 #include <drm/drm_color_mgmt.h> 15 #include <drm/drm_drv.h> 16 #include <drm/intel/pciids.h> 17 18 #include "display/xe_display.h" 19 #include "regs/xe_gt_regs.h" 20 #include "regs/xe_regs.h" 21 #include "xe_configfs.h" 22 #include "xe_device.h" 23 #include "xe_drv.h" 24 #include "xe_gt.h" 25 #include "xe_gt_sriov_vf.h" 26 #include "xe_guc.h" 27 #include "xe_macros.h" 28 #include "xe_mmio.h" 29 #include "xe_module.h" 30 #include "xe_pci_sriov.h" 31 #include "xe_pci_types.h" 32 #include "xe_pm.h" 33 #include "xe_printk.h" 34 #include "xe_sriov.h" 35 #include "xe_step.h" 36 #include "xe_survivability_mode.h" 37 #include "xe_tile.h" 38 39 enum toggle_d3cold { 40 D3COLD_DISABLE, 41 D3COLD_ENABLE, 42 }; 43 44 __diag_push(); 45 __diag_ignore_all("-Woverride-init", "Allow field overrides in table"); 46 47 #define PLATFORM(x) \ 48 .platform = XE_##x, \ 49 .platform_name = #x 50 51 #define NOP(x) x 52 53 static const struct xe_graphics_desc graphics_xelp = { 54 .hw_engine_mask = BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0), 55 }; 56 57 #define XE_HP_FEATURES \ 58 .has_range_tlb_inval = true 59 60 static const struct xe_graphics_desc graphics_xehpg = { 61 .hw_engine_mask = 62 BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) | 63 BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) | 64 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3), 65 66 XE_HP_FEATURES, 67 }; 68 69 static const struct xe_graphics_desc graphics_xehpc = { 70 .hw_engine_mask = 71 BIT(XE_HW_ENGINE_BCS0) | BIT(XE_HW_ENGINE_BCS1) | 72 BIT(XE_HW_ENGINE_BCS2) | BIT(XE_HW_ENGINE_BCS3) | 73 BIT(XE_HW_ENGINE_BCS4) | BIT(XE_HW_ENGINE_BCS5) | 74 BIT(XE_HW_ENGINE_BCS6) | BIT(XE_HW_ENGINE_BCS7) | 75 BIT(XE_HW_ENGINE_BCS8) | 76 BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) | 77 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3), 78 79 XE_HP_FEATURES, 80 81 .has_asid = 1, 82 .has_atomic_enable_pte_bit = 1, 83 .has_usm = 1, 84 }; 85 86 static const struct xe_graphics_desc graphics_xelpg = { 87 .hw_engine_mask = 88 BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) | 89 BIT(XE_HW_ENGINE_CCS0), 90 91 XE_HP_FEATURES, 92 }; 93 94 #define XE2_GFX_FEATURES \ 95 .has_asid = 1, \ 96 .has_atomic_enable_pte_bit = 1, \ 97 .has_range_tlb_inval = 1, \ 98 .has_usm = 1, \ 99 .has_64bit_timestamp = 1, \ 100 .hw_engine_mask = \ 101 BIT(XE_HW_ENGINE_RCS0) | \ 102 BIT(XE_HW_ENGINE_BCS8) | BIT(XE_HW_ENGINE_BCS0) | \ 103 GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0) 104 105 static const struct xe_graphics_desc graphics_xe2 = { 106 XE2_GFX_FEATURES, 107 }; 108 109 static const struct xe_graphics_desc graphics_xe3p_xpc = { 110 XE2_GFX_FEATURES, 111 .hw_engine_mask = 112 GENMASK(XE_HW_ENGINE_BCS8, XE_HW_ENGINE_BCS1) | 113 GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0), 114 }; 115 116 static const struct xe_media_desc media_xem = { 117 .hw_engine_mask = 118 GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) | 119 GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0), 120 }; 121 122 static const struct xe_media_desc media_xelpmp = { 123 .hw_engine_mask = 124 GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) | 125 GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0) | 126 BIT(XE_HW_ENGINE_GSCCS0) 127 }; 128 129 /* Pre-GMDID Graphics IPs */ 130 static const struct xe_ip graphics_ip_xelp = { 1200, "Xe_LP", &graphics_xelp }; 131 static const struct xe_ip graphics_ip_xelpp = { 1210, "Xe_LP+", &graphics_xelp }; 132 static const struct xe_ip graphics_ip_xehpg = { 1255, "Xe_HPG", &graphics_xehpg }; 133 static const struct xe_ip graphics_ip_xehpc = { 1260, "Xe_HPC", &graphics_xehpc }; 134 135 /* GMDID-based Graphics IPs */ 136 static const struct xe_ip graphics_ips[] = { 137 { 1270, "Xe_LPG", &graphics_xelpg }, 138 { 1271, "Xe_LPG", &graphics_xelpg }, 139 { 1274, "Xe_LPG+", &graphics_xelpg }, 140 { 2001, "Xe2_HPG", &graphics_xe2 }, 141 { 2002, "Xe2_HPG", &graphics_xe2 }, 142 { 2004, "Xe2_LPG", &graphics_xe2 }, 143 { 3000, "Xe3_LPG", &graphics_xe2 }, 144 { 3001, "Xe3_LPG", &graphics_xe2 }, 145 { 3003, "Xe3_LPG", &graphics_xe2 }, 146 { 3004, "Xe3_LPG", &graphics_xe2 }, 147 { 3005, "Xe3_LPG", &graphics_xe2 }, 148 { 3511, "Xe3p_XPC", &graphics_xe3p_xpc }, 149 }; 150 151 /* Pre-GMDID Media IPs */ 152 static const struct xe_ip media_ip_xem = { 1200, "Xe_M", &media_xem }; 153 static const struct xe_ip media_ip_xehpm = { 1255, "Xe_HPM", &media_xem }; 154 155 /* GMDID-based Media IPs */ 156 static const struct xe_ip media_ips[] = { 157 { 1300, "Xe_LPM+", &media_xelpmp }, 158 { 1301, "Xe2_HPM", &media_xelpmp }, 159 { 2000, "Xe2_LPM", &media_xelpmp }, 160 { 3000, "Xe3_LPM", &media_xelpmp }, 161 { 3002, "Xe3_LPM", &media_xelpmp }, 162 { 3500, "Xe3p_LPM", &media_xelpmp }, 163 { 3503, "Xe3p_HPM", &media_xelpmp }, 164 }; 165 166 static const struct xe_device_desc tgl_desc = { 167 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 168 .pre_gmdid_media_ip = &media_ip_xem, 169 PLATFORM(TIGERLAKE), 170 .dma_mask_size = 39, 171 .has_display = true, 172 .has_llc = true, 173 .has_sriov = true, 174 .max_gt_per_tile = 1, 175 .require_force_probe = true, 176 .va_bits = 48, 177 .vm_max_level = 3, 178 }; 179 180 static const struct xe_device_desc rkl_desc = { 181 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 182 .pre_gmdid_media_ip = &media_ip_xem, 183 PLATFORM(ROCKETLAKE), 184 .dma_mask_size = 39, 185 .has_display = true, 186 .has_llc = true, 187 .max_gt_per_tile = 1, 188 .require_force_probe = true, 189 .va_bits = 48, 190 .vm_max_level = 3, 191 }; 192 193 static const u16 adls_rpls_ids[] = { INTEL_RPLS_IDS(NOP), 0 }; 194 195 static const struct xe_device_desc adl_s_desc = { 196 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 197 .pre_gmdid_media_ip = &media_ip_xem, 198 PLATFORM(ALDERLAKE_S), 199 .dma_mask_size = 39, 200 .has_display = true, 201 .has_llc = true, 202 .has_sriov = true, 203 .max_gt_per_tile = 1, 204 .require_force_probe = true, 205 .subplatforms = (const struct xe_subplatform_desc[]) { 206 { XE_SUBPLATFORM_ALDERLAKE_S_RPLS, "RPLS", adls_rpls_ids }, 207 {}, 208 }, 209 .va_bits = 48, 210 .vm_max_level = 3, 211 }; 212 213 static const u16 adlp_rplu_ids[] = { INTEL_RPLU_IDS(NOP), 0 }; 214 215 static const struct xe_device_desc adl_p_desc = { 216 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 217 .pre_gmdid_media_ip = &media_ip_xem, 218 PLATFORM(ALDERLAKE_P), 219 .dma_mask_size = 39, 220 .has_display = true, 221 .has_llc = true, 222 .has_sriov = true, 223 .max_gt_per_tile = 1, 224 .require_force_probe = true, 225 .subplatforms = (const struct xe_subplatform_desc[]) { 226 { XE_SUBPLATFORM_ALDERLAKE_P_RPLU, "RPLU", adlp_rplu_ids }, 227 {}, 228 }, 229 .va_bits = 48, 230 .vm_max_level = 3, 231 }; 232 233 static const struct xe_device_desc adl_n_desc = { 234 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 235 .pre_gmdid_media_ip = &media_ip_xem, 236 PLATFORM(ALDERLAKE_N), 237 .dma_mask_size = 39, 238 .has_display = true, 239 .has_llc = true, 240 .has_sriov = true, 241 .max_gt_per_tile = 1, 242 .require_force_probe = true, 243 .va_bits = 48, 244 .vm_max_level = 3, 245 }; 246 247 #define DGFX_FEATURES \ 248 .is_dgfx = 1 249 250 static const struct xe_device_desc dg1_desc = { 251 .pre_gmdid_graphics_ip = &graphics_ip_xelpp, 252 .pre_gmdid_media_ip = &media_ip_xem, 253 DGFX_FEATURES, 254 PLATFORM(DG1), 255 .dma_mask_size = 39, 256 .has_display = true, 257 .has_gsc_nvm = 1, 258 .has_heci_gscfi = 1, 259 .max_gt_per_tile = 1, 260 .require_force_probe = true, 261 .va_bits = 48, 262 .vm_max_level = 3, 263 }; 264 265 static const u16 dg2_g10_ids[] = { INTEL_DG2_G10_IDS(NOP), INTEL_ATS_M150_IDS(NOP), 0 }; 266 static const u16 dg2_g11_ids[] = { INTEL_DG2_G11_IDS(NOP), INTEL_ATS_M75_IDS(NOP), 0 }; 267 static const u16 dg2_g12_ids[] = { INTEL_DG2_G12_IDS(NOP), 0 }; 268 269 #define DG2_FEATURES \ 270 DGFX_FEATURES, \ 271 PLATFORM(DG2), \ 272 .has_flat_ccs = 1, \ 273 .has_gsc_nvm = 1, \ 274 .has_heci_gscfi = 1, \ 275 .subplatforms = (const struct xe_subplatform_desc[]) { \ 276 { XE_SUBPLATFORM_DG2_G10, "G10", dg2_g10_ids }, \ 277 { XE_SUBPLATFORM_DG2_G11, "G11", dg2_g11_ids }, \ 278 { XE_SUBPLATFORM_DG2_G12, "G12", dg2_g12_ids }, \ 279 { } \ 280 }, \ 281 .va_bits = 48, \ 282 .vm_max_level = 3, \ 283 .vram_flags = XE_VRAM_FLAGS_NEED64K 284 285 static const struct xe_device_desc ats_m_desc = { 286 .pre_gmdid_graphics_ip = &graphics_ip_xehpg, 287 .pre_gmdid_media_ip = &media_ip_xehpm, 288 .dma_mask_size = 46, 289 .max_gt_per_tile = 1, 290 .require_force_probe = true, 291 292 DG2_FEATURES, 293 .has_display = false, 294 .has_sriov = true, 295 }; 296 297 static const struct xe_device_desc dg2_desc = { 298 .pre_gmdid_graphics_ip = &graphics_ip_xehpg, 299 .pre_gmdid_media_ip = &media_ip_xehpm, 300 .dma_mask_size = 46, 301 .max_gt_per_tile = 1, 302 .require_force_probe = true, 303 304 DG2_FEATURES, 305 .has_display = true, 306 .has_fan_control = true, 307 .has_mbx_power_limits = false, 308 }; 309 310 static const __maybe_unused struct xe_device_desc pvc_desc = { 311 .pre_gmdid_graphics_ip = &graphics_ip_xehpc, 312 DGFX_FEATURES, 313 PLATFORM(PVC), 314 .dma_mask_size = 52, 315 .has_display = false, 316 .has_gsc_nvm = 1, 317 .has_heci_gscfi = 1, 318 .max_gt_per_tile = 1, 319 .max_remote_tiles = 1, 320 .require_force_probe = true, 321 .va_bits = 57, 322 .vm_max_level = 4, 323 .vram_flags = XE_VRAM_FLAGS_NEED64K, 324 .has_mbx_power_limits = false, 325 }; 326 327 static const struct xe_device_desc mtl_desc = { 328 /* .graphics and .media determined via GMD_ID */ 329 .require_force_probe = true, 330 PLATFORM(METEORLAKE), 331 .dma_mask_size = 46, 332 .has_display = true, 333 .has_pxp = true, 334 .max_gt_per_tile = 2, 335 .va_bits = 48, 336 .vm_max_level = 4, 337 }; 338 339 static const struct xe_device_desc lnl_desc = { 340 PLATFORM(LUNARLAKE), 341 .dma_mask_size = 46, 342 .has_display = true, 343 .has_flat_ccs = 1, 344 .has_pxp = true, 345 .max_gt_per_tile = 2, 346 .needs_scratch = true, 347 .va_bits = 48, 348 .vm_max_level = 4, 349 }; 350 351 static const u16 bmg_g21_ids[] = { INTEL_BMG_G21_IDS(NOP), 0 }; 352 353 static const struct xe_device_desc bmg_desc = { 354 DGFX_FEATURES, 355 PLATFORM(BATTLEMAGE), 356 .dma_mask_size = 46, 357 .has_display = true, 358 .has_fan_control = true, 359 .has_flat_ccs = 1, 360 .has_mbx_power_limits = true, 361 .has_gsc_nvm = 1, 362 .has_heci_cscfi = 1, 363 .has_late_bind = true, 364 .has_sriov = true, 365 .max_gt_per_tile = 2, 366 .needs_scratch = true, 367 .subplatforms = (const struct xe_subplatform_desc[]) { 368 { XE_SUBPLATFORM_BATTLEMAGE_G21, "G21", bmg_g21_ids }, 369 { } 370 }, 371 .va_bits = 48, 372 .vm_max_level = 4, 373 }; 374 375 static const struct xe_device_desc ptl_desc = { 376 PLATFORM(PANTHERLAKE), 377 .dma_mask_size = 46, 378 .has_display = true, 379 .has_flat_ccs = 1, 380 .has_sriov = true, 381 .max_gt_per_tile = 2, 382 .needs_scratch = true, 383 .needs_shared_vf_gt_wq = true, 384 .va_bits = 48, 385 .vm_max_level = 4, 386 }; 387 388 static const struct xe_device_desc nvls_desc = { 389 PLATFORM(NOVALAKE_S), 390 .dma_mask_size = 46, 391 .has_display = true, 392 .has_flat_ccs = 1, 393 .max_gt_per_tile = 2, 394 .require_force_probe = true, 395 .va_bits = 48, 396 .vm_max_level = 4, 397 }; 398 399 #undef PLATFORM 400 __diag_pop(); 401 402 /* 403 * Make sure any device matches here are from most specific to most 404 * general. For example, since the Quanta match is based on the subsystem 405 * and subvendor IDs, we need it to come before the more general IVB 406 * PCI ID matches, otherwise we'll use the wrong info struct above. 407 */ 408 static const struct pci_device_id pciidlist[] = { 409 INTEL_TGL_IDS(INTEL_VGA_DEVICE, &tgl_desc), 410 INTEL_RKL_IDS(INTEL_VGA_DEVICE, &rkl_desc), 411 INTEL_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc), 412 INTEL_ADLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 413 INTEL_ADLN_IDS(INTEL_VGA_DEVICE, &adl_n_desc), 414 INTEL_RPLU_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 415 INTEL_RPLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 416 INTEL_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc), 417 INTEL_DG1_IDS(INTEL_VGA_DEVICE, &dg1_desc), 418 INTEL_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_desc), 419 INTEL_ARL_IDS(INTEL_VGA_DEVICE, &mtl_desc), 420 INTEL_DG2_IDS(INTEL_VGA_DEVICE, &dg2_desc), 421 INTEL_MTL_IDS(INTEL_VGA_DEVICE, &mtl_desc), 422 INTEL_LNL_IDS(INTEL_VGA_DEVICE, &lnl_desc), 423 INTEL_BMG_IDS(INTEL_VGA_DEVICE, &bmg_desc), 424 INTEL_PTL_IDS(INTEL_VGA_DEVICE, &ptl_desc), 425 INTEL_NVLS_IDS(INTEL_VGA_DEVICE, &nvls_desc), 426 { } 427 }; 428 MODULE_DEVICE_TABLE(pci, pciidlist); 429 430 /* is device_id present in comma separated list of ids */ 431 static bool device_id_in_list(u16 device_id, const char *devices, bool negative) 432 { 433 char *s, *p, *tok; 434 bool ret; 435 436 if (!devices || !*devices) 437 return false; 438 439 /* match everything */ 440 if (negative && strcmp(devices, "!*") == 0) 441 return true; 442 if (!negative && strcmp(devices, "*") == 0) 443 return true; 444 445 s = kstrdup(devices, GFP_KERNEL); 446 if (!s) 447 return false; 448 449 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) { 450 u16 val; 451 452 if (negative && tok[0] == '!') 453 tok++; 454 else if ((negative && tok[0] != '!') || 455 (!negative && tok[0] == '!')) 456 continue; 457 458 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) { 459 ret = true; 460 break; 461 } 462 } 463 464 kfree(s); 465 466 return ret; 467 } 468 469 static bool id_forced(u16 device_id) 470 { 471 return device_id_in_list(device_id, xe_modparam.force_probe, false); 472 } 473 474 static bool id_blocked(u16 device_id) 475 { 476 return device_id_in_list(device_id, xe_modparam.force_probe, true); 477 } 478 479 static const struct xe_subplatform_desc * 480 find_subplatform(const struct xe_device *xe, const struct xe_device_desc *desc) 481 { 482 const struct xe_subplatform_desc *sp; 483 const u16 *id; 484 485 for (sp = desc->subplatforms; sp && sp->subplatform; sp++) 486 for (id = sp->pciidlist; *id; id++) 487 if (*id == xe->info.devid) 488 return sp; 489 490 return NULL; 491 } 492 493 enum xe_gmdid_type { 494 GMDID_GRAPHICS, 495 GMDID_MEDIA 496 }; 497 498 static int read_gmdid(struct xe_device *xe, enum xe_gmdid_type type, u32 *ver, u32 *revid) 499 { 500 struct xe_mmio *mmio = xe_root_tile_mmio(xe); 501 struct xe_reg gmdid_reg = GMD_ID; 502 u32 val; 503 504 KUNIT_STATIC_STUB_REDIRECT(read_gmdid, xe, type, ver, revid); 505 506 if (IS_SRIOV_VF(xe)) { 507 /* 508 * To get the value of the GMDID register, VFs must obtain it 509 * from the GuC using MMIO communication. 510 * 511 * Note that at this point the GTs are not initialized and only 512 * tile-level access to MMIO registers is possible. To use our 513 * existing GuC communication functions we must create a dummy 514 * GT structure and perform at least basic xe_gt and xe_guc 515 * initialization. 516 */ 517 struct xe_gt *gt __free(kfree) = NULL; 518 int err; 519 520 gt = kzalloc(sizeof(*gt), GFP_KERNEL); 521 if (!gt) 522 return -ENOMEM; 523 524 gt->tile = &xe->tiles[0]; 525 if (type == GMDID_MEDIA) { 526 gt->info.id = 1; 527 gt->info.type = XE_GT_TYPE_MEDIA; 528 } else { 529 gt->info.id = 0; 530 gt->info.type = XE_GT_TYPE_MAIN; 531 } 532 533 xe_gt_mmio_init(gt); 534 xe_guc_comm_init_early(>->uc.guc); 535 536 err = xe_gt_sriov_vf_bootstrap(gt); 537 if (err) 538 return err; 539 540 val = xe_gt_sriov_vf_gmdid(gt); 541 } else { 542 /* 543 * GMD_ID is a GT register, but at this point in the driver 544 * init we haven't fully initialized the GT yet so we need to 545 * read the register with the tile's MMIO accessor. That means 546 * we need to apply the GSI offset manually since it won't get 547 * automatically added as it would if we were using a GT mmio 548 * accessor. 549 */ 550 if (type == GMDID_MEDIA) 551 gmdid_reg.addr += MEDIA_GT_GSI_OFFSET; 552 553 val = xe_mmio_read32(mmio, gmdid_reg); 554 } 555 556 *ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val) * 100 + REG_FIELD_GET(GMD_ID_RELEASE_MASK, val); 557 *revid = REG_FIELD_GET(GMD_ID_REVID, val); 558 559 return 0; 560 } 561 562 static const struct xe_ip *find_graphics_ip(unsigned int verx100) 563 { 564 KUNIT_STATIC_STUB_REDIRECT(find_graphics_ip, verx100); 565 566 for (int i = 0; i < ARRAY_SIZE(graphics_ips); i++) 567 if (graphics_ips[i].verx100 == verx100) 568 return &graphics_ips[i]; 569 return NULL; 570 } 571 572 static const struct xe_ip *find_media_ip(unsigned int verx100) 573 { 574 KUNIT_STATIC_STUB_REDIRECT(find_media_ip, verx100); 575 576 for (int i = 0; i < ARRAY_SIZE(media_ips); i++) 577 if (media_ips[i].verx100 == verx100) 578 return &media_ips[i]; 579 return NULL; 580 } 581 582 /* 583 * Read IP version from hardware and select graphics/media IP descriptors 584 * based on the result. 585 */ 586 static int handle_gmdid(struct xe_device *xe, 587 const struct xe_ip **graphics_ip, 588 const struct xe_ip **media_ip, 589 u32 *graphics_revid, 590 u32 *media_revid) 591 { 592 u32 ver; 593 int ret; 594 595 *graphics_ip = NULL; 596 *media_ip = NULL; 597 598 ret = read_gmdid(xe, GMDID_GRAPHICS, &ver, graphics_revid); 599 if (ret) 600 return ret; 601 602 *graphics_ip = find_graphics_ip(ver); 603 if (!*graphics_ip) { 604 drm_err(&xe->drm, "Hardware reports unknown graphics version %u.%02u\n", 605 ver / 100, ver % 100); 606 } 607 608 ret = read_gmdid(xe, GMDID_MEDIA, &ver, media_revid); 609 if (ret) 610 return ret; 611 612 /* Media may legitimately be fused off / not present */ 613 if (ver == 0) 614 return 0; 615 616 *media_ip = find_media_ip(ver); 617 if (!*media_ip) { 618 drm_err(&xe->drm, "Hardware reports unknown media version %u.%02u\n", 619 ver / 100, ver % 100); 620 } 621 622 return 0; 623 } 624 625 /* 626 * Initialize device info content that only depends on static driver_data 627 * passed to the driver at probe time from PCI ID table. 628 */ 629 static int xe_info_init_early(struct xe_device *xe, 630 const struct xe_device_desc *desc, 631 const struct xe_subplatform_desc *subplatform_desc) 632 { 633 int err; 634 635 xe->info.platform_name = desc->platform_name; 636 xe->info.platform = desc->platform; 637 xe->info.subplatform = subplatform_desc ? 638 subplatform_desc->subplatform : XE_SUBPLATFORM_NONE; 639 640 xe->info.dma_mask_size = desc->dma_mask_size; 641 xe->info.va_bits = desc->va_bits; 642 xe->info.vm_max_level = desc->vm_max_level; 643 xe->info.vram_flags = desc->vram_flags; 644 645 xe->info.is_dgfx = desc->is_dgfx; 646 xe->info.has_fan_control = desc->has_fan_control; 647 /* runtime fusing may force flat_ccs to disabled later */ 648 xe->info.has_flat_ccs = desc->has_flat_ccs; 649 xe->info.has_mbx_power_limits = desc->has_mbx_power_limits; 650 xe->info.has_gsc_nvm = desc->has_gsc_nvm; 651 xe->info.has_heci_gscfi = desc->has_heci_gscfi; 652 xe->info.has_heci_cscfi = desc->has_heci_cscfi; 653 xe->info.has_late_bind = desc->has_late_bind; 654 xe->info.has_llc = desc->has_llc; 655 xe->info.has_pxp = desc->has_pxp; 656 xe->info.has_sriov = xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev)) && 657 desc->has_sriov; 658 xe->info.skip_guc_pc = desc->skip_guc_pc; 659 xe->info.skip_mtcfg = desc->skip_mtcfg; 660 xe->info.skip_pcode = desc->skip_pcode; 661 xe->info.needs_scratch = desc->needs_scratch; 662 xe->info.needs_shared_vf_gt_wq = desc->needs_shared_vf_gt_wq; 663 664 xe->info.probe_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) && 665 xe_modparam.probe_display && 666 desc->has_display; 667 668 xe_assert(xe, desc->max_gt_per_tile > 0); 669 xe_assert(xe, desc->max_gt_per_tile <= XE_MAX_GT_PER_TILE); 670 xe->info.max_gt_per_tile = desc->max_gt_per_tile; 671 xe->info.tile_count = 1 + desc->max_remote_tiles; 672 673 err = xe_tile_init_early(xe_device_get_root_tile(xe), xe, 0); 674 if (err) 675 return err; 676 677 return 0; 678 } 679 680 /* 681 * Possibly override number of tile based on configuration register. 682 */ 683 static void xe_info_probe_tile_count(struct xe_device *xe) 684 { 685 struct xe_mmio *mmio; 686 u8 tile_count; 687 u32 mtcfg; 688 689 KUNIT_STATIC_STUB_REDIRECT(xe_info_probe_tile_count, xe); 690 691 /* 692 * Probe for tile count only for platforms that support multiple 693 * tiles. 694 */ 695 if (xe->info.tile_count == 1) 696 return; 697 698 if (xe->info.skip_mtcfg) 699 return; 700 701 mmio = xe_root_tile_mmio(xe); 702 703 /* 704 * Although the per-tile mmio regs are not yet initialized, this 705 * is fine as it's going to the root tile's mmio, that's 706 * guaranteed to be initialized earlier in xe_mmio_probe_early() 707 */ 708 mtcfg = xe_mmio_read32(mmio, XEHP_MTCFG_ADDR); 709 tile_count = REG_FIELD_GET(TILE_COUNT, mtcfg) + 1; 710 711 if (tile_count < xe->info.tile_count) { 712 drm_info(&xe->drm, "tile_count: %d, reduced_tile_count %d\n", 713 xe->info.tile_count, tile_count); 714 xe->info.tile_count = tile_count; 715 } 716 } 717 718 static struct xe_gt *alloc_primary_gt(struct xe_tile *tile, 719 const struct xe_graphics_desc *graphics_desc, 720 const struct xe_media_desc *media_desc) 721 { 722 struct xe_device *xe = tile_to_xe(tile); 723 struct xe_gt *gt; 724 725 if (!xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev))) { 726 xe_info(xe, "Primary GT disabled via configfs\n"); 727 return NULL; 728 } 729 730 gt = xe_gt_alloc(tile); 731 if (IS_ERR(gt)) 732 return gt; 733 734 gt->info.type = XE_GT_TYPE_MAIN; 735 gt->info.id = tile->id * xe->info.max_gt_per_tile; 736 gt->info.has_indirect_ring_state = graphics_desc->has_indirect_ring_state; 737 gt->info.engine_mask = graphics_desc->hw_engine_mask; 738 739 /* 740 * Before media version 13, the media IP was part of the primary GT 741 * so we need to add the media engines to the primary GT's engine list. 742 */ 743 if (MEDIA_VER(xe) < 13 && media_desc) 744 gt->info.engine_mask |= media_desc->hw_engine_mask; 745 746 return gt; 747 } 748 749 static struct xe_gt *alloc_media_gt(struct xe_tile *tile, 750 const struct xe_media_desc *media_desc) 751 { 752 struct xe_device *xe = tile_to_xe(tile); 753 struct xe_gt *gt; 754 755 if (!xe_configfs_media_gt_allowed(to_pci_dev(xe->drm.dev))) { 756 xe_info(xe, "Media GT disabled via configfs\n"); 757 return NULL; 758 } 759 760 if (MEDIA_VER(xe) < 13 || !media_desc) 761 return NULL; 762 763 gt = xe_gt_alloc(tile); 764 if (IS_ERR(gt)) 765 return gt; 766 767 gt->info.type = XE_GT_TYPE_MEDIA; 768 gt->info.id = tile->id * xe->info.max_gt_per_tile + 1; 769 gt->info.has_indirect_ring_state = media_desc->has_indirect_ring_state; 770 gt->info.engine_mask = media_desc->hw_engine_mask; 771 772 return gt; 773 } 774 775 /* 776 * Initialize device info content that does require knowledge about 777 * graphics / media IP version. 778 * Make sure that GT / tile structures allocated by the driver match the data 779 * present in device info. 780 */ 781 static int xe_info_init(struct xe_device *xe, 782 const struct xe_device_desc *desc) 783 { 784 u32 graphics_gmdid_revid = 0, media_gmdid_revid = 0; 785 const struct xe_ip *graphics_ip; 786 const struct xe_ip *media_ip; 787 const struct xe_graphics_desc *graphics_desc; 788 const struct xe_media_desc *media_desc; 789 struct xe_tile *tile; 790 struct xe_gt *gt; 791 int ret; 792 u8 id; 793 794 /* 795 * If this platform supports GMD_ID, we'll detect the proper IP 796 * descriptor to use from hardware registers. 797 * desc->pre_gmdid_graphics_ip will only ever be set at this point for 798 * platforms before GMD_ID. In that case the IP descriptions and 799 * versions are simply derived from that. 800 */ 801 if (desc->pre_gmdid_graphics_ip) { 802 graphics_ip = desc->pre_gmdid_graphics_ip; 803 media_ip = desc->pre_gmdid_media_ip; 804 xe->info.step = xe_step_pre_gmdid_get(xe); 805 } else { 806 xe_assert(xe, !desc->pre_gmdid_media_ip); 807 ret = handle_gmdid(xe, &graphics_ip, &media_ip, 808 &graphics_gmdid_revid, &media_gmdid_revid); 809 if (ret) 810 return ret; 811 812 xe->info.step = xe_step_gmdid_get(xe, 813 graphics_gmdid_revid, 814 media_gmdid_revid); 815 } 816 817 /* 818 * If we couldn't detect the graphics IP, that's considered a fatal 819 * error and we should abort driver load. Failing to detect media 820 * IP is non-fatal; we'll just proceed without enabling media support. 821 */ 822 if (!graphics_ip) 823 return -ENODEV; 824 825 xe->info.graphics_verx100 = graphics_ip->verx100; 826 xe->info.graphics_name = graphics_ip->name; 827 graphics_desc = graphics_ip->desc; 828 829 if (media_ip) { 830 xe->info.media_verx100 = media_ip->verx100; 831 xe->info.media_name = media_ip->name; 832 media_desc = media_ip->desc; 833 } else { 834 xe->info.media_name = "none"; 835 media_desc = NULL; 836 } 837 838 xe->info.has_asid = graphics_desc->has_asid; 839 xe->info.has_atomic_enable_pte_bit = graphics_desc->has_atomic_enable_pte_bit; 840 if (xe->info.platform != XE_PVC) 841 xe->info.has_device_atomics_on_smem = 1; 842 843 xe->info.has_range_tlb_inval = graphics_desc->has_range_tlb_inval; 844 xe->info.has_usm = graphics_desc->has_usm; 845 xe->info.has_64bit_timestamp = graphics_desc->has_64bit_timestamp; 846 847 xe_info_probe_tile_count(xe); 848 849 for_each_remote_tile(tile, xe, id) { 850 int err; 851 852 err = xe_tile_init_early(tile, xe, id); 853 if (err) 854 return err; 855 } 856 857 /* Allocate any GT and VRAM structures necessary for the platform. */ 858 for_each_tile(tile, xe, id) { 859 int err; 860 861 err = xe_tile_alloc_vram(tile); 862 if (err) 863 return err; 864 865 tile->primary_gt = alloc_primary_gt(tile, graphics_desc, media_desc); 866 if (IS_ERR(tile->primary_gt)) 867 return PTR_ERR(tile->primary_gt); 868 869 /* 870 * It's not currently possible to probe a device with the 871 * primary GT disabled. With some work, this may be future in 872 * the possible for igpu platforms (although probably not for 873 * dgpu's since access to the primary GT's BCS engines is 874 * required for VRAM management). 875 */ 876 if (!tile->primary_gt) { 877 drm_err(&xe->drm, "Cannot probe device with without a primary GT\n"); 878 return -ENODEV; 879 } 880 881 tile->media_gt = alloc_media_gt(tile, media_desc); 882 if (IS_ERR(tile->media_gt)) 883 return PTR_ERR(tile->media_gt); 884 } 885 886 /* 887 * Now that we have tiles and GTs defined, let's loop over valid GTs 888 * in order to define gt_count. 889 */ 890 for_each_gt(gt, xe, id) 891 xe->info.gt_count++; 892 893 return 0; 894 } 895 896 static void xe_pci_remove(struct pci_dev *pdev) 897 { 898 struct xe_device *xe = pdev_to_xe_device(pdev); 899 900 if (IS_SRIOV_PF(xe)) 901 xe_pci_sriov_configure(pdev, 0); 902 903 if (xe_survivability_mode_is_boot_enabled(xe)) 904 return; 905 906 xe_device_remove(xe); 907 xe_pm_fini(xe); 908 } 909 910 /* 911 * Probe the PCI device, initialize various parts of the driver. 912 * 913 * Fault injection is used to test the error paths of some initialization 914 * functions called either directly from xe_pci_probe() or indirectly for 915 * example through xe_device_probe(). Those functions use the kernel fault 916 * injection capabilities infrastructure, see 917 * Documentation/fault-injection/fault-injection.rst for details. The macro 918 * ALLOW_ERROR_INJECTION() is used to conditionally skip function execution 919 * at runtime and use a provided return value. The first requirement for 920 * error injectable functions is proper handling of the error code by the 921 * caller for recovery, which is always the case here. The second 922 * requirement is that no state is changed before the first error return. 923 * It is not strictly fulfilled for all initialization functions using the 924 * ALLOW_ERROR_INJECTION() macro but this is acceptable because for those 925 * error cases at probe time, the error code is simply propagated up by the 926 * caller. Therefore there is no consequence on those specific callers when 927 * function error injection skips the whole function. 928 */ 929 static int xe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 930 { 931 const struct xe_device_desc *desc = (const void *)ent->driver_data; 932 const struct xe_subplatform_desc *subplatform_desc; 933 struct xe_device *xe; 934 int err; 935 936 xe_configfs_check_device(pdev); 937 938 if (desc->require_force_probe && !id_forced(pdev->device)) { 939 dev_info(&pdev->dev, 940 "Your graphics device %04x is not officially supported\n" 941 "by xe driver in this kernel version. To force Xe probe,\n" 942 "use xe.force_probe='%04x' and i915.force_probe='!%04x'\n" 943 "module parameters or CONFIG_DRM_XE_FORCE_PROBE='%04x' and\n" 944 "CONFIG_DRM_I915_FORCE_PROBE='!%04x' configuration options.\n", 945 pdev->device, pdev->device, pdev->device, 946 pdev->device, pdev->device); 947 return -ENODEV; 948 } 949 950 if (id_blocked(pdev->device)) { 951 dev_info(&pdev->dev, "Probe blocked for device [%04x:%04x].\n", 952 pdev->vendor, pdev->device); 953 return -ENODEV; 954 } 955 956 if (xe_display_driver_probe_defer(pdev)) 957 return -EPROBE_DEFER; 958 959 err = pcim_enable_device(pdev); 960 if (err) 961 return err; 962 963 xe = xe_device_create(pdev, ent); 964 if (IS_ERR(xe)) 965 return PTR_ERR(xe); 966 967 pci_set_drvdata(pdev, &xe->drm); 968 969 xe_pm_assert_unbounded_bridge(xe); 970 subplatform_desc = find_subplatform(xe, desc); 971 972 pci_set_master(pdev); 973 974 err = xe_info_init_early(xe, desc, subplatform_desc); 975 if (err) 976 return err; 977 978 xe_vram_resize_bar(xe); 979 980 err = xe_device_probe_early(xe); 981 /* 982 * In Boot Survivability mode, no drm card is exposed and driver 983 * is loaded with bare minimum to allow for firmware to be 984 * flashed through mei. Return success, if survivability mode 985 * is enabled due to pcode failure or configfs being set 986 */ 987 if (xe_survivability_mode_is_boot_enabled(xe)) 988 return 0; 989 990 if (err) 991 return err; 992 993 err = xe_info_init(xe, desc); 994 if (err) 995 return err; 996 997 err = xe_display_probe(xe); 998 if (err) 999 return err; 1000 1001 drm_dbg(&xe->drm, "%s %s %04x:%04x dgfx:%d gfx:%s (%d.%02d) media:%s (%d.%02d) display:%s dma_m_s:%d tc:%d gscfi:%d cscfi:%d", 1002 desc->platform_name, 1003 subplatform_desc ? subplatform_desc->name : "", 1004 xe->info.devid, xe->info.revid, 1005 xe->info.is_dgfx, 1006 xe->info.graphics_name, 1007 xe->info.graphics_verx100 / 100, 1008 xe->info.graphics_verx100 % 100, 1009 xe->info.media_name, 1010 xe->info.media_verx100 / 100, 1011 xe->info.media_verx100 % 100, 1012 str_yes_no(xe->info.probe_display), 1013 xe->info.dma_mask_size, xe->info.tile_count, 1014 xe->info.has_heci_gscfi, xe->info.has_heci_cscfi); 1015 1016 drm_dbg(&xe->drm, "Stepping = (G:%s, M:%s, B:%s)\n", 1017 xe_step_name(xe->info.step.graphics), 1018 xe_step_name(xe->info.step.media), 1019 xe_step_name(xe->info.step.basedie)); 1020 1021 drm_dbg(&xe->drm, "SR-IOV support: %s (mode: %s)\n", 1022 str_yes_no(xe_device_has_sriov(xe)), 1023 xe_sriov_mode_to_string(xe_device_sriov_mode(xe))); 1024 1025 err = xe_pm_init_early(xe); 1026 if (err) 1027 return err; 1028 1029 err = xe_device_probe(xe); 1030 if (err) 1031 return err; 1032 1033 err = xe_pm_init(xe); 1034 if (err) 1035 goto err_driver_cleanup; 1036 1037 drm_dbg(&xe->drm, "d3cold: capable=%s\n", 1038 str_yes_no(xe->d3cold.capable)); 1039 1040 return 0; 1041 1042 err_driver_cleanup: 1043 xe_pci_remove(pdev); 1044 return err; 1045 } 1046 1047 static void xe_pci_shutdown(struct pci_dev *pdev) 1048 { 1049 xe_device_shutdown(pdev_to_xe_device(pdev)); 1050 } 1051 1052 #ifdef CONFIG_PM_SLEEP 1053 static void d3cold_toggle(struct pci_dev *pdev, enum toggle_d3cold toggle) 1054 { 1055 struct xe_device *xe = pdev_to_xe_device(pdev); 1056 struct pci_dev *root_pdev; 1057 1058 if (!xe->d3cold.capable) 1059 return; 1060 1061 root_pdev = pcie_find_root_port(pdev); 1062 if (!root_pdev) 1063 return; 1064 1065 switch (toggle) { 1066 case D3COLD_DISABLE: 1067 pci_d3cold_disable(root_pdev); 1068 break; 1069 case D3COLD_ENABLE: 1070 pci_d3cold_enable(root_pdev); 1071 break; 1072 } 1073 } 1074 1075 static int xe_pci_suspend(struct device *dev) 1076 { 1077 struct pci_dev *pdev = to_pci_dev(dev); 1078 struct xe_device *xe = pdev_to_xe_device(pdev); 1079 int err; 1080 1081 if (xe_survivability_mode_is_boot_enabled(xe)) 1082 return -EBUSY; 1083 1084 err = xe_pm_suspend(xe); 1085 if (err) 1086 return err; 1087 1088 /* 1089 * Enabling D3Cold is needed for S2Idle/S0ix. 1090 * It is save to allow here since xe_pm_suspend has evicted 1091 * the local memory and the direct complete optimization is disabled. 1092 */ 1093 d3cold_toggle(pdev, D3COLD_ENABLE); 1094 1095 pci_save_state(pdev); 1096 pci_disable_device(pdev); 1097 pci_set_power_state(pdev, PCI_D3cold); 1098 1099 return 0; 1100 } 1101 1102 static int xe_pci_resume(struct device *dev) 1103 { 1104 struct pci_dev *pdev = to_pci_dev(dev); 1105 int err; 1106 1107 /* Give back the D3Cold decision to the runtime P M*/ 1108 d3cold_toggle(pdev, D3COLD_DISABLE); 1109 1110 err = pci_set_power_state(pdev, PCI_D0); 1111 if (err) 1112 return err; 1113 1114 pci_restore_state(pdev); 1115 1116 err = pci_enable_device(pdev); 1117 if (err) 1118 return err; 1119 1120 pci_set_master(pdev); 1121 1122 err = xe_pm_resume(pdev_to_xe_device(pdev)); 1123 if (err) 1124 return err; 1125 1126 return 0; 1127 } 1128 1129 static int xe_pci_runtime_suspend(struct device *dev) 1130 { 1131 struct pci_dev *pdev = to_pci_dev(dev); 1132 struct xe_device *xe = pdev_to_xe_device(pdev); 1133 int err; 1134 1135 err = xe_pm_runtime_suspend(xe); 1136 if (err) 1137 return err; 1138 1139 pci_save_state(pdev); 1140 1141 if (xe->d3cold.allowed) { 1142 d3cold_toggle(pdev, D3COLD_ENABLE); 1143 pci_disable_device(pdev); 1144 pci_ignore_hotplug(pdev); 1145 pci_set_power_state(pdev, PCI_D3cold); 1146 } else { 1147 d3cold_toggle(pdev, D3COLD_DISABLE); 1148 pci_set_power_state(pdev, PCI_D3hot); 1149 } 1150 1151 return 0; 1152 } 1153 1154 static int xe_pci_runtime_resume(struct device *dev) 1155 { 1156 struct pci_dev *pdev = to_pci_dev(dev); 1157 struct xe_device *xe = pdev_to_xe_device(pdev); 1158 int err; 1159 1160 err = pci_set_power_state(pdev, PCI_D0); 1161 if (err) 1162 return err; 1163 1164 pci_restore_state(pdev); 1165 1166 if (xe->d3cold.allowed) { 1167 err = pci_enable_device(pdev); 1168 if (err) 1169 return err; 1170 1171 pci_set_master(pdev); 1172 } 1173 1174 return xe_pm_runtime_resume(xe); 1175 } 1176 1177 static int xe_pci_runtime_idle(struct device *dev) 1178 { 1179 struct pci_dev *pdev = to_pci_dev(dev); 1180 struct xe_device *xe = pdev_to_xe_device(pdev); 1181 1182 xe_pm_d3cold_allowed_toggle(xe); 1183 1184 return 0; 1185 } 1186 1187 static const struct dev_pm_ops xe_pm_ops = { 1188 SET_SYSTEM_SLEEP_PM_OPS(xe_pci_suspend, xe_pci_resume) 1189 SET_RUNTIME_PM_OPS(xe_pci_runtime_suspend, xe_pci_runtime_resume, xe_pci_runtime_idle) 1190 }; 1191 #endif 1192 1193 static struct pci_driver xe_pci_driver = { 1194 .name = DRIVER_NAME, 1195 .id_table = pciidlist, 1196 .probe = xe_pci_probe, 1197 .remove = xe_pci_remove, 1198 .shutdown = xe_pci_shutdown, 1199 .sriov_configure = xe_pci_sriov_configure, 1200 #ifdef CONFIG_PM_SLEEP 1201 .driver.pm = &xe_pm_ops, 1202 #endif 1203 }; 1204 1205 int xe_register_pci_driver(void) 1206 { 1207 return pci_register_driver(&xe_pci_driver); 1208 } 1209 1210 void xe_unregister_pci_driver(void) 1211 { 1212 pci_unregister_driver(&xe_pci_driver); 1213 } 1214 1215 #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST) 1216 #include "tests/xe_pci.c" 1217 #endif 1218