1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 #include "xe_pci.h" 7 8 #include <kunit/static_stub.h> 9 #include <linux/device/driver.h> 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/pm_runtime.h> 13 14 #include <drm/drm_color_mgmt.h> 15 #include <drm/drm_drv.h> 16 #include <drm/intel/pciids.h> 17 18 #include "display/xe_display.h" 19 #include "regs/xe_gt_regs.h" 20 #include "regs/xe_regs.h" 21 #include "xe_configfs.h" 22 #include "xe_device.h" 23 #include "xe_drv.h" 24 #include "xe_gt.h" 25 #include "xe_gt_sriov_vf.h" 26 #include "xe_guc.h" 27 #include "xe_mmio.h" 28 #include "xe_module.h" 29 #include "xe_pci_rebar.h" 30 #include "xe_pci_sriov.h" 31 #include "xe_pci_types.h" 32 #include "xe_pm.h" 33 #include "xe_printk.h" 34 #include "xe_sriov.h" 35 #include "xe_step.h" 36 #include "xe_survivability_mode.h" 37 #include "xe_tile.h" 38 39 enum toggle_d3cold { 40 D3COLD_DISABLE, 41 D3COLD_ENABLE, 42 }; 43 44 __diag_push(); 45 __diag_ignore_all("-Woverride-init", "Allow field overrides in table"); 46 47 #define PLATFORM(x) \ 48 .platform = XE_##x, \ 49 .platform_name = #x 50 51 #define NOP(x) x 52 53 static const struct xe_graphics_desc graphics_xelp = { 54 .hw_engine_mask = BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0), 55 .num_geometry_xecore_fuse_regs = 1, 56 }; 57 58 #define XE_HP_FEATURES \ 59 .has_range_tlb_inval = true 60 61 static const struct xe_graphics_desc graphics_xehpg = { 62 .hw_engine_mask = 63 BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) | 64 BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) | 65 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3), 66 .num_geometry_xecore_fuse_regs = 1, 67 .num_compute_xecore_fuse_regs = 1, 68 69 XE_HP_FEATURES, 70 }; 71 72 static const struct xe_graphics_desc graphics_xehpc = { 73 .hw_engine_mask = 74 BIT(XE_HW_ENGINE_BCS0) | BIT(XE_HW_ENGINE_BCS1) | 75 BIT(XE_HW_ENGINE_BCS2) | BIT(XE_HW_ENGINE_BCS3) | 76 BIT(XE_HW_ENGINE_BCS4) | BIT(XE_HW_ENGINE_BCS5) | 77 BIT(XE_HW_ENGINE_BCS6) | BIT(XE_HW_ENGINE_BCS7) | 78 BIT(XE_HW_ENGINE_BCS8) | 79 BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) | 80 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3), 81 82 XE_HP_FEATURES, 83 84 .has_access_counter = 1, 85 .has_asid = 1, 86 .has_atomic_enable_pte_bit = 1, 87 .has_usm = 1, 88 .num_compute_xecore_fuse_regs = 2, 89 }; 90 91 static const struct xe_graphics_desc graphics_xelpg = { 92 .hw_engine_mask = 93 BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) | 94 BIT(XE_HW_ENGINE_CCS0), 95 .num_geometry_xecore_fuse_regs = 1, 96 .num_compute_xecore_fuse_regs = 1, 97 98 XE_HP_FEATURES, 99 }; 100 101 #define XE2_GFX_FEATURES \ 102 .has_access_counter = 1, \ 103 .has_asid = 1, \ 104 .has_atomic_enable_pte_bit = 1, \ 105 .has_range_tlb_inval = 1, \ 106 .has_usm = 1, \ 107 .has_64bit_timestamp = 1, \ 108 .hw_engine_mask = \ 109 BIT(XE_HW_ENGINE_RCS0) | \ 110 BIT(XE_HW_ENGINE_BCS8) | BIT(XE_HW_ENGINE_BCS0) | \ 111 GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0) 112 113 static const struct xe_graphics_desc graphics_xe2 = { 114 XE2_GFX_FEATURES, 115 .num_geometry_xecore_fuse_regs = 3, 116 .num_compute_xecore_fuse_regs = 3, 117 }; 118 119 static const struct xe_graphics_desc graphics_xe3p_lpg = { 120 XE2_GFX_FEATURES, 121 .has_indirect_ring_state = 1, 122 .multi_queue_engine_class_mask = BIT(XE_ENGINE_CLASS_COPY) | BIT(XE_ENGINE_CLASS_COMPUTE), 123 .num_geometry_xecore_fuse_regs = 3, 124 .num_compute_xecore_fuse_regs = 3, 125 }; 126 127 static const struct xe_graphics_desc graphics_xe3p_xpc = { 128 XE2_GFX_FEATURES, 129 .has_access_counter = 0, 130 .has_indirect_ring_state = 1, 131 .hw_engine_mask = 132 GENMASK(XE_HW_ENGINE_BCS8, XE_HW_ENGINE_BCS1) | 133 GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0), 134 .multi_queue_engine_class_mask = BIT(XE_ENGINE_CLASS_COPY) | 135 BIT(XE_ENGINE_CLASS_COMPUTE), 136 .num_geometry_xecore_fuse_regs = 4, 137 .num_compute_xecore_fuse_regs = 4, 138 }; 139 140 static const struct xe_media_desc media_xem = { 141 .hw_engine_mask = 142 GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) | 143 GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0), 144 }; 145 146 static const struct xe_media_desc media_xelpmp = { 147 .hw_engine_mask = 148 GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) | 149 GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0) | 150 BIT(XE_HW_ENGINE_GSCCS0) 151 }; 152 153 /* Pre-GMDID Graphics IPs */ 154 static const struct xe_ip graphics_ip_xelp = { 1200, "Xe_LP", &graphics_xelp }; 155 static const struct xe_ip graphics_ip_xelpp = { 1210, "Xe_LP+", &graphics_xelp }; 156 static const struct xe_ip graphics_ip_xehpg = { 1255, "Xe_HPG", &graphics_xehpg }; 157 static const struct xe_ip graphics_ip_xehpc = { 1260, "Xe_HPC", &graphics_xehpc }; 158 159 /* GMDID-based Graphics IPs */ 160 static const struct xe_ip graphics_ips[] = { 161 { 1270, "Xe_LPG", &graphics_xelpg }, 162 { 1271, "Xe_LPG", &graphics_xelpg }, 163 { 1274, "Xe_LPG+", &graphics_xelpg }, 164 { 2001, "Xe2_HPG", &graphics_xe2 }, 165 { 2002, "Xe2_HPG", &graphics_xe2 }, 166 { 2004, "Xe2_LPG", &graphics_xe2 }, 167 { 3000, "Xe3_LPG", &graphics_xe2 }, 168 { 3001, "Xe3_LPG", &graphics_xe2 }, 169 { 3003, "Xe3_LPG", &graphics_xe2 }, 170 { 3004, "Xe3_LPG", &graphics_xe2 }, 171 { 3005, "Xe3_LPG", &graphics_xe2 }, 172 { 3510, "Xe3p_LPG", &graphics_xe3p_lpg }, 173 { 3511, "Xe3p_XPC", &graphics_xe3p_xpc }, 174 }; 175 176 /* Pre-GMDID Media IPs */ 177 static const struct xe_ip media_ip_xem = { 1200, "Xe_M", &media_xem }; 178 static const struct xe_ip media_ip_xehpm = { 1255, "Xe_HPM", &media_xem }; 179 180 /* GMDID-based Media IPs */ 181 static const struct xe_ip media_ips[] = { 182 { 1300, "Xe_LPM+", &media_xelpmp }, 183 { 1301, "Xe2_HPM", &media_xelpmp }, 184 { 2000, "Xe2_LPM", &media_xelpmp }, 185 { 3000, "Xe3_LPM", &media_xelpmp }, 186 { 3002, "Xe3_LPM", &media_xelpmp }, 187 { 3500, "Xe3p_LPM", &media_xelpmp }, 188 { 3503, "Xe3p_HPM", &media_xelpmp }, 189 }; 190 191 #define MULTI_LRC_MASK \ 192 .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE) | \ 193 BIT(XE_ENGINE_CLASS_VIDEO_ENHANCE) 194 195 static const struct xe_device_desc tgl_desc = { 196 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 197 .pre_gmdid_media_ip = &media_ip_xem, 198 PLATFORM(TIGERLAKE), 199 .dma_mask_size = 39, 200 .has_cached_pt = true, 201 .has_display = true, 202 .has_llc = true, 203 .has_sriov = true, 204 .max_gt_per_tile = 1, 205 MULTI_LRC_MASK, 206 .require_force_probe = true, 207 .va_bits = 48, 208 .vm_max_level = 3, 209 }; 210 211 static const struct xe_device_desc rkl_desc = { 212 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 213 .pre_gmdid_media_ip = &media_ip_xem, 214 PLATFORM(ROCKETLAKE), 215 .dma_mask_size = 39, 216 .has_cached_pt = true, 217 .has_display = true, 218 .has_llc = true, 219 .max_gt_per_tile = 1, 220 MULTI_LRC_MASK, 221 .require_force_probe = true, 222 .va_bits = 48, 223 .vm_max_level = 3, 224 }; 225 226 static const u16 adls_rpls_ids[] = { INTEL_RPLS_IDS(NOP), 0 }; 227 228 static const struct xe_device_desc adl_s_desc = { 229 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 230 .pre_gmdid_media_ip = &media_ip_xem, 231 PLATFORM(ALDERLAKE_S), 232 .dma_mask_size = 39, 233 .has_cached_pt = true, 234 .has_display = true, 235 .has_llc = true, 236 .has_sriov = true, 237 .max_gt_per_tile = 1, 238 MULTI_LRC_MASK, 239 .require_force_probe = true, 240 .subplatforms = (const struct xe_subplatform_desc[]) { 241 { XE_SUBPLATFORM_ALDERLAKE_S_RPLS, "RPLS", adls_rpls_ids }, 242 {}, 243 }, 244 .va_bits = 48, 245 .vm_max_level = 3, 246 }; 247 248 static const u16 adlp_rplu_ids[] = { INTEL_RPLU_IDS(NOP), 0 }; 249 250 static const struct xe_device_desc adl_p_desc = { 251 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 252 .pre_gmdid_media_ip = &media_ip_xem, 253 PLATFORM(ALDERLAKE_P), 254 .dma_mask_size = 39, 255 .has_cached_pt = true, 256 .has_display = true, 257 .has_llc = true, 258 .has_sriov = true, 259 .max_gt_per_tile = 1, 260 MULTI_LRC_MASK, 261 .require_force_probe = true, 262 .subplatforms = (const struct xe_subplatform_desc[]) { 263 { XE_SUBPLATFORM_ALDERLAKE_P_RPLU, "RPLU", adlp_rplu_ids }, 264 {}, 265 }, 266 .va_bits = 48, 267 .vm_max_level = 3, 268 }; 269 270 static const struct xe_device_desc adl_n_desc = { 271 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 272 .pre_gmdid_media_ip = &media_ip_xem, 273 PLATFORM(ALDERLAKE_N), 274 .dma_mask_size = 39, 275 .has_cached_pt = true, 276 .has_display = true, 277 .has_llc = true, 278 .has_sriov = true, 279 .max_gt_per_tile = 1, 280 MULTI_LRC_MASK, 281 .require_force_probe = true, 282 .va_bits = 48, 283 .vm_max_level = 3, 284 }; 285 286 #define DGFX_FEATURES \ 287 .is_dgfx = 1 288 289 static const struct xe_device_desc dg1_desc = { 290 .pre_gmdid_graphics_ip = &graphics_ip_xelpp, 291 .pre_gmdid_media_ip = &media_ip_xem, 292 DGFX_FEATURES, 293 PLATFORM(DG1), 294 .dma_mask_size = 39, 295 .has_display = true, 296 .has_gsc_nvm = 1, 297 .has_heci_gscfi = 1, 298 .max_gt_per_tile = 1, 299 MULTI_LRC_MASK, 300 .require_force_probe = true, 301 .va_bits = 48, 302 .vm_max_level = 3, 303 }; 304 305 static const u16 dg2_g10_ids[] = { INTEL_DG2_G10_IDS(NOP), INTEL_ATS_M150_IDS(NOP), 0 }; 306 static const u16 dg2_g11_ids[] = { INTEL_DG2_G11_IDS(NOP), INTEL_ATS_M75_IDS(NOP), 0 }; 307 static const u16 dg2_g12_ids[] = { INTEL_DG2_G12_IDS(NOP), 0 }; 308 309 #define DG2_FEATURES \ 310 DGFX_FEATURES, \ 311 PLATFORM(DG2), \ 312 .has_flat_ccs = 1, \ 313 .has_gsc_nvm = 1, \ 314 .has_heci_gscfi = 1, \ 315 .subplatforms = (const struct xe_subplatform_desc[]) { \ 316 { XE_SUBPLATFORM_DG2_G10, "G10", dg2_g10_ids }, \ 317 { XE_SUBPLATFORM_DG2_G11, "G11", dg2_g11_ids }, \ 318 { XE_SUBPLATFORM_DG2_G12, "G12", dg2_g12_ids }, \ 319 { } \ 320 }, \ 321 .va_bits = 48, \ 322 .vm_max_level = 3, \ 323 .vram_flags = XE_VRAM_FLAGS_NEED64K 324 325 static const struct xe_device_desc ats_m_desc = { 326 .pre_gmdid_graphics_ip = &graphics_ip_xehpg, 327 .pre_gmdid_media_ip = &media_ip_xehpm, 328 .dma_mask_size = 46, 329 .max_gt_per_tile = 1, 330 MULTI_LRC_MASK, 331 .require_force_probe = true, 332 333 DG2_FEATURES, 334 .has_display = false, 335 .has_sriov = true, 336 }; 337 338 static const struct xe_device_desc dg2_desc = { 339 .pre_gmdid_graphics_ip = &graphics_ip_xehpg, 340 .pre_gmdid_media_ip = &media_ip_xehpm, 341 .dma_mask_size = 46, 342 .max_gt_per_tile = 1, 343 MULTI_LRC_MASK, 344 .require_force_probe = true, 345 346 DG2_FEATURES, 347 .has_display = true, 348 .has_fan_control = true, 349 .has_mbx_power_limits = false, 350 }; 351 352 static const __maybe_unused struct xe_device_desc pvc_desc = { 353 .pre_gmdid_graphics_ip = &graphics_ip_xehpc, 354 DGFX_FEATURES, 355 PLATFORM(PVC), 356 .dma_mask_size = 52, 357 .has_display = false, 358 .has_gsc_nvm = 1, 359 .has_heci_gscfi = 1, 360 .max_gt_per_tile = 1, 361 .max_remote_tiles = 1, 362 MULTI_LRC_MASK, 363 .require_force_probe = true, 364 .va_bits = 57, 365 .vm_max_level = 4, 366 .vram_flags = XE_VRAM_FLAGS_NEED64K, 367 .has_mbx_power_limits = false, 368 }; 369 370 static const struct xe_device_desc mtl_desc = { 371 /* .graphics and .media determined via GMD_ID */ 372 .require_force_probe = true, 373 PLATFORM(METEORLAKE), 374 .dma_mask_size = 46, 375 .has_display = true, 376 .has_pxp = true, 377 .max_gt_per_tile = 2, 378 MULTI_LRC_MASK, 379 .va_bits = 48, 380 .vm_max_level = 3, 381 }; 382 383 static const struct xe_device_desc lnl_desc = { 384 PLATFORM(LUNARLAKE), 385 .dma_mask_size = 46, 386 .has_display = true, 387 .has_flat_ccs = 1, 388 .has_pxp = true, 389 .max_gt_per_tile = 2, 390 MULTI_LRC_MASK, 391 .needs_scratch = true, 392 .va_bits = 48, 393 .vm_max_level = 4, 394 }; 395 396 static const u16 bmg_g21_ids[] = { INTEL_BMG_G21_IDS(NOP), 0 }; 397 398 static const struct xe_device_desc bmg_desc = { 399 DGFX_FEATURES, 400 PLATFORM(BATTLEMAGE), 401 .dma_mask_size = 46, 402 .has_display = true, 403 .has_fan_control = true, 404 .has_flat_ccs = 1, 405 .has_mbx_power_limits = true, 406 .has_mbx_thermal_info = true, 407 .has_gsc_nvm = 1, 408 .has_heci_cscfi = 1, 409 .has_i2c = true, 410 .has_late_bind = true, 411 .has_pre_prod_wa = 1, 412 .has_soc_remapper_telem = true, 413 .has_sriov = true, 414 .max_gt_per_tile = 2, 415 MULTI_LRC_MASK, 416 .needs_scratch = true, 417 .subplatforms = (const struct xe_subplatform_desc[]) { 418 { XE_SUBPLATFORM_BATTLEMAGE_G21, "G21", bmg_g21_ids }, 419 { } 420 }, 421 .va_bits = 48, 422 .vm_max_level = 4, 423 }; 424 425 static const struct xe_device_desc ptl_desc = { 426 PLATFORM(PANTHERLAKE), 427 .dma_mask_size = 46, 428 .has_display = true, 429 .has_flat_ccs = 1, 430 .has_sriov = true, 431 .has_pre_prod_wa = 1, 432 .has_pxp = true, 433 .max_gt_per_tile = 2, 434 MULTI_LRC_MASK, 435 .needs_scratch = true, 436 .needs_shared_vf_gt_wq = true, 437 .va_bits = 48, 438 .vm_max_level = 4, 439 }; 440 441 static const struct xe_device_desc nvls_desc = { 442 PLATFORM(NOVALAKE_S), 443 .dma_mask_size = 46, 444 .has_display = true, 445 .has_flat_ccs = 1, 446 .has_pre_prod_wa = 1, 447 .max_gt_per_tile = 2, 448 MULTI_LRC_MASK, 449 .require_force_probe = true, 450 .va_bits = 48, 451 .vm_max_level = 4, 452 }; 453 454 static const struct xe_device_desc cri_desc = { 455 DGFX_FEATURES, 456 PLATFORM(CRESCENTISLAND), 457 .dma_mask_size = 52, 458 .has_display = false, 459 .has_flat_ccs = false, 460 .has_gsc_nvm = 1, 461 .has_i2c = true, 462 .has_mbx_power_limits = true, 463 .has_mbx_thermal_info = true, 464 .has_mert = true, 465 .has_pre_prod_wa = 1, 466 .has_soc_remapper_sysctrl = true, 467 .has_soc_remapper_telem = true, 468 .has_sriov = true, 469 .max_gt_per_tile = 2, 470 MULTI_LRC_MASK, 471 .require_force_probe = true, 472 .va_bits = 57, 473 .vm_max_level = 4, 474 }; 475 476 static const struct xe_device_desc nvlp_desc = { 477 PLATFORM(NOVALAKE_P), 478 .dma_mask_size = 46, 479 .has_cached_pt = true, 480 .has_display = true, 481 .has_flat_ccs = 1, 482 .has_page_reclaim_hw_assist = true, 483 .has_pre_prod_wa = true, 484 .max_gt_per_tile = 2, 485 MULTI_LRC_MASK, 486 .require_force_probe = true, 487 .va_bits = 48, 488 .vm_max_level = 4, 489 }; 490 491 #undef PLATFORM 492 __diag_pop(); 493 494 /* 495 * Make sure any device matches here are from most specific to most 496 * general. For example, since the Quanta match is based on the subsystem 497 * and subvendor IDs, we need it to come before the more general IVB 498 * PCI ID matches, otherwise we'll use the wrong info struct above. 499 */ 500 static const struct pci_device_id pciidlist[] = { 501 INTEL_TGL_IDS(INTEL_VGA_DEVICE, &tgl_desc), 502 INTEL_RKL_IDS(INTEL_VGA_DEVICE, &rkl_desc), 503 INTEL_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc), 504 INTEL_ADLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 505 INTEL_ADLN_IDS(INTEL_VGA_DEVICE, &adl_n_desc), 506 INTEL_RPLU_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 507 INTEL_RPLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 508 INTEL_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc), 509 INTEL_DG1_IDS(INTEL_VGA_DEVICE, &dg1_desc), 510 INTEL_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_desc), 511 INTEL_ARL_IDS(INTEL_VGA_DEVICE, &mtl_desc), 512 INTEL_DG2_IDS(INTEL_VGA_DEVICE, &dg2_desc), 513 INTEL_MTL_IDS(INTEL_VGA_DEVICE, &mtl_desc), 514 INTEL_LNL_IDS(INTEL_VGA_DEVICE, &lnl_desc), 515 INTEL_BMG_IDS(INTEL_VGA_DEVICE, &bmg_desc), 516 INTEL_PTL_IDS(INTEL_VGA_DEVICE, &ptl_desc), 517 INTEL_WCL_IDS(INTEL_VGA_DEVICE, &ptl_desc), 518 INTEL_NVLS_IDS(INTEL_VGA_DEVICE, &nvls_desc), 519 INTEL_CRI_IDS(INTEL_PCI_DEVICE, &cri_desc), 520 INTEL_NVLP_IDS(INTEL_VGA_DEVICE, &nvlp_desc), 521 { } 522 }; 523 MODULE_DEVICE_TABLE(pci, pciidlist); 524 525 /* is device_id present in comma separated list of ids */ 526 static bool device_id_in_list(u16 device_id, const char *devices, bool negative) 527 { 528 char *s, *p, *tok; 529 bool ret; 530 531 if (!devices || !*devices) 532 return false; 533 534 /* match everything */ 535 if (negative && strcmp(devices, "!*") == 0) 536 return true; 537 if (!negative && strcmp(devices, "*") == 0) 538 return true; 539 540 s = kstrdup(devices, GFP_KERNEL); 541 if (!s) 542 return false; 543 544 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) { 545 u16 val; 546 547 if (negative && tok[0] == '!') 548 tok++; 549 else if ((negative && tok[0] != '!') || 550 (!negative && tok[0] == '!')) 551 continue; 552 553 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) { 554 ret = true; 555 break; 556 } 557 } 558 559 kfree(s); 560 561 return ret; 562 } 563 564 static bool id_forced(u16 device_id) 565 { 566 return device_id_in_list(device_id, xe_modparam.force_probe, false); 567 } 568 569 static bool id_blocked(u16 device_id) 570 { 571 return device_id_in_list(device_id, xe_modparam.force_probe, true); 572 } 573 574 static const struct xe_subplatform_desc * 575 find_subplatform(const struct xe_device *xe, const struct xe_device_desc *desc) 576 { 577 const struct xe_subplatform_desc *sp; 578 const u16 *id; 579 580 for (sp = desc->subplatforms; sp && sp->subplatform; sp++) 581 for (id = sp->pciidlist; *id; id++) 582 if (*id == xe->info.devid) 583 return sp; 584 585 return NULL; 586 } 587 588 enum xe_gmdid_type { 589 GMDID_GRAPHICS, 590 GMDID_MEDIA 591 }; 592 593 static int read_gmdid(struct xe_device *xe, enum xe_gmdid_type type, u32 *ver, u32 *revid) 594 { 595 struct xe_mmio *mmio = xe_root_tile_mmio(xe); 596 struct xe_reg gmdid_reg = GMD_ID; 597 u32 val; 598 599 KUNIT_STATIC_STUB_REDIRECT(read_gmdid, xe, type, ver, revid); 600 601 if (IS_SRIOV_VF(xe)) { 602 /* 603 * To get the value of the GMDID register, VFs must obtain it 604 * from the GuC using MMIO communication. 605 * 606 * Note that at this point the GTs are not initialized and only 607 * tile-level access to MMIO registers is possible. To use our 608 * existing GuC communication functions we must create a dummy 609 * GT structure and perform at least basic xe_gt and xe_guc 610 * initialization. 611 */ 612 struct xe_gt *gt __free(kfree) = NULL; 613 int err; 614 615 /* Don't try to read media ver if media GT is not allowed */ 616 if (type == GMDID_MEDIA && !xe_configfs_media_gt_allowed(to_pci_dev(xe->drm.dev))) { 617 *ver = *revid = 0; 618 return 0; 619 } 620 621 gt = kzalloc(sizeof(*gt), GFP_KERNEL); 622 if (!gt) 623 return -ENOMEM; 624 625 gt->tile = &xe->tiles[0]; 626 if (type == GMDID_MEDIA) { 627 gt->info.id = 1; 628 gt->info.type = XE_GT_TYPE_MEDIA; 629 } else { 630 gt->info.id = 0; 631 gt->info.type = XE_GT_TYPE_MAIN; 632 } 633 634 xe_gt_mmio_init(gt); 635 xe_guc_comm_init_early(>->uc.guc); 636 637 err = xe_gt_sriov_vf_bootstrap(gt); 638 if (err) 639 return err; 640 641 val = xe_gt_sriov_vf_gmdid(gt); 642 } else { 643 /* 644 * GMD_ID is a GT register, but at this point in the driver 645 * init we haven't fully initialized the GT yet so we need to 646 * read the register with the tile's MMIO accessor. That means 647 * we need to apply the GSI offset manually since it won't get 648 * automatically added as it would if we were using a GT mmio 649 * accessor. 650 */ 651 if (type == GMDID_MEDIA) 652 gmdid_reg.addr += MEDIA_GT_GSI_OFFSET; 653 654 val = xe_mmio_read32(mmio, gmdid_reg); 655 } 656 657 *ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val) * 100 + REG_FIELD_GET(GMD_ID_RELEASE_MASK, val); 658 *revid = REG_FIELD_GET(GMD_ID_REVID, val); 659 660 return 0; 661 } 662 663 static const struct xe_ip *find_graphics_ip(unsigned int verx100) 664 { 665 KUNIT_STATIC_STUB_REDIRECT(find_graphics_ip, verx100); 666 667 for (int i = 0; i < ARRAY_SIZE(graphics_ips); i++) 668 if (graphics_ips[i].verx100 == verx100) 669 return &graphics_ips[i]; 670 return NULL; 671 } 672 673 static const struct xe_ip *find_media_ip(unsigned int verx100) 674 { 675 KUNIT_STATIC_STUB_REDIRECT(find_media_ip, verx100); 676 677 for (int i = 0; i < ARRAY_SIZE(media_ips); i++) 678 if (media_ips[i].verx100 == verx100) 679 return &media_ips[i]; 680 return NULL; 681 } 682 683 /* 684 * Read IP version from hardware and select graphics/media IP descriptors 685 * based on the result. 686 */ 687 static int handle_gmdid(struct xe_device *xe, 688 const struct xe_ip **graphics_ip, 689 const struct xe_ip **media_ip, 690 u32 *graphics_revid, 691 u32 *media_revid) 692 { 693 u32 ver; 694 int ret; 695 696 *graphics_ip = NULL; 697 *media_ip = NULL; 698 699 ret = read_gmdid(xe, GMDID_GRAPHICS, &ver, graphics_revid); 700 if (ret) 701 return ret; 702 703 *graphics_ip = find_graphics_ip(ver); 704 if (!*graphics_ip) { 705 drm_err(&xe->drm, "Hardware reports unknown graphics version %u.%02u\n", 706 ver / 100, ver % 100); 707 } 708 709 ret = read_gmdid(xe, GMDID_MEDIA, &ver, media_revid); 710 if (ret) 711 return ret; 712 713 /* Media may legitimately be fused off / not present */ 714 if (ver == 0) 715 return 0; 716 717 *media_ip = find_media_ip(ver); 718 if (!*media_ip) { 719 drm_err(&xe->drm, "Hardware reports unknown media version %u.%02u\n", 720 ver / 100, ver % 100); 721 } 722 723 return 0; 724 } 725 726 /* 727 * Initialize device info content that only depends on static driver_data 728 * passed to the driver at probe time from PCI ID table. 729 */ 730 static int xe_info_init_early(struct xe_device *xe, 731 const struct xe_device_desc *desc, 732 const struct xe_subplatform_desc *subplatform_desc) 733 { 734 int err; 735 736 xe->info.platform_name = desc->platform_name; 737 xe->info.platform = desc->platform; 738 xe->info.subplatform = subplatform_desc ? 739 subplatform_desc->subplatform : XE_SUBPLATFORM_NONE; 740 741 xe->info.dma_mask_size = desc->dma_mask_size; 742 xe->info.va_bits = desc->va_bits; 743 xe->info.vm_max_level = desc->vm_max_level; 744 xe->info.vram_flags = desc->vram_flags; 745 746 xe->info.is_dgfx = desc->is_dgfx; 747 xe->info.has_cached_pt = desc->has_cached_pt; 748 xe->info.has_fan_control = desc->has_fan_control; 749 /* runtime fusing may force flat_ccs to disabled later */ 750 xe->info.has_flat_ccs = desc->has_flat_ccs; 751 xe->info.has_mbx_power_limits = desc->has_mbx_power_limits; 752 xe->info.has_mbx_thermal_info = desc->has_mbx_thermal_info; 753 xe->info.has_gsc_nvm = desc->has_gsc_nvm; 754 xe->info.has_heci_gscfi = desc->has_heci_gscfi; 755 xe->info.has_heci_cscfi = desc->has_heci_cscfi; 756 xe->info.has_i2c = desc->has_i2c; 757 xe->info.has_late_bind = desc->has_late_bind; 758 xe->info.has_llc = desc->has_llc; 759 xe->info.has_mert = desc->has_mert; 760 xe->info.has_page_reclaim_hw_assist = desc->has_page_reclaim_hw_assist; 761 xe->info.has_pre_prod_wa = desc->has_pre_prod_wa; 762 xe->info.has_pxp = desc->has_pxp; 763 xe->info.has_soc_remapper_sysctrl = desc->has_soc_remapper_sysctrl; 764 xe->info.has_soc_remapper_telem = desc->has_soc_remapper_telem; 765 xe->info.has_sriov = xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev)) && 766 desc->has_sriov; 767 xe->info.skip_guc_pc = desc->skip_guc_pc; 768 xe->info.skip_mtcfg = desc->skip_mtcfg; 769 xe->info.skip_pcode = desc->skip_pcode; 770 xe->info.needs_scratch = desc->needs_scratch; 771 xe->info.needs_shared_vf_gt_wq = desc->needs_shared_vf_gt_wq; 772 xe->info.multi_lrc_mask = desc->multi_lrc_mask; 773 774 xe->info.probe_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) && 775 xe_modparam.probe_display && 776 desc->has_display; 777 778 xe_assert(xe, desc->max_gt_per_tile > 0); 779 xe_assert(xe, desc->max_gt_per_tile <= XE_MAX_GT_PER_TILE); 780 xe->info.max_gt_per_tile = desc->max_gt_per_tile; 781 xe->info.tile_count = 1 + desc->max_remote_tiles; 782 783 xe_step_platform_get(xe); 784 785 err = xe_tile_init_early(xe_device_get_root_tile(xe), xe, 0); 786 if (err) 787 return err; 788 789 return 0; 790 } 791 792 /* 793 * Possibly override number of tile based on configuration register. 794 */ 795 static void xe_info_probe_tile_count(struct xe_device *xe) 796 { 797 struct xe_mmio *mmio; 798 u8 tile_count; 799 u32 mtcfg; 800 801 KUNIT_STATIC_STUB_REDIRECT(xe_info_probe_tile_count, xe); 802 803 /* 804 * Probe for tile count only for platforms that support multiple 805 * tiles. 806 */ 807 if (xe->info.tile_count == 1) 808 return; 809 810 if (xe->info.skip_mtcfg) 811 return; 812 813 mmio = xe_root_tile_mmio(xe); 814 815 /* 816 * Although the per-tile mmio regs are not yet initialized, this 817 * is fine as it's going to the root tile's mmio, that's 818 * guaranteed to be initialized earlier in xe_mmio_probe_early() 819 */ 820 mtcfg = xe_mmio_read32(mmio, XEHP_MTCFG_ADDR); 821 tile_count = REG_FIELD_GET(TILE_COUNT, mtcfg) + 1; 822 823 if (tile_count < xe->info.tile_count) { 824 drm_info(&xe->drm, "tile_count: %d, reduced_tile_count %d\n", 825 xe->info.tile_count, tile_count); 826 xe->info.tile_count = tile_count; 827 } 828 } 829 830 static struct xe_gt *alloc_primary_gt(struct xe_tile *tile, 831 const struct xe_graphics_desc *graphics_desc, 832 const struct xe_media_desc *media_desc) 833 { 834 struct xe_device *xe = tile_to_xe(tile); 835 struct xe_gt *gt; 836 837 if (!xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev))) { 838 xe_info(xe, "Primary GT disabled via configfs\n"); 839 return NULL; 840 } 841 842 gt = xe_gt_alloc(tile); 843 if (IS_ERR(gt)) 844 return gt; 845 846 gt->info.type = XE_GT_TYPE_MAIN; 847 gt->info.id = tile->id * xe->info.max_gt_per_tile; 848 gt->info.has_indirect_ring_state = graphics_desc->has_indirect_ring_state; 849 gt->info.multi_queue_engine_class_mask = graphics_desc->multi_queue_engine_class_mask; 850 gt->info.engine_mask = graphics_desc->hw_engine_mask; 851 gt->info.num_geometry_xecore_fuse_regs = graphics_desc->num_geometry_xecore_fuse_regs; 852 gt->info.num_compute_xecore_fuse_regs = graphics_desc->num_compute_xecore_fuse_regs; 853 854 /* 855 * Even if the service copy engines wind up being fused off, their 856 * presence in the IP descriptor indicates that the platform supports 857 * Xe2-style MEM_SET and MEM_COPY functionality. 858 */ 859 if (graphics_desc->hw_engine_mask & GENMASK(XE_HW_ENGINE_BCS8, 860 XE_HW_ENGINE_BCS1)) 861 gt->info.has_xe2_blt_instructions = true; 862 863 /* 864 * Before media version 13, the media IP was part of the primary GT 865 * so we need to add the media engines to the primary GT's engine list. 866 */ 867 if (MEDIA_VER(xe) < 13 && media_desc) 868 gt->info.engine_mask |= media_desc->hw_engine_mask; 869 870 return gt; 871 } 872 873 static struct xe_gt *alloc_media_gt(struct xe_tile *tile, 874 const struct xe_media_desc *media_desc) 875 { 876 struct xe_device *xe = tile_to_xe(tile); 877 struct xe_gt *gt; 878 879 if (!xe_configfs_media_gt_allowed(to_pci_dev(xe->drm.dev))) { 880 xe_info(xe, "Media GT disabled via configfs\n"); 881 return NULL; 882 } 883 884 if (MEDIA_VER(xe) < 13 || !media_desc) 885 return NULL; 886 887 gt = xe_gt_alloc(tile); 888 if (IS_ERR(gt)) 889 return gt; 890 891 gt->info.type = XE_GT_TYPE_MEDIA; 892 gt->info.id = tile->id * xe->info.max_gt_per_tile + 1; 893 gt->info.has_indirect_ring_state = media_desc->has_indirect_ring_state; 894 gt->info.engine_mask = media_desc->hw_engine_mask; 895 896 return gt; 897 } 898 899 /* 900 * Initialize device info content that does require knowledge about 901 * graphics / media IP version. 902 * Make sure that GT / tile structures allocated by the driver match the data 903 * present in device info. 904 */ 905 static int xe_info_init(struct xe_device *xe, 906 const struct xe_device_desc *desc) 907 { 908 u32 graphics_gmdid_revid = 0, media_gmdid_revid = 0; 909 const struct xe_ip *graphics_ip; 910 const struct xe_ip *media_ip; 911 const struct xe_graphics_desc *graphics_desc; 912 const struct xe_media_desc *media_desc; 913 struct xe_tile *tile; 914 struct xe_gt *gt; 915 int ret; 916 u8 id; 917 918 /* 919 * If this platform supports GMD_ID, we'll detect the proper IP 920 * descriptor to use from hardware registers. 921 * desc->pre_gmdid_graphics_ip will only ever be set at this point for 922 * platforms before GMD_ID. In that case the IP descriptions and 923 * versions are simply derived from that. 924 */ 925 if (desc->pre_gmdid_graphics_ip) { 926 graphics_ip = desc->pre_gmdid_graphics_ip; 927 media_ip = desc->pre_gmdid_media_ip; 928 xe_step_pre_gmdid_get(xe); 929 } else { 930 xe_assert(xe, !desc->pre_gmdid_media_ip); 931 ret = handle_gmdid(xe, &graphics_ip, &media_ip, 932 &graphics_gmdid_revid, &media_gmdid_revid); 933 if (ret) 934 return ret; 935 936 xe_step_gmdid_get(xe, graphics_gmdid_revid, media_gmdid_revid); 937 } 938 939 /* 940 * If we couldn't detect the graphics IP, that's considered a fatal 941 * error and we should abort driver load. Failing to detect media 942 * IP is non-fatal; we'll just proceed without enabling media support. 943 */ 944 if (!graphics_ip) 945 return -ENODEV; 946 947 xe->info.graphics_verx100 = graphics_ip->verx100; 948 xe->info.graphics_name = graphics_ip->name; 949 graphics_desc = graphics_ip->desc; 950 951 if (media_ip) { 952 xe->info.media_verx100 = media_ip->verx100; 953 xe->info.media_name = media_ip->name; 954 media_desc = media_ip->desc; 955 } else { 956 xe->info.media_name = "none"; 957 media_desc = NULL; 958 } 959 960 xe->info.has_access_counter = graphics_desc->has_access_counter; 961 xe->info.has_asid = graphics_desc->has_asid; 962 xe->info.has_atomic_enable_pte_bit = graphics_desc->has_atomic_enable_pte_bit; 963 if (xe->info.platform != XE_PVC) 964 xe->info.has_device_atomics_on_smem = 1; 965 966 xe->info.has_range_tlb_inval = graphics_desc->has_range_tlb_inval; 967 xe->info.has_ctx_tlb_inval = graphics_desc->has_ctx_tlb_inval; 968 xe->info.has_usm = graphics_desc->has_usm; 969 xe->info.has_64bit_timestamp = graphics_desc->has_64bit_timestamp; 970 xe->info.has_mem_copy_instr = GRAPHICS_VER(xe) >= 20; 971 972 xe_info_probe_tile_count(xe); 973 974 for_each_remote_tile(tile, xe, id) { 975 int err; 976 977 err = xe_tile_init_early(tile, xe, id); 978 if (err) 979 return err; 980 } 981 982 /* Allocate any GT and VRAM structures necessary for the platform. */ 983 for_each_tile(tile, xe, id) { 984 int err; 985 986 err = xe_tile_alloc_vram(tile); 987 if (err) 988 return err; 989 990 tile->primary_gt = alloc_primary_gt(tile, graphics_desc, media_desc); 991 if (IS_ERR(tile->primary_gt)) 992 return PTR_ERR(tile->primary_gt); 993 994 /* 995 * It's not currently possible to probe a device with the 996 * primary GT disabled. With some work, this may be future in 997 * the possible for igpu platforms (although probably not for 998 * dgpu's since access to the primary GT's BCS engines is 999 * required for VRAM management). 1000 */ 1001 if (!tile->primary_gt) { 1002 drm_err(&xe->drm, "Cannot probe device with without a primary GT\n"); 1003 return -ENODEV; 1004 } 1005 1006 tile->media_gt = alloc_media_gt(tile, media_desc); 1007 if (IS_ERR(tile->media_gt)) 1008 return PTR_ERR(tile->media_gt); 1009 } 1010 1011 /* 1012 * Now that we have tiles and GTs defined, let's loop over valid GTs 1013 * in order to define gt_count. 1014 */ 1015 for_each_gt(gt, xe, id) 1016 xe->info.gt_count++; 1017 1018 return 0; 1019 } 1020 1021 static void xe_pci_remove(struct pci_dev *pdev) 1022 { 1023 struct xe_device *xe = pdev_to_xe_device(pdev); 1024 1025 if (IS_SRIOV_PF(xe)) 1026 xe_pci_sriov_configure(pdev, 0); 1027 1028 if (xe_survivability_mode_is_boot_enabled(xe)) 1029 return; 1030 1031 xe_device_remove(xe); 1032 xe_pm_fini(xe); 1033 } 1034 1035 /* 1036 * Probe the PCI device, initialize various parts of the driver. 1037 * 1038 * Fault injection is used to test the error paths of some initialization 1039 * functions called either directly from xe_pci_probe() or indirectly for 1040 * example through xe_device_probe(). Those functions use the kernel fault 1041 * injection capabilities infrastructure, see 1042 * Documentation/fault-injection/fault-injection.rst for details. The macro 1043 * ALLOW_ERROR_INJECTION() is used to conditionally skip function execution 1044 * at runtime and use a provided return value. The first requirement for 1045 * error injectable functions is proper handling of the error code by the 1046 * caller for recovery, which is always the case here. The second 1047 * requirement is that no state is changed before the first error return. 1048 * It is not strictly fulfilled for all initialization functions using the 1049 * ALLOW_ERROR_INJECTION() macro but this is acceptable because for those 1050 * error cases at probe time, the error code is simply propagated up by the 1051 * caller. Therefore there is no consequence on those specific callers when 1052 * function error injection skips the whole function. 1053 */ 1054 static int xe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1055 { 1056 const struct xe_device_desc *desc = (const void *)ent->driver_data; 1057 const struct xe_subplatform_desc *subplatform_desc; 1058 struct xe_device *xe; 1059 int err; 1060 1061 xe_configfs_check_device(pdev); 1062 1063 if (desc->require_force_probe && !id_forced(pdev->device)) { 1064 dev_info(&pdev->dev, 1065 "Your graphics device %04x is not officially supported\n" 1066 "by xe driver in this kernel version. To force Xe probe,\n" 1067 "use xe.force_probe='%04x' and i915.force_probe='!%04x'\n" 1068 "module parameters or CONFIG_DRM_XE_FORCE_PROBE='%04x' and\n" 1069 "CONFIG_DRM_I915_FORCE_PROBE='!%04x' configuration options.\n", 1070 pdev->device, pdev->device, pdev->device, 1071 pdev->device, pdev->device); 1072 return -ENODEV; 1073 } 1074 1075 if (id_blocked(pdev->device)) { 1076 dev_info(&pdev->dev, "Probe blocked for device [%04x:%04x].\n", 1077 pdev->vendor, pdev->device); 1078 return -ENODEV; 1079 } 1080 1081 if (xe_display_driver_probe_defer(pdev)) 1082 return -EPROBE_DEFER; 1083 1084 err = pcim_enable_device(pdev); 1085 if (err) 1086 return err; 1087 1088 xe = xe_device_create(pdev, ent); 1089 if (IS_ERR(xe)) 1090 return PTR_ERR(xe); 1091 1092 pci_set_drvdata(pdev, &xe->drm); 1093 1094 xe_pm_assert_unbounded_bridge(xe); 1095 subplatform_desc = find_subplatform(xe, desc); 1096 1097 pci_set_master(pdev); 1098 1099 err = xe_info_init_early(xe, desc, subplatform_desc); 1100 if (err) 1101 return err; 1102 1103 xe_pci_rebar_resize(xe); 1104 1105 err = xe_device_probe_early(xe); 1106 /* 1107 * In Boot Survivability mode, no drm card is exposed and driver 1108 * is loaded with bare minimum to allow for firmware to be 1109 * flashed through mei. Return success, if survivability mode 1110 * is enabled due to pcode failure or configfs being set 1111 */ 1112 if (xe_survivability_mode_is_boot_enabled(xe)) 1113 return 0; 1114 1115 if (err) 1116 return err; 1117 1118 err = xe_info_init(xe, desc); 1119 if (err) 1120 return err; 1121 1122 err = xe_display_probe(xe); 1123 if (err) 1124 return err; 1125 1126 drm_dbg(&xe->drm, "%s %s %04x:%04x dgfx:%d gfx:%s (%d.%02d) media:%s (%d.%02d) display:%s dma_m_s:%d tc:%d gscfi:%d cscfi:%d", 1127 desc->platform_name, 1128 subplatform_desc ? subplatform_desc->name : "", 1129 xe->info.devid, xe->info.revid, 1130 xe->info.is_dgfx, 1131 xe->info.graphics_name, 1132 xe->info.graphics_verx100 / 100, 1133 xe->info.graphics_verx100 % 100, 1134 xe->info.media_name, 1135 xe->info.media_verx100 / 100, 1136 xe->info.media_verx100 % 100, 1137 str_yes_no(xe->info.probe_display), 1138 xe->info.dma_mask_size, xe->info.tile_count, 1139 xe->info.has_heci_gscfi, xe->info.has_heci_cscfi); 1140 1141 drm_dbg(&xe->drm, "Stepping = (G:%s, M:%s, B:%s)\n", 1142 xe_step_name(xe->info.step.graphics), 1143 xe_step_name(xe->info.step.media), 1144 xe_step_name(xe->info.step.basedie)); 1145 1146 drm_dbg(&xe->drm, "SR-IOV support: %s (mode: %s)\n", 1147 str_yes_no(xe_device_has_sriov(xe)), 1148 xe_sriov_mode_to_string(xe_device_sriov_mode(xe))); 1149 1150 err = xe_pm_init_early(xe); 1151 if (err) 1152 return err; 1153 1154 err = xe_device_probe(xe); 1155 if (err) 1156 return err; 1157 1158 err = xe_pm_init(xe); 1159 if (err) 1160 goto err_driver_cleanup; 1161 1162 drm_dbg(&xe->drm, "d3cold: capable=%s\n", 1163 str_yes_no(xe->d3cold.capable)); 1164 1165 return 0; 1166 1167 err_driver_cleanup: 1168 xe_pci_remove(pdev); 1169 return err; 1170 } 1171 1172 static void xe_pci_shutdown(struct pci_dev *pdev) 1173 { 1174 xe_device_shutdown(pdev_to_xe_device(pdev)); 1175 } 1176 1177 #ifdef CONFIG_PM_SLEEP 1178 static void d3cold_toggle(struct pci_dev *pdev, enum toggle_d3cold toggle) 1179 { 1180 struct xe_device *xe = pdev_to_xe_device(pdev); 1181 struct pci_dev *root_pdev; 1182 1183 if (!xe->d3cold.capable) 1184 return; 1185 1186 root_pdev = pcie_find_root_port(pdev); 1187 if (!root_pdev) 1188 return; 1189 1190 switch (toggle) { 1191 case D3COLD_DISABLE: 1192 pci_d3cold_disable(root_pdev); 1193 break; 1194 case D3COLD_ENABLE: 1195 pci_d3cold_enable(root_pdev); 1196 break; 1197 } 1198 } 1199 1200 static int xe_pci_suspend(struct device *dev) 1201 { 1202 struct pci_dev *pdev = to_pci_dev(dev); 1203 struct xe_device *xe = pdev_to_xe_device(pdev); 1204 int err; 1205 1206 if (xe_survivability_mode_is_boot_enabled(xe)) 1207 return -EBUSY; 1208 1209 err = xe_pm_suspend(xe); 1210 if (err) 1211 return err; 1212 1213 /* 1214 * Enabling D3Cold is needed for S2Idle/S0ix. 1215 * It is save to allow here since xe_pm_suspend has evicted 1216 * the local memory and the direct complete optimization is disabled. 1217 */ 1218 d3cold_toggle(pdev, D3COLD_ENABLE); 1219 1220 pci_save_state(pdev); 1221 pci_disable_device(pdev); 1222 pci_set_power_state(pdev, PCI_D3cold); 1223 1224 return 0; 1225 } 1226 1227 static int xe_pci_resume(struct device *dev) 1228 { 1229 struct pci_dev *pdev = to_pci_dev(dev); 1230 int err; 1231 1232 /* Give back the D3Cold decision to the runtime P M*/ 1233 d3cold_toggle(pdev, D3COLD_DISABLE); 1234 1235 err = pci_set_power_state(pdev, PCI_D0); 1236 if (err) 1237 return err; 1238 1239 pci_restore_state(pdev); 1240 1241 err = pci_enable_device(pdev); 1242 if (err) 1243 return err; 1244 1245 pci_set_master(pdev); 1246 1247 err = xe_pm_resume(pdev_to_xe_device(pdev)); 1248 if (err) 1249 return err; 1250 1251 return 0; 1252 } 1253 1254 static int xe_pci_runtime_suspend(struct device *dev) 1255 { 1256 struct pci_dev *pdev = to_pci_dev(dev); 1257 struct xe_device *xe = pdev_to_xe_device(pdev); 1258 int err; 1259 1260 /* 1261 * We hold an additional reference to the runtime PM to keep PF in D0 1262 * during VFs lifetime, as our VFs do not implement the PM capability. 1263 * This means we should never be runtime suspending as long as VFs are 1264 * enabled. 1265 */ 1266 xe_assert(xe, !IS_SRIOV_VF(xe)); 1267 xe_assert(xe, !pci_num_vf(pdev)); 1268 1269 err = xe_pm_runtime_suspend(xe); 1270 if (err) 1271 return err; 1272 1273 pci_save_state(pdev); 1274 1275 if (xe->d3cold.allowed) { 1276 d3cold_toggle(pdev, D3COLD_ENABLE); 1277 pci_disable_device(pdev); 1278 pci_ignore_hotplug(pdev); 1279 pci_set_power_state(pdev, PCI_D3cold); 1280 } else { 1281 d3cold_toggle(pdev, D3COLD_DISABLE); 1282 pci_set_power_state(pdev, PCI_D3hot); 1283 } 1284 1285 return 0; 1286 } 1287 1288 static int xe_pci_runtime_resume(struct device *dev) 1289 { 1290 struct pci_dev *pdev = to_pci_dev(dev); 1291 struct xe_device *xe = pdev_to_xe_device(pdev); 1292 int err; 1293 1294 err = pci_set_power_state(pdev, PCI_D0); 1295 if (err) 1296 return err; 1297 1298 pci_restore_state(pdev); 1299 1300 if (xe->d3cold.allowed) { 1301 err = pci_enable_device(pdev); 1302 if (err) 1303 return err; 1304 1305 pci_set_master(pdev); 1306 } 1307 1308 return xe_pm_runtime_resume(xe); 1309 } 1310 1311 static int xe_pci_runtime_idle(struct device *dev) 1312 { 1313 struct pci_dev *pdev = to_pci_dev(dev); 1314 struct xe_device *xe = pdev_to_xe_device(pdev); 1315 1316 xe_pm_d3cold_allowed_toggle(xe); 1317 1318 return 0; 1319 } 1320 1321 static const struct dev_pm_ops xe_pm_ops = { 1322 SET_SYSTEM_SLEEP_PM_OPS(xe_pci_suspend, xe_pci_resume) 1323 SET_RUNTIME_PM_OPS(xe_pci_runtime_suspend, xe_pci_runtime_resume, xe_pci_runtime_idle) 1324 }; 1325 #endif 1326 1327 static struct pci_driver xe_pci_driver = { 1328 .name = DRIVER_NAME, 1329 .id_table = pciidlist, 1330 .probe = xe_pci_probe, 1331 .remove = xe_pci_remove, 1332 .shutdown = xe_pci_shutdown, 1333 .sriov_configure = xe_pci_sriov_configure, 1334 #ifdef CONFIG_PM_SLEEP 1335 .driver.pm = &xe_pm_ops, 1336 #endif 1337 }; 1338 1339 /** 1340 * xe_pci_to_pf_device() - Get PF &xe_device. 1341 * @pdev: the VF &pci_dev device 1342 * 1343 * Return: pointer to PF &xe_device, NULL otherwise. 1344 */ 1345 struct xe_device *xe_pci_to_pf_device(struct pci_dev *pdev) 1346 { 1347 struct drm_device *drm; 1348 1349 drm = pci_iov_get_pf_drvdata(pdev, &xe_pci_driver); 1350 if (IS_ERR(drm)) 1351 return NULL; 1352 1353 return to_xe_device(drm); 1354 } 1355 1356 int xe_register_pci_driver(void) 1357 { 1358 return pci_register_driver(&xe_pci_driver); 1359 } 1360 1361 void xe_unregister_pci_driver(void) 1362 { 1363 pci_unregister_driver(&xe_pci_driver); 1364 } 1365 1366 #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST) 1367 #include "tests/xe_pci.c" 1368 #endif 1369