1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 #include "xe_pci.h" 7 8 #include <kunit/static_stub.h> 9 #include <linux/device/driver.h> 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/pm_runtime.h> 13 14 #include <drm/drm_color_mgmt.h> 15 #include <drm/drm_drv.h> 16 #include <drm/intel/pciids.h> 17 18 #include "display/xe_display.h" 19 #include "regs/xe_gt_regs.h" 20 #include "xe_device.h" 21 #include "xe_drv.h" 22 #include "xe_gt.h" 23 #include "xe_gt_sriov_vf.h" 24 #include "xe_guc.h" 25 #include "xe_macros.h" 26 #include "xe_mmio.h" 27 #include "xe_module.h" 28 #include "xe_pci_sriov.h" 29 #include "xe_pci_types.h" 30 #include "xe_pm.h" 31 #include "xe_sriov.h" 32 #include "xe_step.h" 33 #include "xe_survivability_mode.h" 34 #include "xe_tile.h" 35 36 enum toggle_d3cold { 37 D3COLD_DISABLE, 38 D3COLD_ENABLE, 39 }; 40 41 struct xe_subplatform_desc { 42 enum xe_subplatform subplatform; 43 const char *name; 44 const u16 *pciidlist; 45 }; 46 47 struct xe_device_desc { 48 /* Should only ever be set for platforms without GMD_ID */ 49 const struct xe_ip *pre_gmdid_graphics_ip; 50 /* Should only ever be set for platforms without GMD_ID */ 51 const struct xe_ip *pre_gmdid_media_ip; 52 53 const char *platform_name; 54 const struct xe_subplatform_desc *subplatforms; 55 56 enum xe_platform platform; 57 58 u8 dma_mask_size; 59 u8 max_remote_tiles:2; 60 61 u8 require_force_probe:1; 62 u8 is_dgfx:1; 63 64 u8 has_display:1; 65 u8 has_fan_control:1; 66 u8 has_heci_gscfi:1; 67 u8 has_heci_cscfi:1; 68 u8 has_llc:1; 69 u8 has_pxp:1; 70 u8 has_sriov:1; 71 u8 needs_scratch:1; 72 u8 skip_guc_pc:1; 73 u8 skip_mtcfg:1; 74 u8 skip_pcode:1; 75 }; 76 77 __diag_push(); 78 __diag_ignore_all("-Woverride-init", "Allow field overrides in table"); 79 80 #define PLATFORM(x) \ 81 .platform = XE_##x, \ 82 .platform_name = #x 83 84 #define NOP(x) x 85 86 static const struct xe_graphics_desc graphics_xelp = { 87 .hw_engine_mask = BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0), 88 89 .va_bits = 48, 90 .vm_max_level = 3, 91 }; 92 93 #define XE_HP_FEATURES \ 94 .has_range_tlb_invalidation = true, \ 95 .va_bits = 48, \ 96 .vm_max_level = 3 97 98 static const struct xe_graphics_desc graphics_xehpg = { 99 .hw_engine_mask = 100 BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) | 101 BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) | 102 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3), 103 104 XE_HP_FEATURES, 105 .vram_flags = XE_VRAM_FLAGS_NEED64K, 106 107 .has_flat_ccs = 1, 108 }; 109 110 static const struct xe_graphics_desc graphics_xehpc = { 111 .hw_engine_mask = 112 BIT(XE_HW_ENGINE_BCS0) | BIT(XE_HW_ENGINE_BCS1) | 113 BIT(XE_HW_ENGINE_BCS2) | BIT(XE_HW_ENGINE_BCS3) | 114 BIT(XE_HW_ENGINE_BCS4) | BIT(XE_HW_ENGINE_BCS5) | 115 BIT(XE_HW_ENGINE_BCS6) | BIT(XE_HW_ENGINE_BCS7) | 116 BIT(XE_HW_ENGINE_BCS8) | 117 BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) | 118 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3), 119 120 XE_HP_FEATURES, 121 .va_bits = 57, 122 .vm_max_level = 4, 123 .vram_flags = XE_VRAM_FLAGS_NEED64K, 124 125 .has_asid = 1, 126 .has_atomic_enable_pte_bit = 1, 127 .has_usm = 1, 128 }; 129 130 static const struct xe_graphics_desc graphics_xelpg = { 131 .hw_engine_mask = 132 BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) | 133 BIT(XE_HW_ENGINE_CCS0), 134 135 XE_HP_FEATURES, 136 }; 137 138 #define XE2_GFX_FEATURES \ 139 .has_asid = 1, \ 140 .has_atomic_enable_pte_bit = 1, \ 141 .has_flat_ccs = 1, \ 142 .has_indirect_ring_state = 1, \ 143 .has_range_tlb_invalidation = 1, \ 144 .has_usm = 1, \ 145 .has_64bit_timestamp = 1, \ 146 .va_bits = 48, \ 147 .vm_max_level = 4, \ 148 .hw_engine_mask = \ 149 BIT(XE_HW_ENGINE_RCS0) | \ 150 BIT(XE_HW_ENGINE_BCS8) | BIT(XE_HW_ENGINE_BCS0) | \ 151 GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0) 152 153 static const struct xe_graphics_desc graphics_xe2 = { 154 XE2_GFX_FEATURES, 155 }; 156 157 static const struct xe_media_desc media_xem = { 158 .hw_engine_mask = 159 GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) | 160 GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0), 161 }; 162 163 static const struct xe_media_desc media_xelpmp = { 164 .hw_engine_mask = 165 GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) | 166 GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0) | 167 BIT(XE_HW_ENGINE_GSCCS0) 168 }; 169 170 /* Pre-GMDID Graphics IPs */ 171 static const struct xe_ip graphics_ip_xelp = { 1200, "Xe_LP", &graphics_xelp }; 172 static const struct xe_ip graphics_ip_xelpp = { 1210, "Xe_LP+", &graphics_xelp }; 173 static const struct xe_ip graphics_ip_xehpg = { 1255, "Xe_HPG", &graphics_xehpg }; 174 static const struct xe_ip graphics_ip_xehpc = { 1260, "Xe_HPC", &graphics_xehpc }; 175 176 /* GMDID-based Graphics IPs */ 177 static const struct xe_ip graphics_ips[] = { 178 { 1270, "Xe_LPG", &graphics_xelpg }, 179 { 1271, "Xe_LPG", &graphics_xelpg }, 180 { 1274, "Xe_LPG+", &graphics_xelpg }, 181 { 2001, "Xe2_HPG", &graphics_xe2 }, 182 { 2004, "Xe2_LPG", &graphics_xe2 }, 183 { 3000, "Xe3_LPG", &graphics_xe2 }, 184 { 3001, "Xe3_LPG", &graphics_xe2 }, 185 }; 186 187 /* Pre-GMDID Media IPs */ 188 static const struct xe_ip media_ip_xem = { 1200, "Xe_M", &media_xem }; 189 static const struct xe_ip media_ip_xehpm = { 1255, "Xe_HPM", &media_xem }; 190 191 /* GMDID-based Media IPs */ 192 static const struct xe_ip media_ips[] = { 193 { 1300, "Xe_LPM+", &media_xelpmp }, 194 { 1301, "Xe2_HPM", &media_xelpmp }, 195 { 2000, "Xe2_LPM", &media_xelpmp }, 196 { 3000, "Xe3_LPM", &media_xelpmp }, 197 }; 198 199 static const struct xe_device_desc tgl_desc = { 200 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 201 .pre_gmdid_media_ip = &media_ip_xem, 202 PLATFORM(TIGERLAKE), 203 .dma_mask_size = 39, 204 .has_display = true, 205 .has_llc = true, 206 .require_force_probe = true, 207 }; 208 209 static const struct xe_device_desc rkl_desc = { 210 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 211 .pre_gmdid_media_ip = &media_ip_xem, 212 PLATFORM(ROCKETLAKE), 213 .dma_mask_size = 39, 214 .has_display = true, 215 .has_llc = true, 216 .require_force_probe = true, 217 }; 218 219 static const u16 adls_rpls_ids[] = { INTEL_RPLS_IDS(NOP), 0 }; 220 221 static const struct xe_device_desc adl_s_desc = { 222 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 223 .pre_gmdid_media_ip = &media_ip_xem, 224 PLATFORM(ALDERLAKE_S), 225 .dma_mask_size = 39, 226 .has_display = true, 227 .has_llc = true, 228 .require_force_probe = true, 229 .subplatforms = (const struct xe_subplatform_desc[]) { 230 { XE_SUBPLATFORM_ALDERLAKE_S_RPLS, "RPLS", adls_rpls_ids }, 231 {}, 232 }, 233 }; 234 235 static const u16 adlp_rplu_ids[] = { INTEL_RPLU_IDS(NOP), 0 }; 236 237 static const struct xe_device_desc adl_p_desc = { 238 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 239 .pre_gmdid_media_ip = &media_ip_xem, 240 PLATFORM(ALDERLAKE_P), 241 .dma_mask_size = 39, 242 .has_display = true, 243 .has_llc = true, 244 .require_force_probe = true, 245 .subplatforms = (const struct xe_subplatform_desc[]) { 246 { XE_SUBPLATFORM_ALDERLAKE_P_RPLU, "RPLU", adlp_rplu_ids }, 247 {}, 248 }, 249 }; 250 251 static const struct xe_device_desc adl_n_desc = { 252 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 253 .pre_gmdid_media_ip = &media_ip_xem, 254 PLATFORM(ALDERLAKE_N), 255 .dma_mask_size = 39, 256 .has_display = true, 257 .has_llc = true, 258 .require_force_probe = true, 259 }; 260 261 #define DGFX_FEATURES \ 262 .is_dgfx = 1 263 264 static const struct xe_device_desc dg1_desc = { 265 .pre_gmdid_graphics_ip = &graphics_ip_xelpp, 266 .pre_gmdid_media_ip = &media_ip_xem, 267 DGFX_FEATURES, 268 PLATFORM(DG1), 269 .dma_mask_size = 39, 270 .has_display = true, 271 .has_heci_gscfi = 1, 272 .require_force_probe = true, 273 }; 274 275 static const u16 dg2_g10_ids[] = { INTEL_DG2_G10_IDS(NOP), INTEL_ATS_M150_IDS(NOP), 0 }; 276 static const u16 dg2_g11_ids[] = { INTEL_DG2_G11_IDS(NOP), INTEL_ATS_M75_IDS(NOP), 0 }; 277 static const u16 dg2_g12_ids[] = { INTEL_DG2_G12_IDS(NOP), 0 }; 278 279 #define DG2_FEATURES \ 280 DGFX_FEATURES, \ 281 PLATFORM(DG2), \ 282 .has_heci_gscfi = 1, \ 283 .subplatforms = (const struct xe_subplatform_desc[]) { \ 284 { XE_SUBPLATFORM_DG2_G10, "G10", dg2_g10_ids }, \ 285 { XE_SUBPLATFORM_DG2_G11, "G11", dg2_g11_ids }, \ 286 { XE_SUBPLATFORM_DG2_G12, "G12", dg2_g12_ids }, \ 287 { } \ 288 } 289 290 static const struct xe_device_desc ats_m_desc = { 291 .pre_gmdid_graphics_ip = &graphics_ip_xehpg, 292 .pre_gmdid_media_ip = &media_ip_xehpm, 293 .dma_mask_size = 46, 294 .require_force_probe = true, 295 296 DG2_FEATURES, 297 .has_display = false, 298 }; 299 300 static const struct xe_device_desc dg2_desc = { 301 .pre_gmdid_graphics_ip = &graphics_ip_xehpg, 302 .pre_gmdid_media_ip = &media_ip_xehpm, 303 .dma_mask_size = 46, 304 .require_force_probe = true, 305 306 DG2_FEATURES, 307 .has_display = true, 308 .has_fan_control = true, 309 }; 310 311 static const __maybe_unused struct xe_device_desc pvc_desc = { 312 .pre_gmdid_graphics_ip = &graphics_ip_xehpc, 313 DGFX_FEATURES, 314 PLATFORM(PVC), 315 .dma_mask_size = 52, 316 .has_display = false, 317 .has_heci_gscfi = 1, 318 .max_remote_tiles = 1, 319 .require_force_probe = true, 320 }; 321 322 static const struct xe_device_desc mtl_desc = { 323 /* .graphics and .media determined via GMD_ID */ 324 .require_force_probe = true, 325 PLATFORM(METEORLAKE), 326 .dma_mask_size = 46, 327 .has_display = true, 328 .has_pxp = true, 329 }; 330 331 static const struct xe_device_desc lnl_desc = { 332 PLATFORM(LUNARLAKE), 333 .dma_mask_size = 46, 334 .has_display = true, 335 .has_pxp = true, 336 .needs_scratch = true, 337 }; 338 339 static const struct xe_device_desc bmg_desc = { 340 DGFX_FEATURES, 341 PLATFORM(BATTLEMAGE), 342 .dma_mask_size = 46, 343 .has_display = true, 344 .has_fan_control = true, 345 .has_heci_cscfi = 1, 346 .needs_scratch = true, 347 }; 348 349 static const struct xe_device_desc ptl_desc = { 350 PLATFORM(PANTHERLAKE), 351 .dma_mask_size = 46, 352 .has_display = true, 353 .has_sriov = true, 354 .require_force_probe = true, 355 .needs_scratch = true, 356 }; 357 358 #undef PLATFORM 359 __diag_pop(); 360 361 /* 362 * Make sure any device matches here are from most specific to most 363 * general. For example, since the Quanta match is based on the subsystem 364 * and subvendor IDs, we need it to come before the more general IVB 365 * PCI ID matches, otherwise we'll use the wrong info struct above. 366 */ 367 static const struct pci_device_id pciidlist[] = { 368 INTEL_TGL_IDS(INTEL_VGA_DEVICE, &tgl_desc), 369 INTEL_RKL_IDS(INTEL_VGA_DEVICE, &rkl_desc), 370 INTEL_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc), 371 INTEL_ADLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 372 INTEL_ADLN_IDS(INTEL_VGA_DEVICE, &adl_n_desc), 373 INTEL_RPLU_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 374 INTEL_RPLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 375 INTEL_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc), 376 INTEL_DG1_IDS(INTEL_VGA_DEVICE, &dg1_desc), 377 INTEL_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_desc), 378 INTEL_ARL_IDS(INTEL_VGA_DEVICE, &mtl_desc), 379 INTEL_DG2_IDS(INTEL_VGA_DEVICE, &dg2_desc), 380 INTEL_MTL_IDS(INTEL_VGA_DEVICE, &mtl_desc), 381 INTEL_LNL_IDS(INTEL_VGA_DEVICE, &lnl_desc), 382 INTEL_BMG_IDS(INTEL_VGA_DEVICE, &bmg_desc), 383 INTEL_PTL_IDS(INTEL_VGA_DEVICE, &ptl_desc), 384 { } 385 }; 386 MODULE_DEVICE_TABLE(pci, pciidlist); 387 388 /* is device_id present in comma separated list of ids */ 389 static bool device_id_in_list(u16 device_id, const char *devices, bool negative) 390 { 391 char *s, *p, *tok; 392 bool ret; 393 394 if (!devices || !*devices) 395 return false; 396 397 /* match everything */ 398 if (negative && strcmp(devices, "!*") == 0) 399 return true; 400 if (!negative && strcmp(devices, "*") == 0) 401 return true; 402 403 s = kstrdup(devices, GFP_KERNEL); 404 if (!s) 405 return false; 406 407 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) { 408 u16 val; 409 410 if (negative && tok[0] == '!') 411 tok++; 412 else if ((negative && tok[0] != '!') || 413 (!negative && tok[0] == '!')) 414 continue; 415 416 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) { 417 ret = true; 418 break; 419 } 420 } 421 422 kfree(s); 423 424 return ret; 425 } 426 427 static bool id_forced(u16 device_id) 428 { 429 return device_id_in_list(device_id, xe_modparam.force_probe, false); 430 } 431 432 static bool id_blocked(u16 device_id) 433 { 434 return device_id_in_list(device_id, xe_modparam.force_probe, true); 435 } 436 437 static const struct xe_subplatform_desc * 438 find_subplatform(const struct xe_device *xe, const struct xe_device_desc *desc) 439 { 440 const struct xe_subplatform_desc *sp; 441 const u16 *id; 442 443 for (sp = desc->subplatforms; sp && sp->subplatform; sp++) 444 for (id = sp->pciidlist; *id; id++) 445 if (*id == xe->info.devid) 446 return sp; 447 448 return NULL; 449 } 450 451 enum xe_gmdid_type { 452 GMDID_GRAPHICS, 453 GMDID_MEDIA 454 }; 455 456 static void read_gmdid(struct xe_device *xe, enum xe_gmdid_type type, u32 *ver, u32 *revid) 457 { 458 struct xe_mmio *mmio = xe_root_tile_mmio(xe); 459 struct xe_reg gmdid_reg = GMD_ID; 460 u32 val; 461 462 KUNIT_STATIC_STUB_REDIRECT(read_gmdid, xe, type, ver, revid); 463 464 if (IS_SRIOV_VF(xe)) { 465 struct xe_gt *gt = xe_root_mmio_gt(xe); 466 467 /* 468 * To get the value of the GMDID register, VFs must obtain it 469 * from the GuC using MMIO communication. 470 * 471 * Note that at this point the xe_gt is not fully uninitialized 472 * and only basic access to MMIO registers is possible. To use 473 * our existing GuC communication functions we must perform at 474 * least basic xe_gt and xe_guc initialization. 475 * 476 * Since to obtain the value of GMDID_MEDIA we need to use the 477 * media GuC, temporarily tweak the gt type. 478 */ 479 xe_gt_assert(gt, gt->info.type == XE_GT_TYPE_UNINITIALIZED); 480 481 if (type == GMDID_MEDIA) { 482 gt->info.id = 1; 483 gt->info.type = XE_GT_TYPE_MEDIA; 484 } else { 485 gt->info.id = 0; 486 gt->info.type = XE_GT_TYPE_MAIN; 487 } 488 489 xe_gt_mmio_init(gt); 490 xe_guc_comm_init_early(>->uc.guc); 491 492 /* Don't bother with GMDID if failed to negotiate the GuC ABI */ 493 val = xe_gt_sriov_vf_bootstrap(gt) ? 0 : xe_gt_sriov_vf_gmdid(gt); 494 495 /* 496 * Only undo xe_gt.info here, the remaining changes made above 497 * will be overwritten as part of the regular initialization. 498 */ 499 gt->info.id = 0; 500 gt->info.type = XE_GT_TYPE_UNINITIALIZED; 501 } else { 502 /* 503 * GMD_ID is a GT register, but at this point in the driver 504 * init we haven't fully initialized the GT yet so we need to 505 * read the register with the tile's MMIO accessor. That means 506 * we need to apply the GSI offset manually since it won't get 507 * automatically added as it would if we were using a GT mmio 508 * accessor. 509 */ 510 if (type == GMDID_MEDIA) 511 gmdid_reg.addr += MEDIA_GT_GSI_OFFSET; 512 513 val = xe_mmio_read32(mmio, gmdid_reg); 514 } 515 516 *ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val) * 100 + REG_FIELD_GET(GMD_ID_RELEASE_MASK, val); 517 *revid = REG_FIELD_GET(GMD_ID_REVID, val); 518 } 519 520 /* 521 * Read IP version from hardware and select graphics/media IP descriptors 522 * based on the result. 523 */ 524 static void handle_gmdid(struct xe_device *xe, 525 const struct xe_ip **graphics_ip, 526 const struct xe_ip **media_ip, 527 u32 *graphics_revid, 528 u32 *media_revid) 529 { 530 u32 ver; 531 532 *graphics_ip = NULL; 533 *media_ip = NULL; 534 535 read_gmdid(xe, GMDID_GRAPHICS, &ver, graphics_revid); 536 537 for (int i = 0; i < ARRAY_SIZE(graphics_ips); i++) { 538 if (ver == graphics_ips[i].verx100) { 539 *graphics_ip = &graphics_ips[i]; 540 541 break; 542 } 543 } 544 545 if (!*graphics_ip) { 546 drm_err(&xe->drm, "Hardware reports unknown graphics version %u.%02u\n", 547 ver / 100, ver % 100); 548 } 549 550 read_gmdid(xe, GMDID_MEDIA, &ver, media_revid); 551 /* Media may legitimately be fused off / not present */ 552 if (ver == 0) 553 return; 554 555 for (int i = 0; i < ARRAY_SIZE(media_ips); i++) { 556 if (ver == media_ips[i].verx100) { 557 *media_ip = &media_ips[i]; 558 559 break; 560 } 561 } 562 563 if (!*media_ip) { 564 drm_err(&xe->drm, "Hardware reports unknown media version %u.%02u\n", 565 ver / 100, ver % 100); 566 } 567 } 568 569 /* 570 * Initialize device info content that only depends on static driver_data 571 * passed to the driver at probe time from PCI ID table. 572 */ 573 static int xe_info_init_early(struct xe_device *xe, 574 const struct xe_device_desc *desc, 575 const struct xe_subplatform_desc *subplatform_desc) 576 { 577 int err; 578 579 xe->info.platform_name = desc->platform_name; 580 xe->info.platform = desc->platform; 581 xe->info.subplatform = subplatform_desc ? 582 subplatform_desc->subplatform : XE_SUBPLATFORM_NONE; 583 584 xe->info.dma_mask_size = desc->dma_mask_size; 585 xe->info.is_dgfx = desc->is_dgfx; 586 xe->info.has_fan_control = desc->has_fan_control; 587 xe->info.has_heci_gscfi = desc->has_heci_gscfi; 588 xe->info.has_heci_cscfi = desc->has_heci_cscfi; 589 xe->info.has_llc = desc->has_llc; 590 xe->info.has_pxp = desc->has_pxp; 591 xe->info.has_sriov = desc->has_sriov; 592 xe->info.skip_guc_pc = desc->skip_guc_pc; 593 xe->info.skip_mtcfg = desc->skip_mtcfg; 594 xe->info.skip_pcode = desc->skip_pcode; 595 xe->info.needs_scratch = desc->needs_scratch; 596 597 xe->info.probe_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) && 598 xe_modparam.probe_display && 599 desc->has_display; 600 xe->info.tile_count = 1 + desc->max_remote_tiles; 601 602 err = xe_tile_init_early(xe_device_get_root_tile(xe), xe, 0); 603 if (err) 604 return err; 605 606 return 0; 607 } 608 609 /* 610 * Initialize device info content that does require knowledge about 611 * graphics / media IP version. 612 * Make sure that GT / tile structures allocated by the driver match the data 613 * present in device info. 614 */ 615 static int xe_info_init(struct xe_device *xe, 616 const struct xe_device_desc *desc) 617 { 618 u32 graphics_gmdid_revid = 0, media_gmdid_revid = 0; 619 const struct xe_ip *graphics_ip; 620 const struct xe_ip *media_ip; 621 const struct xe_graphics_desc *graphics_desc; 622 const struct xe_media_desc *media_desc; 623 struct xe_tile *tile; 624 struct xe_gt *gt; 625 u8 id; 626 627 /* 628 * If this platform supports GMD_ID, we'll detect the proper IP 629 * descriptor to use from hardware registers. 630 * desc->pre_gmdid_graphics_ip will only ever be set at this point for 631 * platforms before GMD_ID. In that case the IP descriptions and 632 * versions are simply derived from that. 633 */ 634 if (desc->pre_gmdid_graphics_ip) { 635 graphics_ip = desc->pre_gmdid_graphics_ip; 636 media_ip = desc->pre_gmdid_media_ip; 637 xe->info.step = xe_step_pre_gmdid_get(xe); 638 } else { 639 xe_assert(xe, !desc->pre_gmdid_media_ip); 640 handle_gmdid(xe, &graphics_ip, &media_ip, 641 &graphics_gmdid_revid, &media_gmdid_revid); 642 xe->info.step = xe_step_gmdid_get(xe, 643 graphics_gmdid_revid, 644 media_gmdid_revid); 645 } 646 647 /* 648 * If we couldn't detect the graphics IP, that's considered a fatal 649 * error and we should abort driver load. Failing to detect media 650 * IP is non-fatal; we'll just proceed without enabling media support. 651 */ 652 if (!graphics_ip) 653 return -ENODEV; 654 655 xe->info.graphics_verx100 = graphics_ip->verx100; 656 xe->info.graphics_name = graphics_ip->name; 657 graphics_desc = graphics_ip->desc; 658 659 if (media_ip) { 660 xe->info.media_verx100 = media_ip->verx100; 661 xe->info.media_name = media_ip->name; 662 media_desc = media_ip->desc; 663 } else { 664 xe->info.media_name = "none"; 665 media_desc = NULL; 666 } 667 668 xe->info.vram_flags = graphics_desc->vram_flags; 669 xe->info.va_bits = graphics_desc->va_bits; 670 xe->info.vm_max_level = graphics_desc->vm_max_level; 671 xe->info.has_asid = graphics_desc->has_asid; 672 xe->info.has_atomic_enable_pte_bit = graphics_desc->has_atomic_enable_pte_bit; 673 if (xe->info.platform != XE_PVC) 674 xe->info.has_device_atomics_on_smem = 1; 675 676 /* Runtime detection may change this later */ 677 xe->info.has_flat_ccs = graphics_desc->has_flat_ccs; 678 679 xe->info.has_range_tlb_invalidation = graphics_desc->has_range_tlb_invalidation; 680 xe->info.has_usm = graphics_desc->has_usm; 681 xe->info.has_64bit_timestamp = graphics_desc->has_64bit_timestamp; 682 683 for_each_remote_tile(tile, xe, id) { 684 int err; 685 686 err = xe_tile_init_early(tile, xe, id); 687 if (err) 688 return err; 689 } 690 691 /* 692 * All platforms have at least one primary GT. Any platform with media 693 * version 13 or higher has an additional dedicated media GT. And 694 * depending on the graphics IP there may be additional "remote tiles." 695 * All of these together determine the overall GT count. 696 */ 697 for_each_tile(tile, xe, id) { 698 gt = tile->primary_gt; 699 gt->info.id = xe->info.gt_count++; 700 gt->info.type = XE_GT_TYPE_MAIN; 701 gt->info.has_indirect_ring_state = graphics_desc->has_indirect_ring_state; 702 gt->info.engine_mask = graphics_desc->hw_engine_mask; 703 704 if (MEDIA_VER(xe) < 13 && media_desc) 705 gt->info.engine_mask |= media_desc->hw_engine_mask; 706 707 if (MEDIA_VER(xe) < 13 || !media_desc) 708 continue; 709 710 /* 711 * Allocate and setup media GT for platforms with standalone 712 * media. 713 */ 714 tile->media_gt = xe_gt_alloc(tile); 715 if (IS_ERR(tile->media_gt)) 716 return PTR_ERR(tile->media_gt); 717 718 gt = tile->media_gt; 719 gt->info.type = XE_GT_TYPE_MEDIA; 720 gt->info.has_indirect_ring_state = media_desc->has_indirect_ring_state; 721 gt->info.engine_mask = media_desc->hw_engine_mask; 722 723 /* 724 * FIXME: At the moment multi-tile and standalone media are 725 * mutually exclusive on current platforms. We'll need to 726 * come up with a better way to number GTs if we ever wind 727 * up with platforms that support both together. 728 */ 729 drm_WARN_ON(&xe->drm, id != 0); 730 gt->info.id = xe->info.gt_count++; 731 } 732 733 return 0; 734 } 735 736 static void xe_pci_remove(struct pci_dev *pdev) 737 { 738 struct xe_device *xe = pdev_to_xe_device(pdev); 739 740 if (IS_SRIOV_PF(xe)) 741 xe_pci_sriov_configure(pdev, 0); 742 743 if (xe_survivability_mode_is_enabled(xe)) 744 return; 745 746 xe_device_remove(xe); 747 xe_pm_fini(xe); 748 } 749 750 /* 751 * Probe the PCI device, initialize various parts of the driver. 752 * 753 * Fault injection is used to test the error paths of some initialization 754 * functions called either directly from xe_pci_probe() or indirectly for 755 * example through xe_device_probe(). Those functions use the kernel fault 756 * injection capabilities infrastructure, see 757 * Documentation/fault-injection/fault-injection.rst for details. The macro 758 * ALLOW_ERROR_INJECTION() is used to conditionally skip function execution 759 * at runtime and use a provided return value. The first requirement for 760 * error injectable functions is proper handling of the error code by the 761 * caller for recovery, which is always the case here. The second 762 * requirement is that no state is changed before the first error return. 763 * It is not strictly fulfilled for all initialization functions using the 764 * ALLOW_ERROR_INJECTION() macro but this is acceptable because for those 765 * error cases at probe time, the error code is simply propagated up by the 766 * caller. Therefore there is no consequence on those specific callers when 767 * function error injection skips the whole function. 768 */ 769 static int xe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 770 { 771 const struct xe_device_desc *desc = (const void *)ent->driver_data; 772 const struct xe_subplatform_desc *subplatform_desc; 773 struct xe_device *xe; 774 int err; 775 776 if (desc->require_force_probe && !id_forced(pdev->device)) { 777 dev_info(&pdev->dev, 778 "Your graphics device %04x is not officially supported\n" 779 "by xe driver in this kernel version. To force Xe probe,\n" 780 "use xe.force_probe='%04x' and i915.force_probe='!%04x'\n" 781 "module parameters or CONFIG_DRM_XE_FORCE_PROBE='%04x' and\n" 782 "CONFIG_DRM_I915_FORCE_PROBE='!%04x' configuration options.\n", 783 pdev->device, pdev->device, pdev->device, 784 pdev->device, pdev->device); 785 return -ENODEV; 786 } 787 788 if (id_blocked(pdev->device)) { 789 dev_info(&pdev->dev, "Probe blocked for device [%04x:%04x].\n", 790 pdev->vendor, pdev->device); 791 return -ENODEV; 792 } 793 794 if (xe_display_driver_probe_defer(pdev)) 795 return -EPROBE_DEFER; 796 797 err = pcim_enable_device(pdev); 798 if (err) 799 return err; 800 801 xe = xe_device_create(pdev, ent); 802 if (IS_ERR(xe)) 803 return PTR_ERR(xe); 804 805 pci_set_drvdata(pdev, &xe->drm); 806 807 xe_pm_assert_unbounded_bridge(xe); 808 subplatform_desc = find_subplatform(xe, desc); 809 810 pci_set_master(pdev); 811 812 err = xe_info_init_early(xe, desc, subplatform_desc); 813 if (err) 814 return err; 815 816 err = xe_device_probe_early(xe); 817 /* 818 * In Boot Survivability mode, no drm card is exposed and driver 819 * is loaded with bare minimum to allow for firmware to be 820 * flashed through mei. Return success, if survivability mode 821 * is enabled due to pcode failure or configfs being set 822 */ 823 if (xe_survivability_mode_is_enabled(xe)) 824 return 0; 825 826 if (err) 827 return err; 828 829 err = xe_info_init(xe, desc); 830 if (err) 831 return err; 832 833 err = xe_display_probe(xe); 834 if (err) 835 return err; 836 837 drm_dbg(&xe->drm, "%s %s %04x:%04x dgfx:%d gfx:%s (%d.%02d) media:%s (%d.%02d) display:%s dma_m_s:%d tc:%d gscfi:%d cscfi:%d", 838 desc->platform_name, 839 subplatform_desc ? subplatform_desc->name : "", 840 xe->info.devid, xe->info.revid, 841 xe->info.is_dgfx, 842 xe->info.graphics_name, 843 xe->info.graphics_verx100 / 100, 844 xe->info.graphics_verx100 % 100, 845 xe->info.media_name, 846 xe->info.media_verx100 / 100, 847 xe->info.media_verx100 % 100, 848 str_yes_no(xe->info.probe_display), 849 xe->info.dma_mask_size, xe->info.tile_count, 850 xe->info.has_heci_gscfi, xe->info.has_heci_cscfi); 851 852 drm_dbg(&xe->drm, "Stepping = (G:%s, M:%s, B:%s)\n", 853 xe_step_name(xe->info.step.graphics), 854 xe_step_name(xe->info.step.media), 855 xe_step_name(xe->info.step.basedie)); 856 857 drm_dbg(&xe->drm, "SR-IOV support: %s (mode: %s)\n", 858 str_yes_no(xe_device_has_sriov(xe)), 859 xe_sriov_mode_to_string(xe_device_sriov_mode(xe))); 860 861 err = xe_pm_init_early(xe); 862 if (err) 863 return err; 864 865 err = xe_device_probe(xe); 866 if (err) 867 return err; 868 869 err = xe_pm_init(xe); 870 if (err) 871 goto err_driver_cleanup; 872 873 drm_dbg(&xe->drm, "d3cold: capable=%s\n", 874 str_yes_no(xe->d3cold.capable)); 875 876 return 0; 877 878 err_driver_cleanup: 879 xe_pci_remove(pdev); 880 return err; 881 } 882 883 static void xe_pci_shutdown(struct pci_dev *pdev) 884 { 885 xe_device_shutdown(pdev_to_xe_device(pdev)); 886 } 887 888 #ifdef CONFIG_PM_SLEEP 889 static void d3cold_toggle(struct pci_dev *pdev, enum toggle_d3cold toggle) 890 { 891 struct xe_device *xe = pdev_to_xe_device(pdev); 892 struct pci_dev *root_pdev; 893 894 if (!xe->d3cold.capable) 895 return; 896 897 root_pdev = pcie_find_root_port(pdev); 898 if (!root_pdev) 899 return; 900 901 switch (toggle) { 902 case D3COLD_DISABLE: 903 pci_d3cold_disable(root_pdev); 904 break; 905 case D3COLD_ENABLE: 906 pci_d3cold_enable(root_pdev); 907 break; 908 } 909 } 910 911 static int xe_pci_suspend(struct device *dev) 912 { 913 struct pci_dev *pdev = to_pci_dev(dev); 914 struct xe_device *xe = pdev_to_xe_device(pdev); 915 int err; 916 917 if (xe_survivability_mode_is_enabled(xe)) 918 return -EBUSY; 919 920 err = xe_pm_suspend(xe); 921 if (err) 922 return err; 923 924 /* 925 * Enabling D3Cold is needed for S2Idle/S0ix. 926 * It is save to allow here since xe_pm_suspend has evicted 927 * the local memory and the direct complete optimization is disabled. 928 */ 929 d3cold_toggle(pdev, D3COLD_ENABLE); 930 931 pci_save_state(pdev); 932 pci_disable_device(pdev); 933 pci_set_power_state(pdev, PCI_D3cold); 934 935 return 0; 936 } 937 938 static int xe_pci_resume(struct device *dev) 939 { 940 struct pci_dev *pdev = to_pci_dev(dev); 941 int err; 942 943 /* Give back the D3Cold decision to the runtime P M*/ 944 d3cold_toggle(pdev, D3COLD_DISABLE); 945 946 err = pci_set_power_state(pdev, PCI_D0); 947 if (err) 948 return err; 949 950 pci_restore_state(pdev); 951 952 err = pci_enable_device(pdev); 953 if (err) 954 return err; 955 956 pci_set_master(pdev); 957 958 err = xe_pm_resume(pdev_to_xe_device(pdev)); 959 if (err) 960 return err; 961 962 return 0; 963 } 964 965 static int xe_pci_runtime_suspend(struct device *dev) 966 { 967 struct pci_dev *pdev = to_pci_dev(dev); 968 struct xe_device *xe = pdev_to_xe_device(pdev); 969 int err; 970 971 err = xe_pm_runtime_suspend(xe); 972 if (err) 973 return err; 974 975 pci_save_state(pdev); 976 977 if (xe->d3cold.allowed) { 978 d3cold_toggle(pdev, D3COLD_ENABLE); 979 pci_disable_device(pdev); 980 pci_ignore_hotplug(pdev); 981 pci_set_power_state(pdev, PCI_D3cold); 982 } else { 983 d3cold_toggle(pdev, D3COLD_DISABLE); 984 pci_set_power_state(pdev, PCI_D3hot); 985 } 986 987 return 0; 988 } 989 990 static int xe_pci_runtime_resume(struct device *dev) 991 { 992 struct pci_dev *pdev = to_pci_dev(dev); 993 struct xe_device *xe = pdev_to_xe_device(pdev); 994 int err; 995 996 err = pci_set_power_state(pdev, PCI_D0); 997 if (err) 998 return err; 999 1000 pci_restore_state(pdev); 1001 1002 if (xe->d3cold.allowed) { 1003 err = pci_enable_device(pdev); 1004 if (err) 1005 return err; 1006 1007 pci_set_master(pdev); 1008 } 1009 1010 return xe_pm_runtime_resume(xe); 1011 } 1012 1013 static int xe_pci_runtime_idle(struct device *dev) 1014 { 1015 struct pci_dev *pdev = to_pci_dev(dev); 1016 struct xe_device *xe = pdev_to_xe_device(pdev); 1017 1018 xe_pm_d3cold_allowed_toggle(xe); 1019 1020 return 0; 1021 } 1022 1023 static const struct dev_pm_ops xe_pm_ops = { 1024 SET_SYSTEM_SLEEP_PM_OPS(xe_pci_suspend, xe_pci_resume) 1025 SET_RUNTIME_PM_OPS(xe_pci_runtime_suspend, xe_pci_runtime_resume, xe_pci_runtime_idle) 1026 }; 1027 #endif 1028 1029 static struct pci_driver xe_pci_driver = { 1030 .name = DRIVER_NAME, 1031 .id_table = pciidlist, 1032 .probe = xe_pci_probe, 1033 .remove = xe_pci_remove, 1034 .shutdown = xe_pci_shutdown, 1035 .sriov_configure = xe_pci_sriov_configure, 1036 #ifdef CONFIG_PM_SLEEP 1037 .driver.pm = &xe_pm_ops, 1038 #endif 1039 }; 1040 1041 int xe_register_pci_driver(void) 1042 { 1043 return pci_register_driver(&xe_pci_driver); 1044 } 1045 1046 void xe_unregister_pci_driver(void) 1047 { 1048 pci_unregister_driver(&xe_pci_driver); 1049 } 1050 1051 #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST) 1052 #include "tests/xe_pci.c" 1053 #endif 1054