1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 #include "xe_pci.h" 7 8 #include <kunit/static_stub.h> 9 #include <linux/device/driver.h> 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/pm_runtime.h> 13 14 #include <drm/drm_color_mgmt.h> 15 #include <drm/drm_drv.h> 16 #include <drm/intel/pciids.h> 17 18 #include "display/xe_display.h" 19 #include "regs/xe_gt_regs.h" 20 #include "regs/xe_regs.h" 21 #include "xe_configfs.h" 22 #include "xe_device.h" 23 #include "xe_drv.h" 24 #include "xe_gt.h" 25 #include "xe_gt_sriov_vf.h" 26 #include "xe_guc.h" 27 #include "xe_mmio.h" 28 #include "xe_module.h" 29 #include "xe_pci_rebar.h" 30 #include "xe_pci_sriov.h" 31 #include "xe_pci_types.h" 32 #include "xe_pm.h" 33 #include "xe_printk.h" 34 #include "xe_sriov.h" 35 #include "xe_step.h" 36 #include "xe_survivability_mode.h" 37 #include "xe_tile.h" 38 39 enum toggle_d3cold { 40 D3COLD_DISABLE, 41 D3COLD_ENABLE, 42 }; 43 44 __diag_push(); 45 __diag_ignore_all("-Woverride-init", "Allow field overrides in table"); 46 47 #define PLATFORM(x) \ 48 .platform = XE_##x, \ 49 .platform_name = #x 50 51 #define NOP(x) x 52 53 static const struct xe_graphics_desc graphics_xelp = { 54 .hw_engine_mask = BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0), 55 .num_geometry_xecore_fuse_regs = 1, 56 }; 57 58 #define XE_HP_FEATURES \ 59 .has_range_tlb_inval = true 60 61 static const struct xe_graphics_desc graphics_xehpg = { 62 .hw_engine_mask = 63 BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) | 64 BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) | 65 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3), 66 .num_geometry_xecore_fuse_regs = 1, 67 .num_compute_xecore_fuse_regs = 1, 68 69 XE_HP_FEATURES, 70 }; 71 72 static const struct xe_graphics_desc graphics_xehpc = { 73 .hw_engine_mask = 74 BIT(XE_HW_ENGINE_BCS0) | BIT(XE_HW_ENGINE_BCS1) | 75 BIT(XE_HW_ENGINE_BCS2) | BIT(XE_HW_ENGINE_BCS3) | 76 BIT(XE_HW_ENGINE_BCS4) | BIT(XE_HW_ENGINE_BCS5) | 77 BIT(XE_HW_ENGINE_BCS6) | BIT(XE_HW_ENGINE_BCS7) | 78 BIT(XE_HW_ENGINE_BCS8) | 79 BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) | 80 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3), 81 82 XE_HP_FEATURES, 83 84 .has_access_counter = 1, 85 .has_asid = 1, 86 .has_atomic_enable_pte_bit = 1, 87 .has_usm = 1, 88 .num_compute_xecore_fuse_regs = 2, 89 }; 90 91 static const struct xe_graphics_desc graphics_xelpg = { 92 .hw_engine_mask = 93 BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) | 94 BIT(XE_HW_ENGINE_CCS0), 95 .num_geometry_xecore_fuse_regs = 1, 96 .num_compute_xecore_fuse_regs = 1, 97 98 XE_HP_FEATURES, 99 }; 100 101 #define XE2_GFX_FEATURES \ 102 .has_access_counter = 1, \ 103 .has_asid = 1, \ 104 .has_atomic_enable_pte_bit = 1, \ 105 .has_range_tlb_inval = 1, \ 106 .has_usm = 1, \ 107 .has_64bit_timestamp = 1, \ 108 .hw_engine_mask = \ 109 BIT(XE_HW_ENGINE_RCS0) | \ 110 BIT(XE_HW_ENGINE_BCS8) | BIT(XE_HW_ENGINE_BCS0) | \ 111 GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0) 112 113 static const struct xe_graphics_desc graphics_xe2 = { 114 XE2_GFX_FEATURES, 115 .num_geometry_xecore_fuse_regs = 3, 116 .num_compute_xecore_fuse_regs = 3, 117 }; 118 119 static const struct xe_graphics_desc graphics_xe3p_lpg = { 120 XE2_GFX_FEATURES, 121 .has_indirect_ring_state = 1, 122 .multi_queue_engine_class_mask = BIT(XE_ENGINE_CLASS_COPY) | BIT(XE_ENGINE_CLASS_COMPUTE), 123 .num_geometry_xecore_fuse_regs = 3, 124 .num_compute_xecore_fuse_regs = 3, 125 }; 126 127 static const struct xe_graphics_desc graphics_xe3p_xpc = { 128 XE2_GFX_FEATURES, 129 .has_access_counter = 0, 130 .has_indirect_ring_state = 1, 131 .hw_engine_mask = 132 GENMASK(XE_HW_ENGINE_BCS8, XE_HW_ENGINE_BCS1) | 133 GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0), 134 .multi_queue_engine_class_mask = BIT(XE_ENGINE_CLASS_COPY) | 135 BIT(XE_ENGINE_CLASS_COMPUTE), 136 .num_geometry_xecore_fuse_regs = 4, 137 .num_compute_xecore_fuse_regs = 4, 138 }; 139 140 static const struct xe_media_desc media_xem = { 141 .hw_engine_mask = 142 GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) | 143 GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0), 144 }; 145 146 static const struct xe_media_desc media_xelpmp = { 147 .hw_engine_mask = 148 GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) | 149 GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0) | 150 BIT(XE_HW_ENGINE_GSCCS0) 151 }; 152 153 /* Pre-GMDID Graphics IPs */ 154 static const struct xe_ip graphics_ip_xelp = { 1200, "Xe_LP", &graphics_xelp }; 155 static const struct xe_ip graphics_ip_xelpp = { 1210, "Xe_LP+", &graphics_xelp }; 156 static const struct xe_ip graphics_ip_xehpg = { 1255, "Xe_HPG", &graphics_xehpg }; 157 static const struct xe_ip graphics_ip_xehpc = { 1260, "Xe_HPC", &graphics_xehpc }; 158 159 /* GMDID-based Graphics IPs */ 160 static const struct xe_ip graphics_ips[] = { 161 { 1270, "Xe_LPG", &graphics_xelpg }, 162 { 1271, "Xe_LPG", &graphics_xelpg }, 163 { 1274, "Xe_LPG+", &graphics_xelpg }, 164 { 2001, "Xe2_HPG", &graphics_xe2 }, 165 { 2002, "Xe2_HPG", &graphics_xe2 }, 166 { 2004, "Xe2_LPG", &graphics_xe2 }, 167 { 3000, "Xe3_LPG", &graphics_xe2 }, 168 { 3001, "Xe3_LPG", &graphics_xe2 }, 169 { 3003, "Xe3_LPG", &graphics_xe2 }, 170 { 3004, "Xe3_LPG", &graphics_xe2 }, 171 { 3005, "Xe3_LPG", &graphics_xe2 }, 172 { 3510, "Xe3p_LPG", &graphics_xe3p_lpg }, 173 { 3511, "Xe3p_XPC", &graphics_xe3p_xpc }, 174 }; 175 176 /* Pre-GMDID Media IPs */ 177 static const struct xe_ip media_ip_xem = { 1200, "Xe_M", &media_xem }; 178 static const struct xe_ip media_ip_xehpm = { 1255, "Xe_HPM", &media_xem }; 179 180 /* GMDID-based Media IPs */ 181 static const struct xe_ip media_ips[] = { 182 { 1300, "Xe_LPM+", &media_xelpmp }, 183 { 1301, "Xe2_HPM", &media_xelpmp }, 184 { 2000, "Xe2_LPM", &media_xelpmp }, 185 { 3000, "Xe3_LPM", &media_xelpmp }, 186 { 3002, "Xe3_LPM", &media_xelpmp }, 187 { 3500, "Xe3p_LPM", &media_xelpmp }, 188 { 3503, "Xe3p_HPM", &media_xelpmp }, 189 }; 190 191 #define MULTI_LRC_MASK \ 192 .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE) | \ 193 BIT(XE_ENGINE_CLASS_VIDEO_ENHANCE) 194 195 static const struct xe_device_desc tgl_desc = { 196 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 197 .pre_gmdid_media_ip = &media_ip_xem, 198 PLATFORM(TIGERLAKE), 199 .dma_mask_size = 39, 200 .has_cached_pt = true, 201 .has_display = true, 202 .has_llc = true, 203 .has_sriov = true, 204 .max_gt_per_tile = 1, 205 MULTI_LRC_MASK, 206 .require_force_probe = true, 207 .va_bits = 48, 208 .vm_max_level = 3, 209 }; 210 211 static const struct xe_device_desc rkl_desc = { 212 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 213 .pre_gmdid_media_ip = &media_ip_xem, 214 PLATFORM(ROCKETLAKE), 215 .dma_mask_size = 39, 216 .has_cached_pt = true, 217 .has_display = true, 218 .has_llc = true, 219 .max_gt_per_tile = 1, 220 MULTI_LRC_MASK, 221 .require_force_probe = true, 222 .va_bits = 48, 223 .vm_max_level = 3, 224 }; 225 226 static const u16 adls_rpls_ids[] = { INTEL_RPLS_IDS(NOP), 0 }; 227 228 static const struct xe_device_desc adl_s_desc = { 229 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 230 .pre_gmdid_media_ip = &media_ip_xem, 231 PLATFORM(ALDERLAKE_S), 232 .dma_mask_size = 39, 233 .has_cached_pt = true, 234 .has_display = true, 235 .has_llc = true, 236 .has_sriov = true, 237 .max_gt_per_tile = 1, 238 MULTI_LRC_MASK, 239 .require_force_probe = true, 240 .subplatforms = (const struct xe_subplatform_desc[]) { 241 { XE_SUBPLATFORM_ALDERLAKE_S_RPLS, "RPLS", adls_rpls_ids }, 242 {}, 243 }, 244 .va_bits = 48, 245 .vm_max_level = 3, 246 }; 247 248 static const u16 adlp_rplu_ids[] = { INTEL_RPLU_IDS(NOP), 0 }; 249 250 static const struct xe_device_desc adl_p_desc = { 251 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 252 .pre_gmdid_media_ip = &media_ip_xem, 253 PLATFORM(ALDERLAKE_P), 254 .dma_mask_size = 39, 255 .has_cached_pt = true, 256 .has_display = true, 257 .has_llc = true, 258 .has_sriov = true, 259 .max_gt_per_tile = 1, 260 MULTI_LRC_MASK, 261 .require_force_probe = true, 262 .subplatforms = (const struct xe_subplatform_desc[]) { 263 { XE_SUBPLATFORM_ALDERLAKE_P_RPLU, "RPLU", adlp_rplu_ids }, 264 {}, 265 }, 266 .va_bits = 48, 267 .vm_max_level = 3, 268 }; 269 270 static const struct xe_device_desc adl_n_desc = { 271 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 272 .pre_gmdid_media_ip = &media_ip_xem, 273 PLATFORM(ALDERLAKE_N), 274 .dma_mask_size = 39, 275 .has_cached_pt = true, 276 .has_display = true, 277 .has_llc = true, 278 .has_sriov = true, 279 .max_gt_per_tile = 1, 280 MULTI_LRC_MASK, 281 .require_force_probe = true, 282 .va_bits = 48, 283 .vm_max_level = 3, 284 }; 285 286 #define DGFX_FEATURES \ 287 .is_dgfx = 1 288 289 static const struct xe_device_desc dg1_desc = { 290 .pre_gmdid_graphics_ip = &graphics_ip_xelpp, 291 .pre_gmdid_media_ip = &media_ip_xem, 292 DGFX_FEATURES, 293 PLATFORM(DG1), 294 .dma_mask_size = 39, 295 .has_display = true, 296 .has_gsc_nvm = 1, 297 .has_heci_gscfi = 1, 298 .max_gt_per_tile = 1, 299 MULTI_LRC_MASK, 300 .require_force_probe = true, 301 .va_bits = 48, 302 .vm_max_level = 3, 303 }; 304 305 static const u16 dg2_g10_ids[] = { INTEL_DG2_G10_IDS(NOP), INTEL_ATS_M150_IDS(NOP), 0 }; 306 static const u16 dg2_g11_ids[] = { INTEL_DG2_G11_IDS(NOP), INTEL_ATS_M75_IDS(NOP), 0 }; 307 static const u16 dg2_g12_ids[] = { INTEL_DG2_G12_IDS(NOP), 0 }; 308 309 #define DG2_FEATURES \ 310 DGFX_FEATURES, \ 311 PLATFORM(DG2), \ 312 .has_flat_ccs = 1, \ 313 .has_gsc_nvm = 1, \ 314 .has_heci_gscfi = 1, \ 315 .subplatforms = (const struct xe_subplatform_desc[]) { \ 316 { XE_SUBPLATFORM_DG2_G10, "G10", dg2_g10_ids }, \ 317 { XE_SUBPLATFORM_DG2_G11, "G11", dg2_g11_ids }, \ 318 { XE_SUBPLATFORM_DG2_G12, "G12", dg2_g12_ids }, \ 319 { } \ 320 }, \ 321 .va_bits = 48, \ 322 .vm_max_level = 3, \ 323 .vram_flags = XE_VRAM_FLAGS_NEED64K 324 325 static const struct xe_device_desc ats_m_desc = { 326 .pre_gmdid_graphics_ip = &graphics_ip_xehpg, 327 .pre_gmdid_media_ip = &media_ip_xehpm, 328 .dma_mask_size = 46, 329 .max_gt_per_tile = 1, 330 MULTI_LRC_MASK, 331 .require_force_probe = true, 332 333 DG2_FEATURES, 334 .has_display = false, 335 .has_sriov = true, 336 }; 337 338 static const struct xe_device_desc dg2_desc = { 339 .pre_gmdid_graphics_ip = &graphics_ip_xehpg, 340 .pre_gmdid_media_ip = &media_ip_xehpm, 341 .dma_mask_size = 46, 342 .max_gt_per_tile = 1, 343 MULTI_LRC_MASK, 344 .require_force_probe = true, 345 346 DG2_FEATURES, 347 .has_display = true, 348 .has_fan_control = true, 349 .has_mbx_power_limits = false, 350 }; 351 352 static const __maybe_unused struct xe_device_desc pvc_desc = { 353 .pre_gmdid_graphics_ip = &graphics_ip_xehpc, 354 DGFX_FEATURES, 355 PLATFORM(PVC), 356 .dma_mask_size = 52, 357 .has_display = false, 358 .has_gsc_nvm = 1, 359 .has_heci_gscfi = 1, 360 .max_gt_per_tile = 1, 361 .max_remote_tiles = 1, 362 MULTI_LRC_MASK, 363 .require_force_probe = true, 364 .va_bits = 57, 365 .vm_max_level = 4, 366 .vram_flags = XE_VRAM_FLAGS_NEED64K, 367 .has_mbx_power_limits = false, 368 }; 369 370 static const struct xe_device_desc mtl_desc = { 371 /* .graphics and .media determined via GMD_ID */ 372 .require_force_probe = true, 373 PLATFORM(METEORLAKE), 374 .dma_mask_size = 46, 375 .has_display = true, 376 .has_pxp = true, 377 .max_gt_per_tile = 2, 378 MULTI_LRC_MASK, 379 .va_bits = 48, 380 .vm_max_level = 3, 381 }; 382 383 static const struct xe_device_desc lnl_desc = { 384 PLATFORM(LUNARLAKE), 385 .dma_mask_size = 46, 386 .has_display = true, 387 .has_flat_ccs = 1, 388 .has_pxp = true, 389 .max_gt_per_tile = 2, 390 MULTI_LRC_MASK, 391 .needs_scratch = true, 392 .va_bits = 48, 393 .vm_max_level = 4, 394 }; 395 396 static const u16 bmg_g21_ids[] = { INTEL_BMG_G21_IDS(NOP), 0 }; 397 398 static const struct xe_device_desc bmg_desc = { 399 DGFX_FEATURES, 400 PLATFORM(BATTLEMAGE), 401 .dma_mask_size = 46, 402 .has_display = true, 403 .has_fan_control = true, 404 .has_flat_ccs = 1, 405 .has_mbx_power_limits = true, 406 .has_mbx_thermal_info = true, 407 .has_gsc_nvm = 1, 408 .has_heci_cscfi = 1, 409 .has_i2c = true, 410 .has_late_bind = true, 411 .has_pre_prod_wa = 1, 412 .has_soc_remapper_telem = true, 413 .has_sriov = true, 414 .max_gt_per_tile = 2, 415 MULTI_LRC_MASK, 416 .needs_scratch = true, 417 .subplatforms = (const struct xe_subplatform_desc[]) { 418 { XE_SUBPLATFORM_BATTLEMAGE_G21, "G21", bmg_g21_ids }, 419 { } 420 }, 421 .va_bits = 48, 422 .vm_max_level = 4, 423 }; 424 425 static const struct xe_device_desc ptl_desc = { 426 PLATFORM(PANTHERLAKE), 427 .dma_mask_size = 46, 428 .has_display = true, 429 .has_flat_ccs = 1, 430 .has_sriov = true, 431 .has_pre_prod_wa = 1, 432 .has_pxp = true, 433 .max_gt_per_tile = 2, 434 MULTI_LRC_MASK, 435 .needs_scratch = true, 436 .needs_shared_vf_gt_wq = true, 437 .va_bits = 48, 438 .vm_max_level = 4, 439 }; 440 441 static const struct xe_device_desc nvls_desc = { 442 PLATFORM(NOVALAKE_S), 443 .dma_mask_size = 46, 444 .has_display = true, 445 .has_flat_ccs = 1, 446 .has_pre_prod_wa = 1, 447 .max_gt_per_tile = 2, 448 MULTI_LRC_MASK, 449 .require_force_probe = true, 450 .va_bits = 48, 451 .vm_max_level = 4, 452 }; 453 454 static const struct xe_device_desc cri_desc = { 455 DGFX_FEATURES, 456 PLATFORM(CRESCENTISLAND), 457 .dma_mask_size = 52, 458 .has_display = false, 459 .has_flat_ccs = false, 460 .has_gsc_nvm = 1, 461 .has_i2c = true, 462 .has_mbx_power_limits = true, 463 .has_mbx_thermal_info = true, 464 .has_mert = true, 465 .has_pre_prod_wa = 1, 466 .has_soc_remapper_sysctrl = true, 467 .has_soc_remapper_telem = true, 468 .has_sriov = true, 469 .has_sysctrl = true, 470 .max_gt_per_tile = 2, 471 MULTI_LRC_MASK, 472 .require_force_probe = true, 473 .va_bits = 57, 474 .vm_max_level = 4, 475 }; 476 477 static const struct xe_device_desc nvlp_desc = { 478 PLATFORM(NOVALAKE_P), 479 .dma_mask_size = 46, 480 .has_cached_pt = true, 481 .has_display = true, 482 .has_flat_ccs = 1, 483 .has_page_reclaim_hw_assist = true, 484 .has_pre_prod_wa = true, 485 .max_gt_per_tile = 2, 486 MULTI_LRC_MASK, 487 .require_force_probe = true, 488 .va_bits = 48, 489 .vm_max_level = 4, 490 }; 491 492 #undef PLATFORM 493 __diag_pop(); 494 495 /* 496 * Make sure any device matches here are from most specific to most 497 * general. For example, since the Quanta match is based on the subsystem 498 * and subvendor IDs, we need it to come before the more general IVB 499 * PCI ID matches, otherwise we'll use the wrong info struct above. 500 */ 501 static const struct pci_device_id pciidlist[] = { 502 INTEL_TGL_IDS(INTEL_VGA_DEVICE, &tgl_desc), 503 INTEL_RKL_IDS(INTEL_VGA_DEVICE, &rkl_desc), 504 INTEL_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc), 505 INTEL_ADLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 506 INTEL_ADLN_IDS(INTEL_VGA_DEVICE, &adl_n_desc), 507 INTEL_RPLU_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 508 INTEL_RPLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 509 INTEL_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc), 510 INTEL_DG1_IDS(INTEL_VGA_DEVICE, &dg1_desc), 511 INTEL_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_desc), 512 INTEL_ARL_IDS(INTEL_VGA_DEVICE, &mtl_desc), 513 INTEL_DG2_IDS(INTEL_VGA_DEVICE, &dg2_desc), 514 INTEL_MTL_IDS(INTEL_VGA_DEVICE, &mtl_desc), 515 INTEL_LNL_IDS(INTEL_VGA_DEVICE, &lnl_desc), 516 INTEL_BMG_IDS(INTEL_VGA_DEVICE, &bmg_desc), 517 INTEL_PTL_IDS(INTEL_VGA_DEVICE, &ptl_desc), 518 INTEL_WCL_IDS(INTEL_VGA_DEVICE, &ptl_desc), 519 INTEL_NVLS_IDS(INTEL_VGA_DEVICE, &nvls_desc), 520 INTEL_CRI_IDS(INTEL_PCI_DEVICE, &cri_desc), 521 INTEL_NVLP_IDS(INTEL_VGA_DEVICE, &nvlp_desc), 522 { } 523 }; 524 MODULE_DEVICE_TABLE(pci, pciidlist); 525 526 /* is device_id present in comma separated list of ids */ 527 static bool device_id_in_list(u16 device_id, const char *devices, bool negative) 528 { 529 char *s, *p, *tok; 530 bool ret; 531 532 if (!devices || !*devices) 533 return false; 534 535 /* match everything */ 536 if (negative && strcmp(devices, "!*") == 0) 537 return true; 538 if (!negative && strcmp(devices, "*") == 0) 539 return true; 540 541 s = kstrdup(devices, GFP_KERNEL); 542 if (!s) 543 return false; 544 545 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) { 546 u16 val; 547 548 if (negative && tok[0] == '!') 549 tok++; 550 else if ((negative && tok[0] != '!') || 551 (!negative && tok[0] == '!')) 552 continue; 553 554 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) { 555 ret = true; 556 break; 557 } 558 } 559 560 kfree(s); 561 562 return ret; 563 } 564 565 static bool id_forced(u16 device_id) 566 { 567 return device_id_in_list(device_id, xe_modparam.force_probe, false); 568 } 569 570 static bool id_blocked(u16 device_id) 571 { 572 return device_id_in_list(device_id, xe_modparam.force_probe, true); 573 } 574 575 static const struct xe_subplatform_desc * 576 find_subplatform(const struct xe_device *xe, const struct xe_device_desc *desc) 577 { 578 const struct xe_subplatform_desc *sp; 579 const u16 *id; 580 581 for (sp = desc->subplatforms; sp && sp->subplatform; sp++) 582 for (id = sp->pciidlist; *id; id++) 583 if (*id == xe->info.devid) 584 return sp; 585 586 return NULL; 587 } 588 589 enum xe_gmdid_type { 590 GMDID_GRAPHICS, 591 GMDID_MEDIA 592 }; 593 594 static int read_gmdid(struct xe_device *xe, enum xe_gmdid_type type, u32 *ver, u32 *revid) 595 { 596 struct xe_mmio *mmio = xe_root_tile_mmio(xe); 597 struct xe_reg gmdid_reg = GMD_ID; 598 u32 val; 599 600 KUNIT_STATIC_STUB_REDIRECT(read_gmdid, xe, type, ver, revid); 601 602 if (IS_SRIOV_VF(xe)) { 603 /* 604 * To get the value of the GMDID register, VFs must obtain it 605 * from the GuC using MMIO communication. 606 * 607 * Note that at this point the GTs are not initialized and only 608 * tile-level access to MMIO registers is possible. To use our 609 * existing GuC communication functions we must create a dummy 610 * GT structure and perform at least basic xe_gt and xe_guc 611 * initialization. 612 */ 613 struct xe_gt *gt __free(kfree) = NULL; 614 int err; 615 616 /* Don't try to read media ver if media GT is not allowed */ 617 if (type == GMDID_MEDIA && !xe_configfs_media_gt_allowed(to_pci_dev(xe->drm.dev))) { 618 *ver = *revid = 0; 619 return 0; 620 } 621 622 gt = kzalloc(sizeof(*gt), GFP_KERNEL); 623 if (!gt) 624 return -ENOMEM; 625 626 gt->tile = &xe->tiles[0]; 627 if (type == GMDID_MEDIA) { 628 gt->info.id = 1; 629 gt->info.type = XE_GT_TYPE_MEDIA; 630 } else { 631 gt->info.id = 0; 632 gt->info.type = XE_GT_TYPE_MAIN; 633 } 634 635 xe_gt_mmio_init(gt); 636 xe_guc_comm_init_early(>->uc.guc); 637 638 err = xe_gt_sriov_vf_bootstrap(gt); 639 if (err) 640 return err; 641 642 val = xe_gt_sriov_vf_gmdid(gt); 643 } else { 644 /* 645 * GMD_ID is a GT register, but at this point in the driver 646 * init we haven't fully initialized the GT yet so we need to 647 * read the register with the tile's MMIO accessor. That means 648 * we need to apply the GSI offset manually since it won't get 649 * automatically added as it would if we were using a GT mmio 650 * accessor. 651 */ 652 if (type == GMDID_MEDIA) 653 gmdid_reg.addr += MEDIA_GT_GSI_OFFSET; 654 655 val = xe_mmio_read32(mmio, gmdid_reg); 656 } 657 658 *ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val) * 100 + REG_FIELD_GET(GMD_ID_RELEASE_MASK, val); 659 *revid = REG_FIELD_GET(GMD_ID_REVID, val); 660 661 return 0; 662 } 663 664 static const struct xe_ip *find_graphics_ip(unsigned int verx100) 665 { 666 KUNIT_STATIC_STUB_REDIRECT(find_graphics_ip, verx100); 667 668 for (int i = 0; i < ARRAY_SIZE(graphics_ips); i++) 669 if (graphics_ips[i].verx100 == verx100) 670 return &graphics_ips[i]; 671 return NULL; 672 } 673 674 static const struct xe_ip *find_media_ip(unsigned int verx100) 675 { 676 KUNIT_STATIC_STUB_REDIRECT(find_media_ip, verx100); 677 678 for (int i = 0; i < ARRAY_SIZE(media_ips); i++) 679 if (media_ips[i].verx100 == verx100) 680 return &media_ips[i]; 681 return NULL; 682 } 683 684 /* 685 * Read IP version from hardware and select graphics/media IP descriptors 686 * based on the result. 687 */ 688 static int handle_gmdid(struct xe_device *xe, 689 const struct xe_ip **graphics_ip, 690 const struct xe_ip **media_ip, 691 u32 *graphics_revid, 692 u32 *media_revid) 693 { 694 u32 ver; 695 int ret; 696 697 *graphics_ip = NULL; 698 *media_ip = NULL; 699 700 ret = read_gmdid(xe, GMDID_GRAPHICS, &ver, graphics_revid); 701 if (ret) 702 return ret; 703 704 *graphics_ip = find_graphics_ip(ver); 705 if (!*graphics_ip) { 706 drm_err(&xe->drm, "Hardware reports unknown graphics version %u.%02u\n", 707 ver / 100, ver % 100); 708 } 709 710 ret = read_gmdid(xe, GMDID_MEDIA, &ver, media_revid); 711 if (ret) 712 return ret; 713 714 /* Media may legitimately be fused off / not present */ 715 if (ver == 0) 716 return 0; 717 718 *media_ip = find_media_ip(ver); 719 if (!*media_ip) { 720 drm_err(&xe->drm, "Hardware reports unknown media version %u.%02u\n", 721 ver / 100, ver % 100); 722 } 723 724 return 0; 725 } 726 727 /* 728 * Initialize device info content that only depends on static driver_data 729 * passed to the driver at probe time from PCI ID table. 730 */ 731 static int xe_info_init_early(struct xe_device *xe, 732 const struct xe_device_desc *desc, 733 const struct xe_subplatform_desc *subplatform_desc) 734 { 735 int err; 736 737 xe->info.platform_name = desc->platform_name; 738 xe->info.platform = desc->platform; 739 xe->info.subplatform = subplatform_desc ? 740 subplatform_desc->subplatform : XE_SUBPLATFORM_NONE; 741 742 xe->info.dma_mask_size = desc->dma_mask_size; 743 xe->info.va_bits = desc->va_bits; 744 xe->info.vm_max_level = desc->vm_max_level; 745 xe->info.vram_flags = desc->vram_flags; 746 747 xe->info.is_dgfx = desc->is_dgfx; 748 xe->info.has_cached_pt = desc->has_cached_pt; 749 xe->info.has_fan_control = desc->has_fan_control; 750 /* runtime fusing may force flat_ccs to disabled later */ 751 xe->info.has_flat_ccs = desc->has_flat_ccs; 752 xe->info.has_mbx_power_limits = desc->has_mbx_power_limits; 753 xe->info.has_mbx_thermal_info = desc->has_mbx_thermal_info; 754 xe->info.has_gsc_nvm = desc->has_gsc_nvm; 755 xe->info.has_heci_gscfi = desc->has_heci_gscfi; 756 xe->info.has_heci_cscfi = desc->has_heci_cscfi; 757 xe->info.has_i2c = desc->has_i2c; 758 xe->info.has_late_bind = desc->has_late_bind; 759 xe->info.has_llc = desc->has_llc; 760 xe->info.has_mert = desc->has_mert; 761 xe->info.has_page_reclaim_hw_assist = desc->has_page_reclaim_hw_assist; 762 xe->info.has_pre_prod_wa = desc->has_pre_prod_wa; 763 xe->info.has_pxp = desc->has_pxp; 764 xe->info.has_soc_remapper_sysctrl = desc->has_soc_remapper_sysctrl; 765 xe->info.has_soc_remapper_telem = desc->has_soc_remapper_telem; 766 xe->info.has_sriov = xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev)) && 767 desc->has_sriov; 768 xe->info.has_sysctrl = desc->has_sysctrl; 769 xe->info.skip_guc_pc = desc->skip_guc_pc; 770 xe->info.skip_pcode = desc->skip_pcode; 771 xe->info.needs_scratch = desc->needs_scratch; 772 xe->info.needs_shared_vf_gt_wq = desc->needs_shared_vf_gt_wq; 773 xe->info.multi_lrc_mask = desc->multi_lrc_mask; 774 775 xe->info.probe_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) && 776 xe_modparam.probe_display && 777 desc->has_display; 778 779 xe_assert(xe, desc->max_gt_per_tile > 0); 780 xe_assert(xe, desc->max_gt_per_tile <= XE_MAX_GT_PER_TILE); 781 xe->info.max_gt_per_tile = desc->max_gt_per_tile; 782 xe->info.tile_count = 1 + desc->max_remote_tiles; 783 784 xe_step_platform_get(xe); 785 786 err = xe_tile_init_early(xe_device_get_root_tile(xe), xe, 0); 787 if (err) 788 return err; 789 790 return 0; 791 } 792 793 /* 794 * Possibly override number of tile based on configuration register. 795 */ 796 static void xe_info_probe_tile_count(struct xe_device *xe) 797 { 798 struct xe_mmio *mmio; 799 u8 tile_count; 800 u32 mtcfg; 801 802 KUNIT_STATIC_STUB_REDIRECT(xe_info_probe_tile_count, xe); 803 804 /* 805 * Probe for tile count only for platforms that support multiple 806 * tiles. 807 */ 808 if (xe->info.tile_count == 1) 809 return; 810 811 mmio = xe_root_tile_mmio(xe); 812 813 /* 814 * Although the per-tile mmio regs are not yet initialized, this 815 * is fine as it's going to the root tile's mmio, that's 816 * guaranteed to be initialized earlier in xe_mmio_probe_early() 817 */ 818 mtcfg = xe_mmio_read32(mmio, XEHP_MTCFG_ADDR); 819 tile_count = REG_FIELD_GET(TILE_COUNT, mtcfg) + 1; 820 821 if (tile_count < xe->info.tile_count) { 822 drm_info(&xe->drm, "tile_count: %d, reduced_tile_count %d\n", 823 xe->info.tile_count, tile_count); 824 xe->info.tile_count = tile_count; 825 } 826 } 827 828 static struct xe_gt *alloc_primary_gt(struct xe_tile *tile, 829 const struct xe_graphics_desc *graphics_desc, 830 const struct xe_media_desc *media_desc) 831 { 832 struct xe_device *xe = tile_to_xe(tile); 833 struct xe_gt *gt; 834 835 if (!xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev))) { 836 xe_info(xe, "Primary GT disabled via configfs\n"); 837 return NULL; 838 } 839 840 gt = xe_gt_alloc(tile); 841 if (IS_ERR(gt)) 842 return gt; 843 844 gt->info.type = XE_GT_TYPE_MAIN; 845 gt->info.id = tile->id * xe->info.max_gt_per_tile; 846 gt->info.has_indirect_ring_state = graphics_desc->has_indirect_ring_state; 847 gt->info.multi_queue_engine_class_mask = graphics_desc->multi_queue_engine_class_mask; 848 gt->info.engine_mask = graphics_desc->hw_engine_mask; 849 gt->info.num_geometry_xecore_fuse_regs = graphics_desc->num_geometry_xecore_fuse_regs; 850 gt->info.num_compute_xecore_fuse_regs = graphics_desc->num_compute_xecore_fuse_regs; 851 852 /* 853 * Even if the service copy engines wind up being fused off, their 854 * presence in the IP descriptor indicates that the platform supports 855 * Xe2-style MEM_SET and MEM_COPY functionality. 856 */ 857 if (graphics_desc->hw_engine_mask & GENMASK(XE_HW_ENGINE_BCS8, 858 XE_HW_ENGINE_BCS1)) 859 gt->info.has_xe2_blt_instructions = true; 860 861 /* 862 * Before media version 13, the media IP was part of the primary GT 863 * so we need to add the media engines to the primary GT's engine list. 864 */ 865 if (MEDIA_VER(xe) < 13 && media_desc) 866 gt->info.engine_mask |= media_desc->hw_engine_mask; 867 868 return gt; 869 } 870 871 static struct xe_gt *alloc_media_gt(struct xe_tile *tile, 872 const struct xe_media_desc *media_desc) 873 { 874 struct xe_device *xe = tile_to_xe(tile); 875 struct xe_gt *gt; 876 877 if (!xe_configfs_media_gt_allowed(to_pci_dev(xe->drm.dev))) { 878 xe_info(xe, "Media GT disabled via configfs\n"); 879 return NULL; 880 } 881 882 if (MEDIA_VER(xe) < 13 || !media_desc) 883 return NULL; 884 885 gt = xe_gt_alloc(tile); 886 if (IS_ERR(gt)) 887 return gt; 888 889 gt->info.type = XE_GT_TYPE_MEDIA; 890 gt->info.id = tile->id * xe->info.max_gt_per_tile + 1; 891 gt->info.has_indirect_ring_state = media_desc->has_indirect_ring_state; 892 gt->info.engine_mask = media_desc->hw_engine_mask; 893 894 return gt; 895 } 896 897 /* 898 * Initialize device info content that does require knowledge about 899 * graphics / media IP version. 900 * Make sure that GT / tile structures allocated by the driver match the data 901 * present in device info. 902 */ 903 static int xe_info_init(struct xe_device *xe, 904 const struct xe_device_desc *desc) 905 { 906 u32 graphics_gmdid_revid = 0, media_gmdid_revid = 0; 907 const struct xe_ip *graphics_ip; 908 const struct xe_ip *media_ip; 909 const struct xe_graphics_desc *graphics_desc; 910 const struct xe_media_desc *media_desc; 911 struct xe_tile *tile; 912 struct xe_gt *gt; 913 int ret; 914 u8 id; 915 916 /* 917 * If this platform supports GMD_ID, we'll detect the proper IP 918 * descriptor to use from hardware registers. 919 * desc->pre_gmdid_graphics_ip will only ever be set at this point for 920 * platforms before GMD_ID. In that case the IP descriptions and 921 * versions are simply derived from that. 922 */ 923 if (desc->pre_gmdid_graphics_ip) { 924 graphics_ip = desc->pre_gmdid_graphics_ip; 925 media_ip = desc->pre_gmdid_media_ip; 926 xe_step_pre_gmdid_get(xe); 927 } else { 928 xe_assert(xe, !desc->pre_gmdid_media_ip); 929 ret = handle_gmdid(xe, &graphics_ip, &media_ip, 930 &graphics_gmdid_revid, &media_gmdid_revid); 931 if (ret) 932 return ret; 933 934 xe_step_gmdid_get(xe, graphics_gmdid_revid, media_gmdid_revid); 935 } 936 937 /* 938 * If we couldn't detect the graphics IP, that's considered a fatal 939 * error and we should abort driver load. Failing to detect media 940 * IP is non-fatal; we'll just proceed without enabling media support. 941 */ 942 if (!graphics_ip) 943 return -ENODEV; 944 945 xe->info.graphics_verx100 = graphics_ip->verx100; 946 xe->info.graphics_name = graphics_ip->name; 947 graphics_desc = graphics_ip->desc; 948 949 if (media_ip) { 950 xe->info.media_verx100 = media_ip->verx100; 951 xe->info.media_name = media_ip->name; 952 media_desc = media_ip->desc; 953 } else { 954 xe->info.media_name = "none"; 955 media_desc = NULL; 956 } 957 958 xe->info.has_access_counter = graphics_desc->has_access_counter; 959 xe->info.has_asid = graphics_desc->has_asid; 960 xe->info.has_atomic_enable_pte_bit = graphics_desc->has_atomic_enable_pte_bit; 961 if (xe->info.platform != XE_PVC) 962 xe->info.has_device_atomics_on_smem = 1; 963 964 xe->info.has_range_tlb_inval = graphics_desc->has_range_tlb_inval; 965 xe->info.has_ctx_tlb_inval = graphics_desc->has_ctx_tlb_inval; 966 xe->info.has_usm = graphics_desc->has_usm; 967 xe->info.has_64bit_timestamp = graphics_desc->has_64bit_timestamp; 968 xe->info.has_mem_copy_instr = GRAPHICS_VER(xe) >= 20; 969 970 if (IS_SRIOV_VF(xe)) { 971 xe->info.has_sysctrl = 0; 972 xe->info.has_soc_remapper_sysctrl = 0; 973 xe->info.has_soc_remapper_telem = 0; 974 } 975 976 xe_info_probe_tile_count(xe); 977 978 for_each_remote_tile(tile, xe, id) { 979 int err; 980 981 err = xe_tile_init_early(tile, xe, id); 982 if (err) 983 return err; 984 } 985 986 /* Allocate any GT and VRAM structures necessary for the platform. */ 987 for_each_tile(tile, xe, id) { 988 int err; 989 990 err = xe_tile_alloc_vram(tile); 991 if (err) 992 return err; 993 994 tile->primary_gt = alloc_primary_gt(tile, graphics_desc, media_desc); 995 if (IS_ERR(tile->primary_gt)) 996 return PTR_ERR(tile->primary_gt); 997 998 /* 999 * It's not currently possible to probe a device with the 1000 * primary GT disabled. With some work, this may be future in 1001 * the possible for igpu platforms (although probably not for 1002 * dgpu's since access to the primary GT's BCS engines is 1003 * required for VRAM management). 1004 */ 1005 if (!tile->primary_gt) { 1006 drm_err(&xe->drm, "Cannot probe device with without a primary GT\n"); 1007 return -ENODEV; 1008 } 1009 1010 tile->media_gt = alloc_media_gt(tile, media_desc); 1011 if (IS_ERR(tile->media_gt)) 1012 return PTR_ERR(tile->media_gt); 1013 } 1014 1015 /* 1016 * Now that we have tiles and GTs defined, let's loop over valid GTs 1017 * in order to define gt_count. 1018 */ 1019 for_each_gt(gt, xe, id) 1020 xe->info.gt_count++; 1021 1022 return 0; 1023 } 1024 1025 static void xe_pci_remove(struct pci_dev *pdev) 1026 { 1027 struct xe_device *xe = pdev_to_xe_device(pdev); 1028 1029 if (IS_SRIOV_PF(xe)) 1030 xe_pci_sriov_configure(pdev, 0); 1031 1032 if (xe_survivability_mode_is_boot_enabled(xe)) 1033 return; 1034 1035 xe_device_remove(xe); 1036 xe_pm_fini(xe); 1037 } 1038 1039 /* 1040 * Probe the PCI device, initialize various parts of the driver. 1041 * 1042 * Fault injection is used to test the error paths of some initialization 1043 * functions called either directly from xe_pci_probe() or indirectly for 1044 * example through xe_device_probe(). Those functions use the kernel fault 1045 * injection capabilities infrastructure, see 1046 * Documentation/fault-injection/fault-injection.rst for details. The macro 1047 * ALLOW_ERROR_INJECTION() is used to conditionally skip function execution 1048 * at runtime and use a provided return value. The first requirement for 1049 * error injectable functions is proper handling of the error code by the 1050 * caller for recovery, which is always the case here. The second 1051 * requirement is that no state is changed before the first error return. 1052 * It is not strictly fulfilled for all initialization functions using the 1053 * ALLOW_ERROR_INJECTION() macro but this is acceptable because for those 1054 * error cases at probe time, the error code is simply propagated up by the 1055 * caller. Therefore there is no consequence on those specific callers when 1056 * function error injection skips the whole function. 1057 */ 1058 static int xe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1059 { 1060 const struct xe_device_desc *desc = (const void *)ent->driver_data; 1061 const struct xe_subplatform_desc *subplatform_desc; 1062 struct xe_device *xe; 1063 int err; 1064 1065 xe_configfs_check_device(pdev); 1066 1067 if (desc->require_force_probe && !id_forced(pdev->device)) { 1068 dev_info(&pdev->dev, 1069 "Your graphics device %04x is not officially supported\n" 1070 "by xe driver in this kernel version. To force Xe probe,\n" 1071 "use xe.force_probe='%04x' and i915.force_probe='!%04x'\n" 1072 "module parameters or CONFIG_DRM_XE_FORCE_PROBE='%04x' and\n" 1073 "CONFIG_DRM_I915_FORCE_PROBE='!%04x' configuration options.\n", 1074 pdev->device, pdev->device, pdev->device, 1075 pdev->device, pdev->device); 1076 return -ENODEV; 1077 } 1078 1079 if (id_blocked(pdev->device)) { 1080 dev_info(&pdev->dev, "Probe blocked for device [%04x:%04x].\n", 1081 pdev->vendor, pdev->device); 1082 return -ENODEV; 1083 } 1084 1085 if (xe_display_driver_probe_defer(pdev)) 1086 return -EPROBE_DEFER; 1087 1088 err = pcim_enable_device(pdev); 1089 if (err) 1090 return err; 1091 1092 xe = xe_device_create(pdev, ent); 1093 if (IS_ERR(xe)) 1094 return PTR_ERR(xe); 1095 1096 pci_set_drvdata(pdev, &xe->drm); 1097 1098 xe_pm_assert_unbounded_bridge(xe); 1099 subplatform_desc = find_subplatform(xe, desc); 1100 1101 pci_set_master(pdev); 1102 1103 err = xe_info_init_early(xe, desc, subplatform_desc); 1104 if (err) 1105 return err; 1106 1107 xe_pci_rebar_resize(xe); 1108 1109 err = xe_device_probe_early(xe); 1110 /* 1111 * In Boot Survivability mode, no drm card is exposed and driver 1112 * is loaded with bare minimum to allow for firmware to be 1113 * flashed through mei. Return success, if survivability mode 1114 * is enabled due to pcode failure or configfs being set 1115 */ 1116 if (xe_survivability_mode_is_boot_enabled(xe)) 1117 return 0; 1118 1119 if (err) 1120 return err; 1121 1122 err = xe_info_init(xe, desc); 1123 if (err) 1124 return err; 1125 1126 err = xe_display_probe(xe); 1127 if (err) 1128 return err; 1129 1130 drm_dbg(&xe->drm, "%s %s %04x:%04x dgfx:%d gfx:%s (%d.%02d) media:%s (%d.%02d) display:%s dma_m_s:%d tc:%d gscfi:%d cscfi:%d", 1131 desc->platform_name, 1132 subplatform_desc ? subplatform_desc->name : "", 1133 xe->info.devid, xe->info.revid, 1134 xe->info.is_dgfx, 1135 xe->info.graphics_name, 1136 xe->info.graphics_verx100 / 100, 1137 xe->info.graphics_verx100 % 100, 1138 xe->info.media_name, 1139 xe->info.media_verx100 / 100, 1140 xe->info.media_verx100 % 100, 1141 str_yes_no(xe->info.probe_display), 1142 xe->info.dma_mask_size, xe->info.tile_count, 1143 xe->info.has_heci_gscfi, xe->info.has_heci_cscfi); 1144 1145 drm_dbg(&xe->drm, "Stepping = (G:%s, M:%s, B:%s)\n", 1146 xe_step_name(xe->info.step.graphics), 1147 xe_step_name(xe->info.step.media), 1148 xe_step_name(xe->info.step.basedie)); 1149 1150 drm_dbg(&xe->drm, "SR-IOV support: %s (mode: %s)\n", 1151 str_yes_no(xe_device_has_sriov(xe)), 1152 xe_sriov_mode_to_string(xe_device_sriov_mode(xe))); 1153 1154 err = xe_pm_init_early(xe); 1155 if (err) 1156 return err; 1157 1158 err = xe_device_probe(xe); 1159 if (err) 1160 return err; 1161 1162 err = xe_pm_init(xe); 1163 if (err) 1164 goto err_driver_cleanup; 1165 1166 drm_dbg(&xe->drm, "d3cold: capable=%s\n", 1167 str_yes_no(xe->d3cold.capable)); 1168 1169 return 0; 1170 1171 err_driver_cleanup: 1172 xe_pci_remove(pdev); 1173 return err; 1174 } 1175 1176 static void xe_pci_shutdown(struct pci_dev *pdev) 1177 { 1178 xe_device_shutdown(pdev_to_xe_device(pdev)); 1179 } 1180 1181 #ifdef CONFIG_PM_SLEEP 1182 static void d3cold_toggle(struct pci_dev *pdev, enum toggle_d3cold toggle) 1183 { 1184 struct xe_device *xe = pdev_to_xe_device(pdev); 1185 struct pci_dev *root_pdev; 1186 1187 if (!xe->d3cold.capable) 1188 return; 1189 1190 root_pdev = pcie_find_root_port(pdev); 1191 if (!root_pdev) 1192 return; 1193 1194 switch (toggle) { 1195 case D3COLD_DISABLE: 1196 pci_d3cold_disable(root_pdev); 1197 break; 1198 case D3COLD_ENABLE: 1199 pci_d3cold_enable(root_pdev); 1200 break; 1201 } 1202 } 1203 1204 static int xe_pci_suspend(struct device *dev) 1205 { 1206 struct pci_dev *pdev = to_pci_dev(dev); 1207 struct xe_device *xe = pdev_to_xe_device(pdev); 1208 int err; 1209 1210 if (xe_survivability_mode_is_boot_enabled(xe)) 1211 return -EBUSY; 1212 1213 err = xe_pm_suspend(xe); 1214 if (err) 1215 return err; 1216 1217 /* 1218 * Enabling D3Cold is needed for S2Idle/S0ix. 1219 * It is save to allow here since xe_pm_suspend has evicted 1220 * the local memory and the direct complete optimization is disabled. 1221 */ 1222 d3cold_toggle(pdev, D3COLD_ENABLE); 1223 1224 pci_save_state(pdev); 1225 pci_disable_device(pdev); 1226 pci_set_power_state(pdev, PCI_D3cold); 1227 1228 return 0; 1229 } 1230 1231 static int xe_pci_resume(struct device *dev) 1232 { 1233 struct pci_dev *pdev = to_pci_dev(dev); 1234 int err; 1235 1236 /* Give back the D3Cold decision to the runtime P M*/ 1237 d3cold_toggle(pdev, D3COLD_DISABLE); 1238 1239 err = pci_set_power_state(pdev, PCI_D0); 1240 if (err) 1241 return err; 1242 1243 pci_restore_state(pdev); 1244 1245 err = pci_enable_device(pdev); 1246 if (err) 1247 return err; 1248 1249 pci_set_master(pdev); 1250 1251 err = xe_pm_resume(pdev_to_xe_device(pdev)); 1252 if (err) 1253 return err; 1254 1255 return 0; 1256 } 1257 1258 static int xe_pci_runtime_suspend(struct device *dev) 1259 { 1260 struct pci_dev *pdev = to_pci_dev(dev); 1261 struct xe_device *xe = pdev_to_xe_device(pdev); 1262 int err; 1263 1264 /* 1265 * We hold an additional reference to the runtime PM to keep PF in D0 1266 * during VFs lifetime, as our VFs do not implement the PM capability. 1267 * This means we should never be runtime suspending as long as VFs are 1268 * enabled. 1269 */ 1270 xe_assert(xe, !IS_SRIOV_VF(xe)); 1271 xe_assert(xe, !pci_num_vf(pdev)); 1272 1273 err = xe_pm_runtime_suspend(xe); 1274 if (err) 1275 return err; 1276 1277 pci_save_state(pdev); 1278 1279 if (xe->d3cold.allowed) { 1280 d3cold_toggle(pdev, D3COLD_ENABLE); 1281 pci_disable_device(pdev); 1282 pci_ignore_hotplug(pdev); 1283 pci_set_power_state(pdev, PCI_D3cold); 1284 } else { 1285 d3cold_toggle(pdev, D3COLD_DISABLE); 1286 pci_set_power_state(pdev, PCI_D3hot); 1287 } 1288 1289 return 0; 1290 } 1291 1292 static int xe_pci_runtime_resume(struct device *dev) 1293 { 1294 struct pci_dev *pdev = to_pci_dev(dev); 1295 struct xe_device *xe = pdev_to_xe_device(pdev); 1296 int err; 1297 1298 err = pci_set_power_state(pdev, PCI_D0); 1299 if (err) 1300 return err; 1301 1302 pci_restore_state(pdev); 1303 1304 if (xe->d3cold.allowed) { 1305 err = pci_enable_device(pdev); 1306 if (err) 1307 return err; 1308 1309 pci_set_master(pdev); 1310 } 1311 1312 return xe_pm_runtime_resume(xe); 1313 } 1314 1315 static int xe_pci_runtime_idle(struct device *dev) 1316 { 1317 struct pci_dev *pdev = to_pci_dev(dev); 1318 struct xe_device *xe = pdev_to_xe_device(pdev); 1319 1320 xe_pm_d3cold_allowed_toggle(xe); 1321 1322 return 0; 1323 } 1324 1325 static const struct dev_pm_ops xe_pm_ops = { 1326 SET_SYSTEM_SLEEP_PM_OPS(xe_pci_suspend, xe_pci_resume) 1327 SET_RUNTIME_PM_OPS(xe_pci_runtime_suspend, xe_pci_runtime_resume, xe_pci_runtime_idle) 1328 }; 1329 #endif 1330 1331 static struct pci_driver xe_pci_driver = { 1332 .name = DRIVER_NAME, 1333 .id_table = pciidlist, 1334 .probe = xe_pci_probe, 1335 .remove = xe_pci_remove, 1336 .shutdown = xe_pci_shutdown, 1337 .sriov_configure = xe_pci_sriov_configure, 1338 #ifdef CONFIG_PM_SLEEP 1339 .driver.pm = &xe_pm_ops, 1340 #endif 1341 }; 1342 1343 /** 1344 * xe_pci_to_pf_device() - Get PF &xe_device. 1345 * @pdev: the VF &pci_dev device 1346 * 1347 * Return: pointer to PF &xe_device, NULL otherwise. 1348 */ 1349 struct xe_device *xe_pci_to_pf_device(struct pci_dev *pdev) 1350 { 1351 struct drm_device *drm; 1352 1353 drm = pci_iov_get_pf_drvdata(pdev, &xe_pci_driver); 1354 if (IS_ERR(drm)) 1355 return NULL; 1356 1357 return to_xe_device(drm); 1358 } 1359 1360 int xe_register_pci_driver(void) 1361 { 1362 return pci_register_driver(&xe_pci_driver); 1363 } 1364 1365 void xe_unregister_pci_driver(void) 1366 { 1367 pci_unregister_driver(&xe_pci_driver); 1368 } 1369 1370 #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST) 1371 #include "tests/xe_pci.c" 1372 #endif 1373