1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 #include "xe_pci.h" 7 8 #include <kunit/static_stub.h> 9 #include <linux/device/driver.h> 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/pm_runtime.h> 13 14 #include <drm/drm_color_mgmt.h> 15 #include <drm/drm_drv.h> 16 #include <drm/intel/pciids.h> 17 18 #include "display/xe_display.h" 19 #include "regs/xe_gt_regs.h" 20 #include "regs/xe_regs.h" 21 #include "xe_configfs.h" 22 #include "xe_device.h" 23 #include "xe_drv.h" 24 #include "xe_gt.h" 25 #include "xe_gt_sriov_vf.h" 26 #include "xe_guc.h" 27 #include "xe_mmio.h" 28 #include "xe_module.h" 29 #include "xe_pci_rebar.h" 30 #include "xe_pci_sriov.h" 31 #include "xe_pci_types.h" 32 #include "xe_pm.h" 33 #include "xe_printk.h" 34 #include "xe_sriov.h" 35 #include "xe_step.h" 36 #include "xe_survivability_mode.h" 37 #include "xe_tile.h" 38 39 enum toggle_d3cold { 40 D3COLD_DISABLE, 41 D3COLD_ENABLE, 42 }; 43 44 __diag_push(); 45 __diag_ignore_all("-Woverride-init", "Allow field overrides in table"); 46 47 #define PLATFORM(x) \ 48 .platform = XE_##x, \ 49 .platform_name = #x 50 51 #define NOP(x) x 52 53 static const struct xe_graphics_desc graphics_xelp = { 54 .hw_engine_mask = BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0), 55 .num_geometry_xecore_fuse_regs = 1, 56 }; 57 58 #define XE_HP_FEATURES \ 59 .has_range_tlb_inval = true 60 61 static const struct xe_graphics_desc graphics_xehpg = { 62 .hw_engine_mask = 63 BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) | 64 BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) | 65 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3), 66 .num_geometry_xecore_fuse_regs = 1, 67 .num_compute_xecore_fuse_regs = 1, 68 69 XE_HP_FEATURES, 70 }; 71 72 static const struct xe_graphics_desc graphics_xehpc = { 73 .hw_engine_mask = 74 BIT(XE_HW_ENGINE_BCS0) | BIT(XE_HW_ENGINE_BCS1) | 75 BIT(XE_HW_ENGINE_BCS2) | BIT(XE_HW_ENGINE_BCS3) | 76 BIT(XE_HW_ENGINE_BCS4) | BIT(XE_HW_ENGINE_BCS5) | 77 BIT(XE_HW_ENGINE_BCS6) | BIT(XE_HW_ENGINE_BCS7) | 78 BIT(XE_HW_ENGINE_BCS8) | 79 BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) | 80 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3), 81 82 XE_HP_FEATURES, 83 84 .has_access_counter = 1, 85 .has_asid = 1, 86 .has_atomic_enable_pte_bit = 1, 87 .has_usm = 1, 88 .num_compute_xecore_fuse_regs = 2, 89 }; 90 91 static const struct xe_graphics_desc graphics_xelpg = { 92 .hw_engine_mask = 93 BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) | 94 BIT(XE_HW_ENGINE_CCS0), 95 .num_geometry_xecore_fuse_regs = 1, 96 .num_compute_xecore_fuse_regs = 1, 97 98 XE_HP_FEATURES, 99 }; 100 101 #define XE2_GFX_FEATURES \ 102 .has_access_counter = 1, \ 103 .has_asid = 1, \ 104 .has_atomic_enable_pte_bit = 1, \ 105 .has_range_tlb_inval = 1, \ 106 .has_usm = 1, \ 107 .has_64bit_timestamp = 1, \ 108 .hw_engine_mask = \ 109 BIT(XE_HW_ENGINE_RCS0) | \ 110 BIT(XE_HW_ENGINE_BCS8) | BIT(XE_HW_ENGINE_BCS0) | \ 111 GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0) 112 113 static const struct xe_graphics_desc graphics_xe2 = { 114 XE2_GFX_FEATURES, 115 .num_geometry_xecore_fuse_regs = 3, 116 .num_compute_xecore_fuse_regs = 3, 117 }; 118 119 static const struct xe_graphics_desc graphics_xe3p_lpg = { 120 XE2_GFX_FEATURES, 121 .has_indirect_ring_state = 1, 122 .multi_queue_engine_class_mask = BIT(XE_ENGINE_CLASS_COPY) | BIT(XE_ENGINE_CLASS_COMPUTE), 123 .num_geometry_xecore_fuse_regs = 3, 124 .num_compute_xecore_fuse_regs = 3, 125 }; 126 127 static const struct xe_graphics_desc graphics_xe3p_xpc = { 128 XE2_GFX_FEATURES, 129 .has_access_counter = 0, 130 .has_indirect_ring_state = 1, 131 .hw_engine_mask = 132 GENMASK(XE_HW_ENGINE_BCS8, XE_HW_ENGINE_BCS1) | 133 GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0), 134 .multi_queue_engine_class_mask = BIT(XE_ENGINE_CLASS_COPY) | 135 BIT(XE_ENGINE_CLASS_COMPUTE), 136 .num_geometry_xecore_fuse_regs = 4, 137 .num_compute_xecore_fuse_regs = 4, 138 }; 139 140 static const struct xe_media_desc media_xem = { 141 .hw_engine_mask = 142 GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) | 143 GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0), 144 }; 145 146 static const struct xe_media_desc media_xelpmp = { 147 .hw_engine_mask = 148 GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) | 149 GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0) | 150 BIT(XE_HW_ENGINE_GSCCS0) 151 }; 152 153 /* Pre-GMDID Graphics IPs */ 154 static const struct xe_ip graphics_ip_xelp = { 1200, "Xe_LP", &graphics_xelp }; 155 static const struct xe_ip graphics_ip_xelpp = { 1210, "Xe_LP+", &graphics_xelp }; 156 static const struct xe_ip graphics_ip_xehpg = { 1255, "Xe_HPG", &graphics_xehpg }; 157 static const struct xe_ip graphics_ip_xehpc = { 1260, "Xe_HPC", &graphics_xehpc }; 158 159 /* GMDID-based Graphics IPs */ 160 static const struct xe_ip graphics_ips[] = { 161 { 1270, "Xe_LPG", &graphics_xelpg }, 162 { 1271, "Xe_LPG", &graphics_xelpg }, 163 { 1274, "Xe_LPG+", &graphics_xelpg }, 164 { 2001, "Xe2_HPG", &graphics_xe2 }, 165 { 2002, "Xe2_HPG", &graphics_xe2 }, 166 { 2004, "Xe2_LPG", &graphics_xe2 }, 167 { 3000, "Xe3_LPG", &graphics_xe2 }, 168 { 3001, "Xe3_LPG", &graphics_xe2 }, 169 { 3003, "Xe3_LPG", &graphics_xe2 }, 170 { 3004, "Xe3_LPG", &graphics_xe2 }, 171 { 3005, "Xe3_LPG", &graphics_xe2 }, 172 { 3510, "Xe3p_LPG", &graphics_xe3p_lpg }, 173 { 3511, "Xe3p_XPC", &graphics_xe3p_xpc }, 174 }; 175 176 /* Pre-GMDID Media IPs */ 177 static const struct xe_ip media_ip_xem = { 1200, "Xe_M", &media_xem }; 178 static const struct xe_ip media_ip_xehpm = { 1255, "Xe_HPM", &media_xem }; 179 180 /* GMDID-based Media IPs */ 181 static const struct xe_ip media_ips[] = { 182 { 1300, "Xe_LPM+", &media_xelpmp }, 183 { 1301, "Xe2_HPM", &media_xelpmp }, 184 { 2000, "Xe2_LPM", &media_xelpmp }, 185 { 3000, "Xe3_LPM", &media_xelpmp }, 186 { 3002, "Xe3_LPM", &media_xelpmp }, 187 { 3500, "Xe3p_LPM", &media_xelpmp }, 188 { 3503, "Xe3p_HPM", &media_xelpmp }, 189 }; 190 191 #define MULTI_LRC_MASK \ 192 .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE) | \ 193 BIT(XE_ENGINE_CLASS_VIDEO_ENHANCE) 194 195 static const struct xe_device_desc tgl_desc = { 196 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 197 .pre_gmdid_media_ip = &media_ip_xem, 198 PLATFORM(TIGERLAKE), 199 .dma_mask_size = 39, 200 .has_cached_pt = true, 201 .has_display = true, 202 .has_llc = true, 203 .has_sriov = true, 204 .max_gt_per_tile = 1, 205 MULTI_LRC_MASK, 206 .require_force_probe = true, 207 .va_bits = 48, 208 .vm_max_level = 3, 209 }; 210 211 static const struct xe_device_desc rkl_desc = { 212 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 213 .pre_gmdid_media_ip = &media_ip_xem, 214 PLATFORM(ROCKETLAKE), 215 .dma_mask_size = 39, 216 .has_cached_pt = true, 217 .has_display = true, 218 .has_llc = true, 219 .max_gt_per_tile = 1, 220 MULTI_LRC_MASK, 221 .require_force_probe = true, 222 .va_bits = 48, 223 .vm_max_level = 3, 224 }; 225 226 static const u16 adls_rpls_ids[] = { INTEL_RPLS_IDS(NOP), 0 }; 227 228 static const struct xe_device_desc adl_s_desc = { 229 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 230 .pre_gmdid_media_ip = &media_ip_xem, 231 PLATFORM(ALDERLAKE_S), 232 .dma_mask_size = 39, 233 .has_cached_pt = true, 234 .has_display = true, 235 .has_llc = true, 236 .has_sriov = true, 237 .max_gt_per_tile = 1, 238 MULTI_LRC_MASK, 239 .require_force_probe = true, 240 .subplatforms = (const struct xe_subplatform_desc[]) { 241 { XE_SUBPLATFORM_ALDERLAKE_S_RPLS, "RPLS", adls_rpls_ids }, 242 {}, 243 }, 244 .va_bits = 48, 245 .vm_max_level = 3, 246 }; 247 248 static const u16 adlp_rplu_ids[] = { INTEL_RPLU_IDS(NOP), 0 }; 249 250 static const struct xe_device_desc adl_p_desc = { 251 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 252 .pre_gmdid_media_ip = &media_ip_xem, 253 PLATFORM(ALDERLAKE_P), 254 .dma_mask_size = 39, 255 .has_cached_pt = true, 256 .has_display = true, 257 .has_llc = true, 258 .has_sriov = true, 259 .max_gt_per_tile = 1, 260 MULTI_LRC_MASK, 261 .require_force_probe = true, 262 .subplatforms = (const struct xe_subplatform_desc[]) { 263 { XE_SUBPLATFORM_ALDERLAKE_P_RPLU, "RPLU", adlp_rplu_ids }, 264 {}, 265 }, 266 .va_bits = 48, 267 .vm_max_level = 3, 268 }; 269 270 static const struct xe_device_desc adl_n_desc = { 271 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 272 .pre_gmdid_media_ip = &media_ip_xem, 273 PLATFORM(ALDERLAKE_N), 274 .dma_mask_size = 39, 275 .has_cached_pt = true, 276 .has_display = true, 277 .has_llc = true, 278 .has_sriov = true, 279 .max_gt_per_tile = 1, 280 MULTI_LRC_MASK, 281 .require_force_probe = true, 282 .va_bits = 48, 283 .vm_max_level = 3, 284 }; 285 286 #define DGFX_FEATURES \ 287 .is_dgfx = 1 288 289 static const struct xe_device_desc dg1_desc = { 290 .pre_gmdid_graphics_ip = &graphics_ip_xelpp, 291 .pre_gmdid_media_ip = &media_ip_xem, 292 DGFX_FEATURES, 293 PLATFORM(DG1), 294 .dma_mask_size = 39, 295 .has_display = true, 296 .has_gsc_nvm = 1, 297 .has_heci_gscfi = 1, 298 .max_gt_per_tile = 1, 299 MULTI_LRC_MASK, 300 .require_force_probe = true, 301 .va_bits = 48, 302 .vm_max_level = 3, 303 }; 304 305 static const u16 dg2_g10_ids[] = { INTEL_DG2_G10_IDS(NOP), INTEL_ATS_M150_IDS(NOP), 0 }; 306 static const u16 dg2_g11_ids[] = { INTEL_DG2_G11_IDS(NOP), INTEL_ATS_M75_IDS(NOP), 0 }; 307 static const u16 dg2_g12_ids[] = { INTEL_DG2_G12_IDS(NOP), 0 }; 308 309 #define DG2_FEATURES \ 310 DGFX_FEATURES, \ 311 PLATFORM(DG2), \ 312 .has_flat_ccs = 1, \ 313 .has_gsc_nvm = 1, \ 314 .has_heci_gscfi = 1, \ 315 .subplatforms = (const struct xe_subplatform_desc[]) { \ 316 { XE_SUBPLATFORM_DG2_G10, "G10", dg2_g10_ids }, \ 317 { XE_SUBPLATFORM_DG2_G11, "G11", dg2_g11_ids }, \ 318 { XE_SUBPLATFORM_DG2_G12, "G12", dg2_g12_ids }, \ 319 { } \ 320 }, \ 321 .va_bits = 48, \ 322 .vm_max_level = 3, \ 323 .vram_flags = XE_VRAM_FLAGS_NEED64K 324 325 static const struct xe_device_desc ats_m_desc = { 326 .pre_gmdid_graphics_ip = &graphics_ip_xehpg, 327 .pre_gmdid_media_ip = &media_ip_xehpm, 328 .dma_mask_size = 46, 329 .max_gt_per_tile = 1, 330 MULTI_LRC_MASK, 331 .require_force_probe = true, 332 333 DG2_FEATURES, 334 .has_display = false, 335 .has_sriov = true, 336 }; 337 338 static const struct xe_device_desc dg2_desc = { 339 .pre_gmdid_graphics_ip = &graphics_ip_xehpg, 340 .pre_gmdid_media_ip = &media_ip_xehpm, 341 .dma_mask_size = 46, 342 .max_gt_per_tile = 1, 343 MULTI_LRC_MASK, 344 .require_force_probe = true, 345 346 DG2_FEATURES, 347 .has_display = true, 348 .has_fan_control = true, 349 .has_mbx_power_limits = false, 350 }; 351 352 static const __maybe_unused struct xe_device_desc pvc_desc = { 353 .pre_gmdid_graphics_ip = &graphics_ip_xehpc, 354 DGFX_FEATURES, 355 PLATFORM(PVC), 356 .dma_mask_size = 52, 357 .has_display = false, 358 .has_gsc_nvm = 1, 359 .has_heci_gscfi = 1, 360 .max_gt_per_tile = 1, 361 .max_remote_tiles = 1, 362 MULTI_LRC_MASK, 363 .require_force_probe = true, 364 .va_bits = 57, 365 .vm_max_level = 4, 366 .vram_flags = XE_VRAM_FLAGS_NEED64K, 367 .has_mbx_power_limits = false, 368 }; 369 370 static const struct xe_device_desc mtl_desc = { 371 /* .graphics and .media determined via GMD_ID */ 372 .require_force_probe = true, 373 PLATFORM(METEORLAKE), 374 .dma_mask_size = 46, 375 .has_display = true, 376 .has_pxp = true, 377 .max_gt_per_tile = 2, 378 MULTI_LRC_MASK, 379 .va_bits = 48, 380 .vm_max_level = 3, 381 }; 382 383 static const struct xe_device_desc lnl_desc = { 384 PLATFORM(LUNARLAKE), 385 .dma_mask_size = 46, 386 .has_display = true, 387 .has_flat_ccs = 1, 388 .has_pxp = true, 389 .max_gt_per_tile = 2, 390 MULTI_LRC_MASK, 391 .needs_scratch = true, 392 .va_bits = 48, 393 .vm_max_level = 4, 394 }; 395 396 static const u16 bmg_g21_ids[] = { INTEL_BMG_G21_IDS(NOP), 0 }; 397 398 static const struct xe_device_desc bmg_desc = { 399 DGFX_FEATURES, 400 PLATFORM(BATTLEMAGE), 401 .dma_mask_size = 46, 402 .has_display = true, 403 .has_fan_control = true, 404 .has_flat_ccs = 1, 405 .has_mbx_power_limits = true, 406 .has_mbx_thermal_info = true, 407 .has_gsc_nvm = 1, 408 .has_heci_cscfi = 1, 409 .has_i2c = true, 410 .has_late_bind = true, 411 .has_pre_prod_wa = 1, 412 .has_soc_remapper_telem = true, 413 .has_sriov = true, 414 .max_gt_per_tile = 2, 415 MULTI_LRC_MASK, 416 .needs_scratch = true, 417 .subplatforms = (const struct xe_subplatform_desc[]) { 418 { XE_SUBPLATFORM_BATTLEMAGE_G21, "G21", bmg_g21_ids }, 419 { } 420 }, 421 .va_bits = 48, 422 .vm_max_level = 4, 423 }; 424 425 static const struct xe_device_desc ptl_desc = { 426 PLATFORM(PANTHERLAKE), 427 .dma_mask_size = 46, 428 .has_display = true, 429 .has_flat_ccs = 1, 430 .has_sriov = true, 431 .has_pre_prod_wa = 1, 432 .has_pxp = true, 433 .max_gt_per_tile = 2, 434 MULTI_LRC_MASK, 435 .needs_scratch = true, 436 .needs_shared_vf_gt_wq = true, 437 .va_bits = 48, 438 .vm_max_level = 4, 439 }; 440 441 static const struct xe_device_desc nvls_desc = { 442 PLATFORM(NOVALAKE_S), 443 .dma_mask_size = 46, 444 .has_display = true, 445 .has_flat_ccs = 1, 446 .has_pre_prod_wa = 1, 447 .has_sriov = true, 448 .max_gt_per_tile = 2, 449 MULTI_LRC_MASK, 450 .require_force_probe = true, 451 .va_bits = 48, 452 .vm_max_level = 4, 453 }; 454 455 static const struct xe_device_desc cri_desc = { 456 DGFX_FEATURES, 457 PLATFORM(CRESCENTISLAND), 458 .dma_mask_size = 52, 459 .has_display = false, 460 .has_flat_ccs = false, 461 .has_gsc_nvm = 1, 462 .has_i2c = true, 463 .has_mbx_power_limits = true, 464 .has_mbx_thermal_info = true, 465 .has_mert = true, 466 .has_pre_prod_wa = 1, 467 .has_soc_remapper_sysctrl = true, 468 .has_soc_remapper_telem = true, 469 .has_sriov = true, 470 .has_sysctrl = true, 471 .max_gt_per_tile = 2, 472 MULTI_LRC_MASK, 473 .require_force_probe = true, 474 .va_bits = 57, 475 .vm_max_level = 4, 476 }; 477 478 static const struct xe_device_desc nvlp_desc = { 479 PLATFORM(NOVALAKE_P), 480 .dma_mask_size = 46, 481 .has_cached_pt = true, 482 .has_display = true, 483 .has_flat_ccs = 1, 484 .has_page_reclaim_hw_assist = true, 485 .has_pre_prod_wa = true, 486 .has_sriov = true, 487 .max_gt_per_tile = 2, 488 MULTI_LRC_MASK, 489 .require_force_probe = true, 490 .va_bits = 48, 491 .vm_max_level = 4, 492 }; 493 494 #undef PLATFORM 495 __diag_pop(); 496 497 /* 498 * Make sure any device matches here are from most specific to most 499 * general. For example, since the Quanta match is based on the subsystem 500 * and subvendor IDs, we need it to come before the more general IVB 501 * PCI ID matches, otherwise we'll use the wrong info struct above. 502 */ 503 static const struct pci_device_id pciidlist[] = { 504 INTEL_TGL_IDS(INTEL_VGA_DEVICE, &tgl_desc), 505 INTEL_RKL_IDS(INTEL_VGA_DEVICE, &rkl_desc), 506 INTEL_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc), 507 INTEL_ADLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 508 INTEL_ADLN_IDS(INTEL_VGA_DEVICE, &adl_n_desc), 509 INTEL_RPLU_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 510 INTEL_RPLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 511 INTEL_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc), 512 INTEL_DG1_IDS(INTEL_VGA_DEVICE, &dg1_desc), 513 INTEL_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_desc), 514 INTEL_ARL_IDS(INTEL_VGA_DEVICE, &mtl_desc), 515 INTEL_DG2_IDS(INTEL_VGA_DEVICE, &dg2_desc), 516 INTEL_MTL_IDS(INTEL_VGA_DEVICE, &mtl_desc), 517 INTEL_LNL_IDS(INTEL_VGA_DEVICE, &lnl_desc), 518 INTEL_BMG_IDS(INTEL_VGA_DEVICE, &bmg_desc), 519 INTEL_PTL_IDS(INTEL_VGA_DEVICE, &ptl_desc), 520 INTEL_WCL_IDS(INTEL_VGA_DEVICE, &ptl_desc), 521 INTEL_NVLS_IDS(INTEL_VGA_DEVICE, &nvls_desc), 522 INTEL_CRI_IDS(INTEL_PCI_DEVICE, &cri_desc), 523 INTEL_NVLP_IDS(INTEL_VGA_DEVICE, &nvlp_desc), 524 { } 525 }; 526 MODULE_DEVICE_TABLE(pci, pciidlist); 527 528 /* is device_id present in comma separated list of ids */ 529 static bool device_id_in_list(u16 device_id, const char *devices, bool negative) 530 { 531 char *s, *p, *tok; 532 bool ret; 533 534 if (!devices || !*devices) 535 return false; 536 537 /* match everything */ 538 if (negative && strcmp(devices, "!*") == 0) 539 return true; 540 if (!negative && strcmp(devices, "*") == 0) 541 return true; 542 543 s = kstrdup(devices, GFP_KERNEL); 544 if (!s) 545 return false; 546 547 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) { 548 u16 val; 549 550 if (negative && tok[0] == '!') 551 tok++; 552 else if ((negative && tok[0] != '!') || 553 (!negative && tok[0] == '!')) 554 continue; 555 556 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) { 557 ret = true; 558 break; 559 } 560 } 561 562 kfree(s); 563 564 return ret; 565 } 566 567 static bool id_forced(u16 device_id) 568 { 569 return device_id_in_list(device_id, xe_modparam.force_probe, false); 570 } 571 572 static bool id_blocked(u16 device_id) 573 { 574 return device_id_in_list(device_id, xe_modparam.force_probe, true); 575 } 576 577 static const struct xe_subplatform_desc * 578 find_subplatform(const struct xe_device_desc *desc, u16 devid) 579 { 580 const struct xe_subplatform_desc *sp; 581 const u16 *id; 582 583 for (sp = desc->subplatforms; sp && sp->subplatform; sp++) 584 for (id = sp->pciidlist; *id; id++) 585 if (*id == devid) 586 return sp; 587 588 return NULL; 589 } 590 591 enum xe_gmdid_type { 592 GMDID_GRAPHICS, 593 GMDID_MEDIA 594 }; 595 596 static int read_gmdid(struct xe_device *xe, enum xe_gmdid_type type, u32 *ver, u32 *revid) 597 { 598 struct xe_mmio *mmio = xe_root_tile_mmio(xe); 599 struct xe_reg gmdid_reg = GMD_ID; 600 u32 val; 601 602 KUNIT_STATIC_STUB_REDIRECT(read_gmdid, xe, type, ver, revid); 603 604 if (IS_SRIOV_VF(xe)) { 605 /* 606 * To get the value of the GMDID register, VFs must obtain it 607 * from the GuC using MMIO communication. 608 * 609 * Note that at this point the GTs are not initialized and only 610 * tile-level access to MMIO registers is possible. To use our 611 * existing GuC communication functions we must create a dummy 612 * GT structure and perform at least basic xe_gt and xe_guc 613 * initialization. 614 */ 615 struct xe_gt *gt __free(kfree) = NULL; 616 int err; 617 618 /* Don't try to read media ver if media GT is not allowed */ 619 if (type == GMDID_MEDIA && !xe_configfs_media_gt_allowed(to_pci_dev(xe->drm.dev))) { 620 *ver = *revid = 0; 621 return 0; 622 } 623 624 gt = kzalloc(sizeof(*gt), GFP_KERNEL); 625 if (!gt) 626 return -ENOMEM; 627 628 gt->tile = &xe->tiles[0]; 629 if (type == GMDID_MEDIA) { 630 gt->info.id = 1; 631 gt->info.type = XE_GT_TYPE_MEDIA; 632 } else { 633 gt->info.id = 0; 634 gt->info.type = XE_GT_TYPE_MAIN; 635 } 636 637 xe_gt_mmio_init(gt); 638 xe_guc_comm_init_early(>->uc.guc); 639 640 err = xe_gt_sriov_vf_bootstrap(gt); 641 if (err) 642 return err; 643 644 val = xe_gt_sriov_vf_gmdid(gt); 645 } else { 646 /* 647 * GMD_ID is a GT register, but at this point in the driver 648 * init we haven't fully initialized the GT yet so we need to 649 * read the register with the tile's MMIO accessor. That means 650 * we need to apply the GSI offset manually since it won't get 651 * automatically added as it would if we were using a GT mmio 652 * accessor. 653 */ 654 if (type == GMDID_MEDIA) 655 gmdid_reg.addr += MEDIA_GT_GSI_OFFSET; 656 657 val = xe_mmio_read32(mmio, gmdid_reg); 658 } 659 660 *ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val) * 100 + REG_FIELD_GET(GMD_ID_RELEASE_MASK, val); 661 *revid = REG_FIELD_GET(GMD_ID_REVID, val); 662 663 return 0; 664 } 665 666 static const struct xe_ip *find_graphics_ip(unsigned int verx100) 667 { 668 KUNIT_STATIC_STUB_REDIRECT(find_graphics_ip, verx100); 669 670 for (int i = 0; i < ARRAY_SIZE(graphics_ips); i++) 671 if (graphics_ips[i].verx100 == verx100) 672 return &graphics_ips[i]; 673 return NULL; 674 } 675 676 static const struct xe_ip *find_media_ip(unsigned int verx100) 677 { 678 KUNIT_STATIC_STUB_REDIRECT(find_media_ip, verx100); 679 680 for (int i = 0; i < ARRAY_SIZE(media_ips); i++) 681 if (media_ips[i].verx100 == verx100) 682 return &media_ips[i]; 683 return NULL; 684 } 685 686 /* 687 * Read IP version from hardware and select graphics/media IP descriptors 688 * based on the result. 689 */ 690 static int handle_gmdid(struct xe_device *xe, 691 const struct xe_ip **graphics_ip, 692 const struct xe_ip **media_ip, 693 u32 *graphics_revid, 694 u32 *media_revid) 695 { 696 u32 ver; 697 int ret; 698 699 *graphics_ip = NULL; 700 *media_ip = NULL; 701 702 ret = read_gmdid(xe, GMDID_GRAPHICS, &ver, graphics_revid); 703 if (ret) 704 return ret; 705 706 *graphics_ip = find_graphics_ip(ver); 707 if (!*graphics_ip) { 708 drm_err(&xe->drm, "Hardware reports unknown graphics version %u.%02u\n", 709 ver / 100, ver % 100); 710 } 711 712 ret = read_gmdid(xe, GMDID_MEDIA, &ver, media_revid); 713 if (ret) 714 return ret; 715 716 /* Media may legitimately be fused off / not present */ 717 if (ver == 0) 718 return 0; 719 720 *media_ip = find_media_ip(ver); 721 if (!*media_ip) { 722 drm_err(&xe->drm, "Hardware reports unknown media version %u.%02u\n", 723 ver / 100, ver % 100); 724 } 725 726 return 0; 727 } 728 729 static void init_devid(struct xe_device *xe) 730 { 731 struct pci_dev *pdev = to_pci_dev(xe->drm.dev); 732 733 KUNIT_STATIC_STUB_REDIRECT(init_devid, xe); 734 735 xe->info.devid = pdev->device; 736 xe->info.revid = pdev->revision; 737 } 738 739 /* 740 * Initialize device info content that only depends on static driver_data 741 * passed to the driver at probe time from PCI ID table. 742 */ 743 static int xe_info_init_early(struct xe_device *xe, 744 const struct xe_device_desc *desc, 745 const struct xe_subplatform_desc *subplatform_desc) 746 { 747 int err; 748 749 xe->info.platform_name = desc->platform_name; 750 xe->info.platform = desc->platform; 751 xe->info.subplatform = subplatform_desc ? 752 subplatform_desc->subplatform : XE_SUBPLATFORM_NONE; 753 754 init_devid(xe); 755 756 xe->info.dma_mask_size = desc->dma_mask_size; 757 xe->info.va_bits = desc->va_bits; 758 xe->info.vm_max_level = desc->vm_max_level; 759 xe->info.vram_flags = desc->vram_flags; 760 761 xe->info.is_dgfx = desc->is_dgfx; 762 xe->info.has_cached_pt = desc->has_cached_pt; 763 xe->info.has_fan_control = desc->has_fan_control; 764 /* runtime fusing may force flat_ccs to disabled later */ 765 xe->info.has_flat_ccs = desc->has_flat_ccs; 766 xe->info.has_mbx_power_limits = desc->has_mbx_power_limits; 767 xe->info.has_mbx_thermal_info = desc->has_mbx_thermal_info; 768 xe->info.has_gsc_nvm = desc->has_gsc_nvm; 769 xe->info.has_heci_gscfi = desc->has_heci_gscfi; 770 xe->info.has_heci_cscfi = desc->has_heci_cscfi; 771 xe->info.has_i2c = desc->has_i2c; 772 xe->info.has_late_bind = desc->has_late_bind; 773 xe->info.has_llc = desc->has_llc; 774 xe->info.has_mert = desc->has_mert; 775 xe->info.has_page_reclaim_hw_assist = desc->has_page_reclaim_hw_assist; 776 xe->info.has_pre_prod_wa = desc->has_pre_prod_wa; 777 xe->info.has_pxp = desc->has_pxp; 778 xe->info.has_soc_remapper_sysctrl = desc->has_soc_remapper_sysctrl; 779 xe->info.has_soc_remapper_telem = desc->has_soc_remapper_telem; 780 xe->info.has_sriov = xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev)) && 781 desc->has_sriov; 782 xe->info.has_sysctrl = desc->has_sysctrl; 783 xe->info.skip_guc_pc = desc->skip_guc_pc; 784 xe->info.skip_pcode = desc->skip_pcode; 785 xe->info.needs_scratch = desc->needs_scratch; 786 xe->info.needs_shared_vf_gt_wq = desc->needs_shared_vf_gt_wq; 787 xe->info.multi_lrc_mask = desc->multi_lrc_mask; 788 789 xe->info.probe_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) && 790 xe_modparam.probe_display && 791 desc->has_display; 792 xe->info.force_execlist = xe_modparam.force_execlist; 793 794 xe_assert(xe, desc->max_gt_per_tile > 0); 795 xe_assert(xe, desc->max_gt_per_tile <= XE_MAX_GT_PER_TILE); 796 xe->info.max_gt_per_tile = desc->max_gt_per_tile; 797 xe->info.tile_count = 1 + desc->max_remote_tiles; 798 799 xe_step_platform_get(xe); 800 801 err = xe_tile_init_early(xe_device_get_root_tile(xe), xe, 0); 802 if (err) 803 return err; 804 805 return 0; 806 } 807 808 /* 809 * Possibly override number of tile based on configuration register. 810 */ 811 static void xe_info_probe_tile_count(struct xe_device *xe) 812 { 813 struct xe_mmio *mmio; 814 u8 tile_count; 815 u32 mtcfg; 816 817 KUNIT_STATIC_STUB_REDIRECT(xe_info_probe_tile_count, xe); 818 819 /* 820 * Probe for tile count only for platforms that support multiple 821 * tiles. 822 */ 823 if (xe->info.tile_count == 1) 824 return; 825 826 mmio = xe_root_tile_mmio(xe); 827 828 /* 829 * Although the per-tile mmio regs are not yet initialized, this 830 * is fine as it's going to the root tile's mmio, that's 831 * guaranteed to be initialized earlier in xe_mmio_probe_early() 832 */ 833 mtcfg = xe_mmio_read32(mmio, XEHP_MTCFG_ADDR); 834 tile_count = REG_FIELD_GET(TILE_COUNT, mtcfg) + 1; 835 836 if (tile_count < xe->info.tile_count) { 837 drm_info(&xe->drm, "tile_count: %d, reduced_tile_count %d\n", 838 xe->info.tile_count, tile_count); 839 xe->info.tile_count = tile_count; 840 } 841 } 842 843 static struct xe_gt *alloc_primary_gt(struct xe_tile *tile, 844 const struct xe_graphics_desc *graphics_desc, 845 const struct xe_media_desc *media_desc) 846 { 847 struct xe_device *xe = tile_to_xe(tile); 848 struct xe_gt *gt; 849 850 if (!xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev))) { 851 xe_info(xe, "Primary GT disabled via configfs\n"); 852 return NULL; 853 } 854 855 gt = xe_gt_alloc(tile); 856 if (IS_ERR(gt)) 857 return gt; 858 859 gt->info.type = XE_GT_TYPE_MAIN; 860 gt->info.id = tile->id * xe->info.max_gt_per_tile; 861 gt->info.has_indirect_ring_state = graphics_desc->has_indirect_ring_state; 862 gt->info.multi_queue_engine_class_mask = graphics_desc->multi_queue_engine_class_mask; 863 gt->info.engine_mask = graphics_desc->hw_engine_mask; 864 gt->info.num_geometry_xecore_fuse_regs = graphics_desc->num_geometry_xecore_fuse_regs; 865 gt->info.num_compute_xecore_fuse_regs = graphics_desc->num_compute_xecore_fuse_regs; 866 867 /* 868 * Even if the service copy engines wind up being fused off, their 869 * presence in the IP descriptor indicates that the platform supports 870 * Xe2-style MEM_SET and MEM_COPY functionality. 871 */ 872 if (graphics_desc->hw_engine_mask & GENMASK(XE_HW_ENGINE_BCS8, 873 XE_HW_ENGINE_BCS1)) 874 gt->info.has_xe2_blt_instructions = true; 875 876 /* 877 * Before media version 13, the media IP was part of the primary GT 878 * so we need to add the media engines to the primary GT's engine list. 879 */ 880 if (MEDIA_VER(xe) < 13 && media_desc) 881 gt->info.engine_mask |= media_desc->hw_engine_mask; 882 883 return gt; 884 } 885 886 static struct xe_gt *alloc_media_gt(struct xe_tile *tile, 887 const struct xe_media_desc *media_desc) 888 { 889 struct xe_device *xe = tile_to_xe(tile); 890 struct xe_gt *gt; 891 892 if (!xe_configfs_media_gt_allowed(to_pci_dev(xe->drm.dev))) { 893 xe_info(xe, "Media GT disabled via configfs\n"); 894 return NULL; 895 } 896 897 if (MEDIA_VER(xe) < 13 || !media_desc) 898 return NULL; 899 900 gt = xe_gt_alloc(tile); 901 if (IS_ERR(gt)) 902 return gt; 903 904 gt->info.type = XE_GT_TYPE_MEDIA; 905 gt->info.id = tile->id * xe->info.max_gt_per_tile + 1; 906 gt->info.has_indirect_ring_state = media_desc->has_indirect_ring_state; 907 gt->info.engine_mask = media_desc->hw_engine_mask; 908 909 return gt; 910 } 911 912 /* 913 * Initialize device info content that does require knowledge about 914 * graphics / media IP version. 915 * Make sure that GT / tile structures allocated by the driver match the data 916 * present in device info. 917 */ 918 static int xe_info_init(struct xe_device *xe, 919 const struct xe_device_desc *desc) 920 { 921 u32 graphics_gmdid_revid = 0, media_gmdid_revid = 0; 922 const struct xe_ip *graphics_ip; 923 const struct xe_ip *media_ip; 924 const struct xe_graphics_desc *graphics_desc; 925 const struct xe_media_desc *media_desc; 926 struct xe_tile *tile; 927 struct xe_gt *gt; 928 int ret; 929 u8 id; 930 931 /* 932 * If this platform supports GMD_ID, we'll detect the proper IP 933 * descriptor to use from hardware registers. 934 * desc->pre_gmdid_graphics_ip will only ever be set at this point for 935 * platforms before GMD_ID. In that case the IP descriptions and 936 * versions are simply derived from that. 937 */ 938 if (desc->pre_gmdid_graphics_ip) { 939 graphics_ip = desc->pre_gmdid_graphics_ip; 940 media_ip = desc->pre_gmdid_media_ip; 941 xe_step_pre_gmdid_get(xe); 942 } else { 943 xe_assert(xe, !desc->pre_gmdid_media_ip); 944 ret = handle_gmdid(xe, &graphics_ip, &media_ip, 945 &graphics_gmdid_revid, &media_gmdid_revid); 946 if (ret) 947 return ret; 948 949 xe_step_gmdid_get(xe, graphics_gmdid_revid, media_gmdid_revid); 950 } 951 952 /* 953 * If we couldn't detect the graphics IP, that's considered a fatal 954 * error and we should abort driver load. Failing to detect media 955 * IP is non-fatal; we'll just proceed without enabling media support. 956 */ 957 if (!graphics_ip) 958 return -ENODEV; 959 960 xe->info.graphics_verx100 = graphics_ip->verx100; 961 xe->info.graphics_name = graphics_ip->name; 962 graphics_desc = graphics_ip->desc; 963 964 if (media_ip) { 965 xe->info.media_verx100 = media_ip->verx100; 966 xe->info.media_name = media_ip->name; 967 media_desc = media_ip->desc; 968 } else { 969 xe->info.media_name = "none"; 970 media_desc = NULL; 971 } 972 973 xe->info.has_access_counter = graphics_desc->has_access_counter; 974 xe->info.has_asid = graphics_desc->has_asid; 975 xe->info.has_atomic_enable_pte_bit = graphics_desc->has_atomic_enable_pte_bit; 976 if (xe->info.platform != XE_PVC) 977 xe->info.has_device_atomics_on_smem = 1; 978 979 xe->info.has_range_tlb_inval = graphics_desc->has_range_tlb_inval; 980 xe->info.has_ctx_tlb_inval = graphics_desc->has_ctx_tlb_inval; 981 xe->info.has_usm = graphics_desc->has_usm; 982 xe->info.has_64bit_timestamp = graphics_desc->has_64bit_timestamp; 983 xe->info.has_mem_copy_instr = GRAPHICS_VER(xe) >= 20; 984 985 if (IS_SRIOV_VF(xe)) { 986 xe->info.has_sysctrl = 0; 987 xe->info.has_soc_remapper_sysctrl = 0; 988 xe->info.has_soc_remapper_telem = 0; 989 } 990 991 xe_info_probe_tile_count(xe); 992 993 for_each_remote_tile(tile, xe, id) { 994 int err; 995 996 err = xe_tile_init_early(tile, xe, id); 997 if (err) 998 return err; 999 } 1000 1001 /* Allocate any GT and VRAM structures necessary for the platform. */ 1002 for_each_tile(tile, xe, id) { 1003 int err; 1004 1005 err = xe_tile_alloc_vram(tile); 1006 if (err) 1007 return err; 1008 1009 tile->primary_gt = alloc_primary_gt(tile, graphics_desc, media_desc); 1010 if (IS_ERR(tile->primary_gt)) 1011 return PTR_ERR(tile->primary_gt); 1012 1013 /* 1014 * It's not currently possible to probe a device with the 1015 * primary GT disabled. With some work, this may be future in 1016 * the possible for igpu platforms (although probably not for 1017 * dgpu's since access to the primary GT's BCS engines is 1018 * required for VRAM management). 1019 */ 1020 if (!tile->primary_gt) { 1021 drm_err(&xe->drm, "Cannot probe device with without a primary GT\n"); 1022 return -ENODEV; 1023 } 1024 1025 tile->media_gt = alloc_media_gt(tile, media_desc); 1026 if (IS_ERR(tile->media_gt)) 1027 return PTR_ERR(tile->media_gt); 1028 } 1029 1030 /* 1031 * Now that we have tiles and GTs defined, let's loop over valid GTs 1032 * in order to define gt_count. 1033 */ 1034 for_each_gt(gt, xe, id) 1035 xe->info.gt_count++; 1036 1037 return 0; 1038 } 1039 1040 static void xe_pci_remove(struct pci_dev *pdev) 1041 { 1042 struct xe_device *xe = pdev_to_xe_device(pdev); 1043 1044 if (IS_SRIOV_PF(xe)) 1045 xe_pci_sriov_configure(pdev, 0); 1046 1047 if (xe_survivability_mode_is_boot_enabled(xe)) 1048 return; 1049 1050 xe_device_remove(xe); 1051 xe_pm_fini(xe); 1052 } 1053 1054 /* 1055 * Probe the PCI device, initialize various parts of the driver. 1056 * 1057 * Fault injection is used to test the error paths of some initialization 1058 * functions called either directly from xe_pci_probe() or indirectly for 1059 * example through xe_device_probe(). Those functions use the kernel fault 1060 * injection capabilities infrastructure, see 1061 * Documentation/fault-injection/fault-injection.rst for details. The macro 1062 * ALLOW_ERROR_INJECTION() is used to conditionally skip function execution 1063 * at runtime and use a provided return value. The first requirement for 1064 * error injectable functions is proper handling of the error code by the 1065 * caller for recovery, which is always the case here. The second 1066 * requirement is that no state is changed before the first error return. 1067 * It is not strictly fulfilled for all initialization functions using the 1068 * ALLOW_ERROR_INJECTION() macro but this is acceptable because for those 1069 * error cases at probe time, the error code is simply propagated up by the 1070 * caller. Therefore there is no consequence on those specific callers when 1071 * function error injection skips the whole function. 1072 */ 1073 static int xe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1074 { 1075 const struct xe_device_desc *desc = (const void *)ent->driver_data; 1076 const struct xe_subplatform_desc *subplatform_desc; 1077 struct xe_device *xe; 1078 int err; 1079 1080 subplatform_desc = find_subplatform(desc, pdev->device); 1081 1082 xe_configfs_check_device(pdev); 1083 1084 if (desc->require_force_probe && !id_forced(pdev->device)) { 1085 dev_info(&pdev->dev, 1086 "Your graphics device %04x is not officially supported\n" 1087 "by xe driver in this kernel version. To force Xe probe,\n" 1088 "use xe.force_probe='%04x' and i915.force_probe='!%04x'\n" 1089 "module parameters or CONFIG_DRM_XE_FORCE_PROBE='%04x' and\n" 1090 "CONFIG_DRM_I915_FORCE_PROBE='!%04x' configuration options.\n", 1091 pdev->device, pdev->device, pdev->device, 1092 pdev->device, pdev->device); 1093 return -ENODEV; 1094 } 1095 1096 if (id_blocked(pdev->device)) { 1097 dev_info(&pdev->dev, "Probe blocked for device [%04x:%04x].\n", 1098 pdev->vendor, pdev->device); 1099 return -ENODEV; 1100 } 1101 1102 if (xe_display_driver_probe_defer(pdev)) 1103 return -EPROBE_DEFER; 1104 1105 err = pcim_enable_device(pdev); 1106 if (err) 1107 return err; 1108 1109 xe = xe_device_create(pdev); 1110 if (IS_ERR(xe)) 1111 return PTR_ERR(xe); 1112 1113 pci_set_drvdata(pdev, &xe->drm); 1114 1115 xe_pm_assert_unbounded_bridge(xe); 1116 1117 pci_set_master(pdev); 1118 1119 err = xe_info_init_early(xe, desc, subplatform_desc); 1120 if (err) 1121 return err; 1122 1123 xe_pci_rebar_resize(xe); 1124 1125 err = xe_device_probe_early(xe); 1126 /* 1127 * In Boot Survivability mode, no drm card is exposed and driver 1128 * is loaded with bare minimum to allow for firmware to be 1129 * flashed through mei. Return success, if survivability mode 1130 * is enabled due to pcode failure or configfs being set 1131 */ 1132 if (xe_survivability_mode_is_boot_enabled(xe)) 1133 return 0; 1134 1135 if (err) 1136 return err; 1137 1138 err = xe_info_init(xe, desc); 1139 if (err) 1140 return err; 1141 1142 err = xe_display_probe(xe); 1143 if (err) 1144 return err; 1145 1146 drm_dbg(&xe->drm, "%s %s %04x:%04x dgfx:%d gfx:%s (%d.%02d) media:%s (%d.%02d) display:%s dma_m_s:%d tc:%d gscfi:%d cscfi:%d", 1147 desc->platform_name, 1148 subplatform_desc ? subplatform_desc->name : "", 1149 xe->info.devid, xe->info.revid, 1150 xe->info.is_dgfx, 1151 xe->info.graphics_name, 1152 xe->info.graphics_verx100 / 100, 1153 xe->info.graphics_verx100 % 100, 1154 xe->info.media_name, 1155 xe->info.media_verx100 / 100, 1156 xe->info.media_verx100 % 100, 1157 str_yes_no(xe->info.probe_display), 1158 xe->info.dma_mask_size, xe->info.tile_count, 1159 xe->info.has_heci_gscfi, xe->info.has_heci_cscfi); 1160 1161 drm_dbg(&xe->drm, "Stepping = (G:%s, M:%s, B:%s)\n", 1162 xe_step_name(xe->info.step.graphics), 1163 xe_step_name(xe->info.step.media), 1164 xe_step_name(xe->info.step.basedie)); 1165 1166 drm_dbg(&xe->drm, "SR-IOV support: %s (mode: %s)\n", 1167 str_yes_no(xe_device_has_sriov(xe)), 1168 xe_sriov_mode_to_string(xe_device_sriov_mode(xe))); 1169 1170 err = xe_pm_probe(xe); 1171 if (err) 1172 return err; 1173 1174 err = xe_device_probe(xe); 1175 if (err) 1176 return err; 1177 1178 err = xe_pm_init(xe); 1179 if (err) 1180 goto err_driver_cleanup; 1181 1182 return 0; 1183 1184 err_driver_cleanup: 1185 xe_pci_remove(pdev); 1186 return err; 1187 } 1188 1189 static void xe_pci_shutdown(struct pci_dev *pdev) 1190 { 1191 xe_device_shutdown(pdev_to_xe_device(pdev)); 1192 } 1193 1194 #ifdef CONFIG_PM_SLEEP 1195 static void d3cold_toggle(struct pci_dev *pdev, enum toggle_d3cold toggle) 1196 { 1197 struct xe_device *xe = pdev_to_xe_device(pdev); 1198 struct pci_dev *root_pdev; 1199 1200 if (!xe->d3cold.capable) 1201 return; 1202 1203 root_pdev = pcie_find_root_port(pdev); 1204 if (!root_pdev) 1205 return; 1206 1207 switch (toggle) { 1208 case D3COLD_DISABLE: 1209 pci_d3cold_disable(root_pdev); 1210 break; 1211 case D3COLD_ENABLE: 1212 pci_d3cold_enable(root_pdev); 1213 break; 1214 } 1215 } 1216 1217 static int xe_pci_suspend(struct device *dev) 1218 { 1219 struct pci_dev *pdev = to_pci_dev(dev); 1220 struct xe_device *xe = pdev_to_xe_device(pdev); 1221 int err; 1222 1223 if (xe_survivability_mode_is_boot_enabled(xe)) 1224 return -EBUSY; 1225 1226 err = xe_pm_suspend(xe); 1227 if (err) 1228 return err; 1229 1230 /* 1231 * Enabling D3Cold is needed for S2Idle/S0ix. 1232 * It is save to allow here since xe_pm_suspend has evicted 1233 * the local memory and the direct complete optimization is disabled. 1234 */ 1235 d3cold_toggle(pdev, D3COLD_ENABLE); 1236 1237 pci_save_state(pdev); 1238 pci_disable_device(pdev); 1239 pci_set_power_state(pdev, PCI_D3cold); 1240 1241 return 0; 1242 } 1243 1244 static int xe_pci_resume(struct device *dev) 1245 { 1246 struct pci_dev *pdev = to_pci_dev(dev); 1247 int err; 1248 1249 /* Give back the D3Cold decision to the runtime P M*/ 1250 d3cold_toggle(pdev, D3COLD_DISABLE); 1251 1252 err = pci_set_power_state(pdev, PCI_D0); 1253 if (err) 1254 return err; 1255 1256 pci_restore_state(pdev); 1257 1258 err = pci_enable_device(pdev); 1259 if (err) 1260 return err; 1261 1262 pci_set_master(pdev); 1263 1264 err = xe_pm_resume(pdev_to_xe_device(pdev)); 1265 if (err) 1266 return err; 1267 1268 return 0; 1269 } 1270 1271 static int xe_pci_runtime_suspend(struct device *dev) 1272 { 1273 struct pci_dev *pdev = to_pci_dev(dev); 1274 struct xe_device *xe = pdev_to_xe_device(pdev); 1275 int err; 1276 1277 /* 1278 * We hold an additional reference to the runtime PM to keep PF in D0 1279 * during VFs lifetime, as our VFs do not implement the PM capability. 1280 * This means we should never be runtime suspending as long as VFs are 1281 * enabled. 1282 */ 1283 xe_assert(xe, !IS_SRIOV_VF(xe)); 1284 xe_assert(xe, !pci_num_vf(pdev)); 1285 1286 err = xe_pm_runtime_suspend(xe); 1287 if (err) 1288 return err; 1289 1290 pci_save_state(pdev); 1291 1292 if (xe->d3cold.allowed) { 1293 d3cold_toggle(pdev, D3COLD_ENABLE); 1294 pci_disable_device(pdev); 1295 pci_ignore_hotplug(pdev); 1296 pci_set_power_state(pdev, PCI_D3cold); 1297 } else { 1298 d3cold_toggle(pdev, D3COLD_DISABLE); 1299 pci_set_power_state(pdev, PCI_D3hot); 1300 } 1301 1302 return 0; 1303 } 1304 1305 static int xe_pci_runtime_resume(struct device *dev) 1306 { 1307 struct pci_dev *pdev = to_pci_dev(dev); 1308 struct xe_device *xe = pdev_to_xe_device(pdev); 1309 int err; 1310 1311 err = pci_set_power_state(pdev, PCI_D0); 1312 if (err) 1313 return err; 1314 1315 pci_restore_state(pdev); 1316 1317 if (xe->d3cold.allowed) { 1318 err = pci_enable_device(pdev); 1319 if (err) 1320 return err; 1321 1322 pci_set_master(pdev); 1323 } 1324 1325 return xe_pm_runtime_resume(xe); 1326 } 1327 1328 static int xe_pci_runtime_idle(struct device *dev) 1329 { 1330 struct pci_dev *pdev = to_pci_dev(dev); 1331 struct xe_device *xe = pdev_to_xe_device(pdev); 1332 1333 xe_pm_d3cold_allowed_toggle(xe); 1334 1335 return 0; 1336 } 1337 1338 static const struct dev_pm_ops xe_pm_ops = { 1339 SET_SYSTEM_SLEEP_PM_OPS(xe_pci_suspend, xe_pci_resume) 1340 SET_RUNTIME_PM_OPS(xe_pci_runtime_suspend, xe_pci_runtime_resume, xe_pci_runtime_idle) 1341 }; 1342 #endif 1343 1344 static struct pci_driver xe_pci_driver = { 1345 .name = DRIVER_NAME, 1346 .id_table = pciidlist, 1347 .probe = xe_pci_probe, 1348 .remove = xe_pci_remove, 1349 .shutdown = xe_pci_shutdown, 1350 .sriov_configure = xe_pci_sriov_configure, 1351 #ifdef CONFIG_PM_SLEEP 1352 .driver.pm = &xe_pm_ops, 1353 #endif 1354 }; 1355 1356 /** 1357 * xe_pci_to_pf_device() - Get PF &xe_device. 1358 * @pdev: the VF &pci_dev device 1359 * 1360 * Return: pointer to PF &xe_device, NULL otherwise. 1361 */ 1362 struct xe_device *xe_pci_to_pf_device(struct pci_dev *pdev) 1363 { 1364 struct drm_device *drm; 1365 1366 drm = pci_iov_get_pf_drvdata(pdev, &xe_pci_driver); 1367 if (IS_ERR(drm)) 1368 return NULL; 1369 1370 return to_xe_device(drm); 1371 } 1372 1373 int xe_register_pci_driver(void) 1374 { 1375 return pci_register_driver(&xe_pci_driver); 1376 } 1377 1378 void xe_unregister_pci_driver(void) 1379 { 1380 pci_unregister_driver(&xe_pci_driver); 1381 } 1382 1383 #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST) 1384 #include "tests/xe_pci.c" 1385 #endif 1386