1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 #include "xe_pci.h" 7 8 #include <kunit/static_stub.h> 9 #include <linux/device/driver.h> 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/pm_runtime.h> 13 14 #include <drm/drm_color_mgmt.h> 15 #include <drm/drm_drv.h> 16 #include <drm/intel/xe_pciids.h> 17 18 #include "display/xe_display.h" 19 #include "regs/xe_gt_regs.h" 20 #include "xe_device.h" 21 #include "xe_drv.h" 22 #include "xe_gt.h" 23 #include "xe_gt_sriov_vf.h" 24 #include "xe_guc.h" 25 #include "xe_macros.h" 26 #include "xe_mmio.h" 27 #include "xe_module.h" 28 #include "xe_pci_sriov.h" 29 #include "xe_pci_types.h" 30 #include "xe_pm.h" 31 #include "xe_sriov.h" 32 #include "xe_step.h" 33 #include "xe_tile.h" 34 35 enum toggle_d3cold { 36 D3COLD_DISABLE, 37 D3COLD_ENABLE, 38 }; 39 40 struct xe_subplatform_desc { 41 enum xe_subplatform subplatform; 42 const char *name; 43 const u16 *pciidlist; 44 }; 45 46 struct xe_device_desc { 47 /* Should only ever be set for platforms without GMD_ID */ 48 const struct xe_graphics_desc *graphics; 49 /* Should only ever be set for platforms without GMD_ID */ 50 const struct xe_media_desc *media; 51 52 const char *platform_name; 53 const struct xe_subplatform_desc *subplatforms; 54 55 enum xe_platform platform; 56 57 u8 require_force_probe:1; 58 u8 is_dgfx:1; 59 60 u8 has_display:1; 61 u8 has_heci_gscfi:1; 62 u8 has_llc:1; 63 u8 has_mmio_ext:1; 64 u8 has_sriov:1; 65 u8 skip_guc_pc:1; 66 u8 skip_mtcfg:1; 67 u8 skip_pcode:1; 68 }; 69 70 __diag_push(); 71 __diag_ignore_all("-Woverride-init", "Allow field overrides in table"); 72 73 #define PLATFORM(x) \ 74 .platform = XE_##x, \ 75 .platform_name = #x 76 77 #define NOP(x) x 78 79 static const struct xe_graphics_desc graphics_xelp = { 80 .name = "Xe_LP", 81 .ver = 12, 82 .rel = 0, 83 84 .hw_engine_mask = BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0), 85 86 .dma_mask_size = 39, 87 .va_bits = 48, 88 .vm_max_level = 3, 89 }; 90 91 static const struct xe_graphics_desc graphics_xelpp = { 92 .name = "Xe_LP+", 93 .ver = 12, 94 .rel = 10, 95 96 .hw_engine_mask = BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0), 97 98 .dma_mask_size = 39, 99 .va_bits = 48, 100 .vm_max_level = 3, 101 }; 102 103 #define XE_HP_FEATURES \ 104 .has_range_tlb_invalidation = true, \ 105 .has_flat_ccs = true, \ 106 .dma_mask_size = 46, \ 107 .va_bits = 48, \ 108 .vm_max_level = 3 109 110 static const struct xe_graphics_desc graphics_xehpg = { 111 .name = "Xe_HPG", 112 .ver = 12, 113 .rel = 55, 114 115 .hw_engine_mask = 116 BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) | 117 BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) | 118 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3), 119 120 XE_HP_FEATURES, 121 .vram_flags = XE_VRAM_FLAGS_NEED64K, 122 }; 123 124 static const struct xe_graphics_desc graphics_xehpc = { 125 .name = "Xe_HPC", 126 .ver = 12, 127 .rel = 60, 128 129 .hw_engine_mask = 130 BIT(XE_HW_ENGINE_BCS0) | BIT(XE_HW_ENGINE_BCS1) | 131 BIT(XE_HW_ENGINE_BCS2) | BIT(XE_HW_ENGINE_BCS3) | 132 BIT(XE_HW_ENGINE_BCS4) | BIT(XE_HW_ENGINE_BCS5) | 133 BIT(XE_HW_ENGINE_BCS6) | BIT(XE_HW_ENGINE_BCS7) | 134 BIT(XE_HW_ENGINE_BCS8) | 135 BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) | 136 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3), 137 138 XE_HP_FEATURES, 139 .dma_mask_size = 52, 140 .max_remote_tiles = 1, 141 .va_bits = 57, 142 .vm_max_level = 4, 143 .vram_flags = XE_VRAM_FLAGS_NEED64K, 144 145 .has_asid = 1, 146 .has_atomic_enable_pte_bit = 1, 147 .has_flat_ccs = 0, 148 .has_usm = 1, 149 }; 150 151 static const struct xe_graphics_desc graphics_xelpg = { 152 .name = "Xe_LPG", 153 .hw_engine_mask = 154 BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) | 155 BIT(XE_HW_ENGINE_CCS0), 156 157 XE_HP_FEATURES, 158 .has_flat_ccs = 0, 159 }; 160 161 #define XE2_GFX_FEATURES \ 162 .dma_mask_size = 46, \ 163 .has_asid = 1, \ 164 .has_atomic_enable_pte_bit = 1, \ 165 .has_flat_ccs = 1, \ 166 .has_indirect_ring_state = 1, \ 167 .has_range_tlb_invalidation = 1, \ 168 .has_usm = 1, \ 169 .va_bits = 48, \ 170 .vm_max_level = 4, \ 171 .hw_engine_mask = \ 172 BIT(XE_HW_ENGINE_RCS0) | \ 173 BIT(XE_HW_ENGINE_BCS8) | BIT(XE_HW_ENGINE_BCS0) | \ 174 GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0) 175 176 static const struct xe_graphics_desc graphics_xe2 = { 177 .name = "Xe2_LPG / Xe2_HPG", 178 179 XE2_GFX_FEATURES, 180 }; 181 182 static const struct xe_media_desc media_xem = { 183 .name = "Xe_M", 184 .ver = 12, 185 .rel = 0, 186 187 .hw_engine_mask = 188 GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) | 189 GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0), 190 }; 191 192 static const struct xe_media_desc media_xehpm = { 193 .name = "Xe_HPM", 194 .ver = 12, 195 .rel = 55, 196 197 .hw_engine_mask = 198 GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) | 199 GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0), 200 }; 201 202 static const struct xe_media_desc media_xelpmp = { 203 .name = "Xe_LPM+", 204 .hw_engine_mask = 205 GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) | 206 GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0) | 207 BIT(XE_HW_ENGINE_GSCCS0) 208 }; 209 210 static const struct xe_media_desc media_xe2 = { 211 .name = "Xe2_LPM / Xe2_HPM", 212 .hw_engine_mask = 213 GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) | 214 GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0) | 215 BIT(XE_HW_ENGINE_GSCCS0) 216 }; 217 218 static const struct xe_device_desc tgl_desc = { 219 .graphics = &graphics_xelp, 220 .media = &media_xem, 221 PLATFORM(TIGERLAKE), 222 .has_display = true, 223 .has_llc = true, 224 .require_force_probe = true, 225 }; 226 227 static const struct xe_device_desc rkl_desc = { 228 .graphics = &graphics_xelp, 229 .media = &media_xem, 230 PLATFORM(ROCKETLAKE), 231 .has_display = true, 232 .has_llc = true, 233 .require_force_probe = true, 234 }; 235 236 static const u16 adls_rpls_ids[] = { XE_RPLS_IDS(NOP), 0 }; 237 238 static const struct xe_device_desc adl_s_desc = { 239 .graphics = &graphics_xelp, 240 .media = &media_xem, 241 PLATFORM(ALDERLAKE_S), 242 .has_display = true, 243 .has_llc = true, 244 .require_force_probe = true, 245 .subplatforms = (const struct xe_subplatform_desc[]) { 246 { XE_SUBPLATFORM_ALDERLAKE_S_RPLS, "RPLS", adls_rpls_ids }, 247 {}, 248 }, 249 }; 250 251 static const u16 adlp_rplu_ids[] = { XE_RPLU_IDS(NOP), 0 }; 252 253 static const struct xe_device_desc adl_p_desc = { 254 .graphics = &graphics_xelp, 255 .media = &media_xem, 256 PLATFORM(ALDERLAKE_P), 257 .has_display = true, 258 .has_llc = true, 259 .require_force_probe = true, 260 .subplatforms = (const struct xe_subplatform_desc[]) { 261 { XE_SUBPLATFORM_ALDERLAKE_P_RPLU, "RPLU", adlp_rplu_ids }, 262 {}, 263 }, 264 }; 265 266 static const struct xe_device_desc adl_n_desc = { 267 .graphics = &graphics_xelp, 268 .media = &media_xem, 269 PLATFORM(ALDERLAKE_N), 270 .has_display = true, 271 .has_llc = true, 272 .require_force_probe = true, 273 }; 274 275 #define DGFX_FEATURES \ 276 .is_dgfx = 1 277 278 static const struct xe_device_desc dg1_desc = { 279 .graphics = &graphics_xelpp, 280 .media = &media_xem, 281 DGFX_FEATURES, 282 PLATFORM(DG1), 283 .has_display = true, 284 .has_heci_gscfi = 1, 285 .require_force_probe = true, 286 }; 287 288 static const u16 dg2_g10_ids[] = { XE_DG2_G10_IDS(NOP), XE_ATS_M150_IDS(NOP), 0 }; 289 static const u16 dg2_g11_ids[] = { XE_DG2_G11_IDS(NOP), XE_ATS_M75_IDS(NOP), 0 }; 290 static const u16 dg2_g12_ids[] = { XE_DG2_G12_IDS(NOP), 0 }; 291 292 #define DG2_FEATURES \ 293 DGFX_FEATURES, \ 294 PLATFORM(DG2), \ 295 .has_heci_gscfi = 1, \ 296 .subplatforms = (const struct xe_subplatform_desc[]) { \ 297 { XE_SUBPLATFORM_DG2_G10, "G10", dg2_g10_ids }, \ 298 { XE_SUBPLATFORM_DG2_G11, "G11", dg2_g11_ids }, \ 299 { XE_SUBPLATFORM_DG2_G12, "G12", dg2_g12_ids }, \ 300 { } \ 301 } 302 303 static const struct xe_device_desc ats_m_desc = { 304 .graphics = &graphics_xehpg, 305 .media = &media_xehpm, 306 .require_force_probe = true, 307 308 DG2_FEATURES, 309 .has_display = false, 310 }; 311 312 static const struct xe_device_desc dg2_desc = { 313 .graphics = &graphics_xehpg, 314 .media = &media_xehpm, 315 .require_force_probe = true, 316 317 DG2_FEATURES, 318 .has_display = true, 319 }; 320 321 static const __maybe_unused struct xe_device_desc pvc_desc = { 322 .graphics = &graphics_xehpc, 323 DGFX_FEATURES, 324 PLATFORM(PVC), 325 .has_display = false, 326 .has_heci_gscfi = 1, 327 .require_force_probe = true, 328 }; 329 330 static const struct xe_device_desc mtl_desc = { 331 /* .graphics and .media determined via GMD_ID */ 332 .require_force_probe = true, 333 PLATFORM(METEORLAKE), 334 .has_display = true, 335 }; 336 337 static const struct xe_device_desc lnl_desc = { 338 PLATFORM(LUNARLAKE), 339 .has_display = true, 340 .require_force_probe = true, 341 }; 342 343 static const struct xe_device_desc bmg_desc __maybe_unused = { 344 DGFX_FEATURES, 345 PLATFORM(BATTLEMAGE), 346 .has_display = true, 347 .require_force_probe = true, 348 }; 349 350 #undef PLATFORM 351 __diag_pop(); 352 353 /* Map of GMD_ID values to graphics IP */ 354 static const struct gmdid_map graphics_ip_map[] = { 355 { 1270, &graphics_xelpg }, 356 { 1271, &graphics_xelpg }, 357 { 1274, &graphics_xelpg }, /* Xe_LPG+ */ 358 { 2001, &graphics_xe2 }, 359 { 2004, &graphics_xe2 }, 360 }; 361 362 /* Map of GMD_ID values to media IP */ 363 static const struct gmdid_map media_ip_map[] = { 364 { 1300, &media_xelpmp }, 365 { 1301, &media_xe2 }, 366 { 2000, &media_xe2 }, 367 }; 368 369 #define INTEL_VGA_DEVICE(id, info) { \ 370 PCI_DEVICE(PCI_VENDOR_ID_INTEL, id), \ 371 PCI_BASE_CLASS_DISPLAY << 16, 0xff << 16, \ 372 (unsigned long) info } 373 374 /* 375 * Make sure any device matches here are from most specific to most 376 * general. For example, since the Quanta match is based on the subsystem 377 * and subvendor IDs, we need it to come before the more general IVB 378 * PCI ID matches, otherwise we'll use the wrong info struct above. 379 */ 380 static const struct pci_device_id pciidlist[] = { 381 XE_TGL_IDS(INTEL_VGA_DEVICE, &tgl_desc), 382 XE_RKL_IDS(INTEL_VGA_DEVICE, &rkl_desc), 383 XE_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc), 384 XE_ADLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 385 XE_ADLN_IDS(INTEL_VGA_DEVICE, &adl_n_desc), 386 XE_RPLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 387 XE_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc), 388 XE_DG1_IDS(INTEL_VGA_DEVICE, &dg1_desc), 389 XE_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_desc), 390 XE_DG2_IDS(INTEL_VGA_DEVICE, &dg2_desc), 391 XE_MTL_IDS(INTEL_VGA_DEVICE, &mtl_desc), 392 XE_LNL_IDS(INTEL_VGA_DEVICE, &lnl_desc), 393 { } 394 }; 395 MODULE_DEVICE_TABLE(pci, pciidlist); 396 397 #undef INTEL_VGA_DEVICE 398 399 /* is device_id present in comma separated list of ids */ 400 static bool device_id_in_list(u16 device_id, const char *devices, bool negative) 401 { 402 char *s, *p, *tok; 403 bool ret; 404 405 if (!devices || !*devices) 406 return false; 407 408 /* match everything */ 409 if (negative && strcmp(devices, "!*") == 0) 410 return true; 411 if (!negative && strcmp(devices, "*") == 0) 412 return true; 413 414 s = kstrdup(devices, GFP_KERNEL); 415 if (!s) 416 return false; 417 418 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) { 419 u16 val; 420 421 if (negative && tok[0] == '!') 422 tok++; 423 else if ((negative && tok[0] != '!') || 424 (!negative && tok[0] == '!')) 425 continue; 426 427 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) { 428 ret = true; 429 break; 430 } 431 } 432 433 kfree(s); 434 435 return ret; 436 } 437 438 static bool id_forced(u16 device_id) 439 { 440 return device_id_in_list(device_id, xe_modparam.force_probe, false); 441 } 442 443 static bool id_blocked(u16 device_id) 444 { 445 return device_id_in_list(device_id, xe_modparam.force_probe, true); 446 } 447 448 static const struct xe_subplatform_desc * 449 find_subplatform(const struct xe_device *xe, const struct xe_device_desc *desc) 450 { 451 const struct xe_subplatform_desc *sp; 452 const u16 *id; 453 454 for (sp = desc->subplatforms; sp && sp->subplatform; sp++) 455 for (id = sp->pciidlist; *id; id++) 456 if (*id == xe->info.devid) 457 return sp; 458 459 return NULL; 460 } 461 462 enum xe_gmdid_type { 463 GMDID_GRAPHICS, 464 GMDID_MEDIA 465 }; 466 467 static void read_gmdid(struct xe_device *xe, enum xe_gmdid_type type, u32 *ver, u32 *revid) 468 { 469 struct xe_gt *gt = xe_root_mmio_gt(xe); 470 struct xe_reg gmdid_reg = GMD_ID; 471 u32 val; 472 473 KUNIT_STATIC_STUB_REDIRECT(read_gmdid, xe, type, ver, revid); 474 475 if (IS_SRIOV_VF(xe)) { 476 /* 477 * To get the value of the GMDID register, VFs must obtain it 478 * from the GuC using MMIO communication. 479 * 480 * Note that at this point the xe_gt is not fully uninitialized 481 * and only basic access to MMIO registers is possible. To use 482 * our existing GuC communication functions we must perform at 483 * least basic xe_gt and xe_guc initialization. 484 * 485 * Since to obtain the value of GMDID_MEDIA we need to use the 486 * media GuC, temporarly tweak the gt type. 487 */ 488 xe_gt_assert(gt, gt->info.type == XE_GT_TYPE_UNINITIALIZED); 489 490 if (type == GMDID_MEDIA) { 491 gt->info.id = 1; 492 gt->info.type = XE_GT_TYPE_MEDIA; 493 } else { 494 gt->info.id = 0; 495 gt->info.type = XE_GT_TYPE_MAIN; 496 } 497 498 xe_guc_comm_init_early(>->uc.guc); 499 500 /* Don't bother with GMDID if failed to negotiate the GuC ABI */ 501 val = xe_gt_sriov_vf_bootstrap(gt) ? 0 : xe_gt_sriov_vf_gmdid(gt); 502 503 /* 504 * Only undo xe_gt.info here, the remaining changes made above 505 * will be overwritten as part of the regular initialization. 506 */ 507 gt->info.id = 0; 508 gt->info.type = XE_GT_TYPE_UNINITIALIZED; 509 } else { 510 /* 511 * We need to apply the GSI offset explicitly here as at this 512 * point the xe_gt is not fully uninitialized and only basic 513 * access to MMIO registers is possible. 514 */ 515 if (type == GMDID_MEDIA) 516 gmdid_reg.addr += MEDIA_GT_GSI_OFFSET; 517 518 val = xe_mmio_read32(gt, gmdid_reg); 519 } 520 521 *ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val) * 100 + REG_FIELD_GET(GMD_ID_RELEASE_MASK, val); 522 *revid = REG_FIELD_GET(GMD_ID_REVID, val); 523 } 524 525 /* 526 * Pre-GMD_ID platform: device descriptor already points to the appropriate 527 * graphics descriptor. Simply forward the description and calculate the version 528 * appropriately. "graphics" should be present in all such platforms, while 529 * media is optional. 530 */ 531 static void handle_pre_gmdid(struct xe_device *xe, 532 const struct xe_graphics_desc *graphics, 533 const struct xe_media_desc *media) 534 { 535 xe->info.graphics_verx100 = graphics->ver * 100 + graphics->rel; 536 537 if (media) 538 xe->info.media_verx100 = media->ver * 100 + media->rel; 539 540 } 541 542 /* 543 * GMD_ID platform: read IP version from hardware and select graphics descriptor 544 * based on the result. 545 */ 546 static void handle_gmdid(struct xe_device *xe, 547 const struct xe_graphics_desc **graphics, 548 const struct xe_media_desc **media, 549 u32 *graphics_revid, 550 u32 *media_revid) 551 { 552 u32 ver; 553 554 read_gmdid(xe, GMDID_GRAPHICS, &ver, graphics_revid); 555 556 for (int i = 0; i < ARRAY_SIZE(graphics_ip_map); i++) { 557 if (ver == graphics_ip_map[i].ver) { 558 xe->info.graphics_verx100 = ver; 559 *graphics = graphics_ip_map[i].ip; 560 561 break; 562 } 563 } 564 565 if (!xe->info.graphics_verx100) { 566 drm_err(&xe->drm, "Hardware reports unknown graphics version %u.%02u\n", 567 ver / 100, ver % 100); 568 } 569 570 read_gmdid(xe, GMDID_MEDIA, &ver, media_revid); 571 572 /* Media may legitimately be fused off / not present */ 573 if (ver == 0) 574 return; 575 576 for (int i = 0; i < ARRAY_SIZE(media_ip_map); i++) { 577 if (ver == media_ip_map[i].ver) { 578 xe->info.media_verx100 = ver; 579 *media = media_ip_map[i].ip; 580 581 break; 582 } 583 } 584 585 if (!xe->info.media_verx100) { 586 drm_err(&xe->drm, "Hardware reports unknown media version %u.%02u\n", 587 ver / 100, ver % 100); 588 } 589 } 590 591 /* 592 * Initialize device info content that only depends on static driver_data 593 * passed to the driver at probe time from PCI ID table. 594 */ 595 static int xe_info_init_early(struct xe_device *xe, 596 const struct xe_device_desc *desc, 597 const struct xe_subplatform_desc *subplatform_desc) 598 { 599 int err; 600 601 xe->info.platform_name = desc->platform_name; 602 xe->info.platform = desc->platform; 603 xe->info.subplatform = subplatform_desc ? 604 subplatform_desc->subplatform : XE_SUBPLATFORM_NONE; 605 606 xe->info.is_dgfx = desc->is_dgfx; 607 xe->info.has_heci_gscfi = desc->has_heci_gscfi; 608 xe->info.has_llc = desc->has_llc; 609 xe->info.has_mmio_ext = desc->has_mmio_ext; 610 xe->info.has_sriov = desc->has_sriov; 611 xe->info.skip_guc_pc = desc->skip_guc_pc; 612 xe->info.skip_mtcfg = desc->skip_mtcfg; 613 xe->info.skip_pcode = desc->skip_pcode; 614 615 xe->info.enable_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) && 616 xe_modparam.enable_display && 617 desc->has_display; 618 619 err = xe_tile_init_early(xe_device_get_root_tile(xe), xe, 0); 620 if (err) 621 return err; 622 623 return 0; 624 } 625 626 /* 627 * Initialize device info content that does require knowledge about 628 * graphics / media IP version. 629 * Make sure that GT / tile structures allocated by the driver match the data 630 * present in device info. 631 */ 632 static int xe_info_init(struct xe_device *xe, 633 const struct xe_graphics_desc *graphics_desc, 634 const struct xe_media_desc *media_desc) 635 { 636 u32 graphics_gmdid_revid = 0, media_gmdid_revid = 0; 637 struct xe_tile *tile; 638 struct xe_gt *gt; 639 u8 id; 640 641 /* 642 * If this platform supports GMD_ID, we'll detect the proper IP 643 * descriptor to use from hardware registers. desc->graphics will only 644 * ever be set at this point for platforms before GMD_ID. In that case 645 * the IP descriptions and versions are simply derived from that. 646 */ 647 if (graphics_desc) { 648 handle_pre_gmdid(xe, graphics_desc, media_desc); 649 xe->info.step = xe_step_pre_gmdid_get(xe); 650 } else { 651 xe_assert(xe, !media_desc); 652 handle_gmdid(xe, &graphics_desc, &media_desc, 653 &graphics_gmdid_revid, &media_gmdid_revid); 654 xe->info.step = xe_step_gmdid_get(xe, 655 graphics_gmdid_revid, 656 media_gmdid_revid); 657 } 658 659 /* 660 * If we couldn't detect the graphics IP, that's considered a fatal 661 * error and we should abort driver load. Failing to detect media 662 * IP is non-fatal; we'll just proceed without enabling media support. 663 */ 664 if (!graphics_desc) 665 return -ENODEV; 666 667 xe->info.graphics_name = graphics_desc->name; 668 xe->info.media_name = media_desc ? media_desc->name : "none"; 669 xe->info.tile_mmio_ext_size = graphics_desc->tile_mmio_ext_size; 670 671 xe->info.dma_mask_size = graphics_desc->dma_mask_size; 672 xe->info.vram_flags = graphics_desc->vram_flags; 673 xe->info.va_bits = graphics_desc->va_bits; 674 xe->info.vm_max_level = graphics_desc->vm_max_level; 675 xe->info.has_asid = graphics_desc->has_asid; 676 xe->info.has_atomic_enable_pte_bit = graphics_desc->has_atomic_enable_pte_bit; 677 if (xe->info.platform != XE_PVC) 678 xe->info.has_device_atomics_on_smem = 1; 679 xe->info.has_flat_ccs = graphics_desc->has_flat_ccs; 680 xe->info.has_range_tlb_invalidation = graphics_desc->has_range_tlb_invalidation; 681 xe->info.has_usm = graphics_desc->has_usm; 682 683 /* 684 * All platforms have at least one primary GT. Any platform with media 685 * version 13 or higher has an additional dedicated media GT. And 686 * depending on the graphics IP there may be additional "remote tiles." 687 * All of these together determine the overall GT count. 688 * 689 * FIXME: 'tile_count' here is misnamed since the rest of the driver 690 * treats it as the number of GTs rather than just the number of tiles. 691 */ 692 xe->info.tile_count = 1 + graphics_desc->max_remote_tiles; 693 694 for_each_remote_tile(tile, xe, id) { 695 int err; 696 697 err = xe_tile_init_early(tile, xe, id); 698 if (err) 699 return err; 700 } 701 702 for_each_tile(tile, xe, id) { 703 gt = tile->primary_gt; 704 gt->info.id = xe->info.gt_count++; 705 gt->info.type = XE_GT_TYPE_MAIN; 706 gt->info.has_indirect_ring_state = graphics_desc->has_indirect_ring_state; 707 gt->info.engine_mask = graphics_desc->hw_engine_mask; 708 if (MEDIA_VER(xe) < 13 && media_desc) 709 gt->info.engine_mask |= media_desc->hw_engine_mask; 710 711 if (MEDIA_VER(xe) < 13 || !media_desc) 712 continue; 713 714 /* 715 * Allocate and setup media GT for platforms with standalone 716 * media. 717 */ 718 tile->media_gt = xe_gt_alloc(tile); 719 if (IS_ERR(tile->media_gt)) 720 return PTR_ERR(tile->media_gt); 721 722 gt = tile->media_gt; 723 gt->info.type = XE_GT_TYPE_MEDIA; 724 gt->info.has_indirect_ring_state = media_desc->has_indirect_ring_state; 725 gt->info.engine_mask = media_desc->hw_engine_mask; 726 gt->mmio.adj_offset = MEDIA_GT_GSI_OFFSET; 727 gt->mmio.adj_limit = MEDIA_GT_GSI_LENGTH; 728 729 /* 730 * FIXME: At the moment multi-tile and standalone media are 731 * mutually exclusive on current platforms. We'll need to 732 * come up with a better way to number GTs if we ever wind 733 * up with platforms that support both together. 734 */ 735 drm_WARN_ON(&xe->drm, id != 0); 736 gt->info.id = xe->info.gt_count++; 737 } 738 739 return 0; 740 } 741 742 static void xe_pci_remove(struct pci_dev *pdev) 743 { 744 struct xe_device *xe; 745 746 xe = pci_get_drvdata(pdev); 747 if (!xe) /* driver load aborted, nothing to cleanup */ 748 return; 749 750 xe_device_remove(xe); 751 xe_pm_runtime_fini(xe); 752 pci_set_drvdata(pdev, NULL); 753 } 754 755 static int xe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 756 { 757 const struct xe_device_desc *desc = (const void *)ent->driver_data; 758 const struct xe_subplatform_desc *subplatform_desc; 759 struct xe_device *xe; 760 int err; 761 762 if (desc->require_force_probe && !id_forced(pdev->device)) { 763 dev_info(&pdev->dev, 764 "Your graphics device %04x is not officially supported\n" 765 "by xe driver in this kernel version. To force Xe probe,\n" 766 "use xe.force_probe='%04x' and i915.force_probe='!%04x'\n" 767 "module parameters or CONFIG_DRM_XE_FORCE_PROBE='%04x' and\n" 768 "CONFIG_DRM_I915_FORCE_PROBE='!%04x' configuration options.\n", 769 pdev->device, pdev->device, pdev->device, 770 pdev->device, pdev->device); 771 return -ENODEV; 772 } 773 774 if (id_blocked(pdev->device)) { 775 dev_info(&pdev->dev, "Probe blocked for device [%04x:%04x].\n", 776 pdev->vendor, pdev->device); 777 return -ENODEV; 778 } 779 780 if (xe_display_driver_probe_defer(pdev)) 781 return -EPROBE_DEFER; 782 783 err = pcim_enable_device(pdev); 784 if (err) 785 return err; 786 787 xe = xe_device_create(pdev, ent); 788 if (IS_ERR(xe)) 789 return PTR_ERR(xe); 790 791 pci_set_drvdata(pdev, xe); 792 793 xe_pm_assert_unbounded_bridge(xe); 794 subplatform_desc = find_subplatform(xe, desc); 795 796 pci_set_master(pdev); 797 798 err = xe_info_init_early(xe, desc, subplatform_desc); 799 if (err) 800 return err; 801 802 err = xe_device_probe_early(xe); 803 if (err) 804 return err; 805 806 err = xe_info_init(xe, desc->graphics, desc->media); 807 if (err) 808 return err; 809 810 err = xe_display_probe(xe); 811 if (err) 812 return err; 813 814 drm_dbg(&xe->drm, "%s %s %04x:%04x dgfx:%d gfx:%s (%d.%02d) media:%s (%d.%02d) display:%s dma_m_s:%d tc:%d gscfi:%d", 815 desc->platform_name, 816 subplatform_desc ? subplatform_desc->name : "", 817 xe->info.devid, xe->info.revid, 818 xe->info.is_dgfx, 819 xe->info.graphics_name, 820 xe->info.graphics_verx100 / 100, 821 xe->info.graphics_verx100 % 100, 822 xe->info.media_name, 823 xe->info.media_verx100 / 100, 824 xe->info.media_verx100 % 100, 825 str_yes_no(xe->info.enable_display), 826 xe->info.dma_mask_size, xe->info.tile_count, 827 xe->info.has_heci_gscfi); 828 829 drm_dbg(&xe->drm, "Stepping = (G:%s, M:%s, D:%s, B:%s)\n", 830 xe_step_name(xe->info.step.graphics), 831 xe_step_name(xe->info.step.media), 832 xe_step_name(xe->info.step.display), 833 xe_step_name(xe->info.step.basedie)); 834 835 drm_dbg(&xe->drm, "SR-IOV support: %s (mode: %s)\n", 836 str_yes_no(xe_device_has_sriov(xe)), 837 xe_sriov_mode_to_string(xe_device_sriov_mode(xe))); 838 839 err = xe_pm_init_early(xe); 840 if (err) 841 return err; 842 843 err = xe_device_probe(xe); 844 if (err) 845 return err; 846 847 err = xe_pm_init(xe); 848 if (err) 849 goto err_driver_cleanup; 850 851 drm_dbg(&xe->drm, "d3cold: capable=%s\n", 852 str_yes_no(xe->d3cold.capable)); 853 854 return 0; 855 856 err_driver_cleanup: 857 xe_pci_remove(pdev); 858 return err; 859 } 860 861 static void xe_pci_shutdown(struct pci_dev *pdev) 862 { 863 xe_device_shutdown(pdev_to_xe_device(pdev)); 864 } 865 866 #ifdef CONFIG_PM_SLEEP 867 static void d3cold_toggle(struct pci_dev *pdev, enum toggle_d3cold toggle) 868 { 869 struct xe_device *xe = pdev_to_xe_device(pdev); 870 struct pci_dev *root_pdev; 871 872 if (!xe->d3cold.capable) 873 return; 874 875 root_pdev = pcie_find_root_port(pdev); 876 if (!root_pdev) 877 return; 878 879 switch (toggle) { 880 case D3COLD_DISABLE: 881 pci_d3cold_disable(root_pdev); 882 break; 883 case D3COLD_ENABLE: 884 pci_d3cold_enable(root_pdev); 885 break; 886 } 887 } 888 889 static int xe_pci_suspend(struct device *dev) 890 { 891 struct pci_dev *pdev = to_pci_dev(dev); 892 int err; 893 894 err = xe_pm_suspend(pdev_to_xe_device(pdev)); 895 if (err) 896 return err; 897 898 /* 899 * Enabling D3Cold is needed for S2Idle/S0ix. 900 * It is save to allow here since xe_pm_suspend has evicted 901 * the local memory and the direct complete optimization is disabled. 902 */ 903 d3cold_toggle(pdev, D3COLD_ENABLE); 904 905 pci_save_state(pdev); 906 pci_disable_device(pdev); 907 908 return 0; 909 } 910 911 static int xe_pci_resume(struct device *dev) 912 { 913 struct pci_dev *pdev = to_pci_dev(dev); 914 int err; 915 916 /* Give back the D3Cold decision to the runtime P M*/ 917 d3cold_toggle(pdev, D3COLD_DISABLE); 918 919 err = pci_set_power_state(pdev, PCI_D0); 920 if (err) 921 return err; 922 923 err = pci_enable_device(pdev); 924 if (err) 925 return err; 926 927 pci_set_master(pdev); 928 929 err = xe_pm_resume(pdev_to_xe_device(pdev)); 930 if (err) 931 return err; 932 933 return 0; 934 } 935 936 static int xe_pci_runtime_suspend(struct device *dev) 937 { 938 struct pci_dev *pdev = to_pci_dev(dev); 939 struct xe_device *xe = pdev_to_xe_device(pdev); 940 int err; 941 942 err = xe_pm_runtime_suspend(xe); 943 if (err) 944 return err; 945 946 pci_save_state(pdev); 947 948 if (xe->d3cold.allowed) { 949 d3cold_toggle(pdev, D3COLD_ENABLE); 950 pci_disable_device(pdev); 951 pci_ignore_hotplug(pdev); 952 pci_set_power_state(pdev, PCI_D3cold); 953 } else { 954 d3cold_toggle(pdev, D3COLD_DISABLE); 955 pci_set_power_state(pdev, PCI_D3hot); 956 } 957 958 return 0; 959 } 960 961 static int xe_pci_runtime_resume(struct device *dev) 962 { 963 struct pci_dev *pdev = to_pci_dev(dev); 964 struct xe_device *xe = pdev_to_xe_device(pdev); 965 int err; 966 967 err = pci_set_power_state(pdev, PCI_D0); 968 if (err) 969 return err; 970 971 pci_restore_state(pdev); 972 973 if (xe->d3cold.allowed) { 974 err = pci_enable_device(pdev); 975 if (err) 976 return err; 977 978 pci_set_master(pdev); 979 } 980 981 return xe_pm_runtime_resume(xe); 982 } 983 984 static int xe_pci_runtime_idle(struct device *dev) 985 { 986 struct pci_dev *pdev = to_pci_dev(dev); 987 struct xe_device *xe = pdev_to_xe_device(pdev); 988 989 xe_pm_d3cold_allowed_toggle(xe); 990 991 return 0; 992 } 993 994 static const struct dev_pm_ops xe_pm_ops = { 995 SET_SYSTEM_SLEEP_PM_OPS(xe_pci_suspend, xe_pci_resume) 996 SET_RUNTIME_PM_OPS(xe_pci_runtime_suspend, xe_pci_runtime_resume, xe_pci_runtime_idle) 997 }; 998 #endif 999 1000 static struct pci_driver xe_pci_driver = { 1001 .name = DRIVER_NAME, 1002 .id_table = pciidlist, 1003 .probe = xe_pci_probe, 1004 .remove = xe_pci_remove, 1005 .shutdown = xe_pci_shutdown, 1006 #ifdef CONFIG_PCI_IOV 1007 .sriov_configure = xe_pci_sriov_configure, 1008 #endif 1009 #ifdef CONFIG_PM_SLEEP 1010 .driver.pm = &xe_pm_ops, 1011 #endif 1012 }; 1013 1014 int xe_register_pci_driver(void) 1015 { 1016 return pci_register_driver(&xe_pci_driver); 1017 } 1018 1019 void xe_unregister_pci_driver(void) 1020 { 1021 pci_unregister_driver(&xe_pci_driver); 1022 } 1023 1024 #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST) 1025 #include "tests/xe_pci.c" 1026 #endif 1027