1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 #include "xe_pci.h" 7 8 #include <kunit/static_stub.h> 9 #include <linux/device/driver.h> 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/pm_runtime.h> 13 14 #include <drm/drm_color_mgmt.h> 15 #include <drm/drm_drv.h> 16 #include <drm/intel/pciids.h> 17 18 #include "display/xe_display.h" 19 #include "regs/xe_gt_regs.h" 20 #include "regs/xe_regs.h" 21 #include "xe_configfs.h" 22 #include "xe_device.h" 23 #include "xe_drv.h" 24 #include "xe_gt.h" 25 #include "xe_gt_sriov_vf.h" 26 #include "xe_guc.h" 27 #include "xe_mmio.h" 28 #include "xe_module.h" 29 #include "xe_pci_error.h" 30 #include "xe_pci_rebar.h" 31 #include "xe_pci_sriov.h" 32 #include "xe_pci_types.h" 33 #include "xe_pm.h" 34 #include "xe_printk.h" 35 #include "xe_sriov.h" 36 #include "xe_step.h" 37 #include "xe_survivability_mode.h" 38 #include "xe_tile.h" 39 40 enum toggle_d3cold { 41 D3COLD_DISABLE, 42 D3COLD_ENABLE, 43 }; 44 45 __diag_push(); 46 __diag_ignore_all("-Woverride-init", "Allow field overrides in table"); 47 48 #define PLATFORM(x) \ 49 .platform = XE_##x, \ 50 .platform_name = #x 51 52 #define NOP(x) x 53 54 static const struct xe_graphics_desc graphics_xelp = { 55 .hw_engine_mask = BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0), 56 .num_geometry_xecore_fuse_regs = 1, 57 }; 58 59 #define XE_HP_FEATURES \ 60 .has_range_tlb_inval = true 61 62 static const struct xe_graphics_desc graphics_xehpg = { 63 .hw_engine_mask = 64 BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) | 65 BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) | 66 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3), 67 .num_geometry_xecore_fuse_regs = 1, 68 .num_compute_xecore_fuse_regs = 1, 69 70 XE_HP_FEATURES, 71 }; 72 73 static const struct xe_graphics_desc graphics_xehpc = { 74 .hw_engine_mask = 75 BIT(XE_HW_ENGINE_BCS0) | BIT(XE_HW_ENGINE_BCS1) | 76 BIT(XE_HW_ENGINE_BCS2) | BIT(XE_HW_ENGINE_BCS3) | 77 BIT(XE_HW_ENGINE_BCS4) | BIT(XE_HW_ENGINE_BCS5) | 78 BIT(XE_HW_ENGINE_BCS6) | BIT(XE_HW_ENGINE_BCS7) | 79 BIT(XE_HW_ENGINE_BCS8) | 80 BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) | 81 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3), 82 83 XE_HP_FEATURES, 84 85 .has_access_counter = 1, 86 .has_asid = 1, 87 .has_atomic_enable_pte_bit = 1, 88 .has_usm = 1, 89 .num_compute_xecore_fuse_regs = 2, 90 }; 91 92 static const struct xe_graphics_desc graphics_xelpg = { 93 .hw_engine_mask = 94 BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) | 95 BIT(XE_HW_ENGINE_CCS0), 96 .num_geometry_xecore_fuse_regs = 1, 97 .num_compute_xecore_fuse_regs = 1, 98 99 XE_HP_FEATURES, 100 }; 101 102 #define XE2_GFX_FEATURES \ 103 .has_access_counter = 1, \ 104 .has_asid = 1, \ 105 .has_atomic_enable_pte_bit = 1, \ 106 .has_range_tlb_inval = 1, \ 107 .has_usm = 1, \ 108 .has_64bit_timestamp = 1, \ 109 .hw_engine_mask = \ 110 BIT(XE_HW_ENGINE_RCS0) | \ 111 BIT(XE_HW_ENGINE_BCS8) | BIT(XE_HW_ENGINE_BCS0) | \ 112 GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0) 113 114 static const struct xe_graphics_desc graphics_xe2 = { 115 XE2_GFX_FEATURES, 116 .num_geometry_xecore_fuse_regs = 3, 117 .num_compute_xecore_fuse_regs = 3, 118 }; 119 120 static const struct xe_graphics_desc graphics_xe3p_lpg = { 121 XE2_GFX_FEATURES, 122 .has_indirect_ring_state = 1, 123 .multi_queue_engine_class_mask = BIT(XE_ENGINE_CLASS_COPY) | BIT(XE_ENGINE_CLASS_COMPUTE), 124 .num_geometry_xecore_fuse_regs = 3, 125 .num_compute_xecore_fuse_regs = 3, 126 }; 127 128 static const struct xe_graphics_desc graphics_xe3p_xpc = { 129 XE2_GFX_FEATURES, 130 .has_access_counter = 0, 131 .has_indirect_ring_state = 1, 132 .hw_engine_mask = 133 GENMASK(XE_HW_ENGINE_BCS8, XE_HW_ENGINE_BCS1) | 134 GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0), 135 .multi_queue_engine_class_mask = BIT(XE_ENGINE_CLASS_COPY) | 136 BIT(XE_ENGINE_CLASS_COMPUTE), 137 .num_geometry_xecore_fuse_regs = 4, 138 .num_compute_xecore_fuse_regs = 4, 139 }; 140 141 static const struct xe_media_desc media_xem = { 142 .hw_engine_mask = 143 GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) | 144 GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0), 145 }; 146 147 static const struct xe_media_desc media_xelpmp = { 148 .hw_engine_mask = 149 GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) | 150 GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0) | 151 BIT(XE_HW_ENGINE_GSCCS0) 152 }; 153 154 /* Pre-GMDID Graphics IPs */ 155 static const struct xe_ip graphics_ip_xelp = { 1200, "Xe_LP", &graphics_xelp }; 156 static const struct xe_ip graphics_ip_xelpp = { 1210, "Xe_LP+", &graphics_xelp }; 157 static const struct xe_ip graphics_ip_xehpg = { 1255, "Xe_HPG", &graphics_xehpg }; 158 static const struct xe_ip graphics_ip_xehpc = { 1260, "Xe_HPC", &graphics_xehpc }; 159 160 /* GMDID-based Graphics IPs */ 161 static const struct xe_ip graphics_ips[] = { 162 { 1270, "Xe_LPG", &graphics_xelpg }, 163 { 1271, "Xe_LPG", &graphics_xelpg }, 164 { 1274, "Xe_LPG+", &graphics_xelpg }, 165 { 2001, "Xe2_HPG", &graphics_xe2 }, 166 { 2002, "Xe2_HPG", &graphics_xe2 }, 167 { 2004, "Xe2_LPG", &graphics_xe2 }, 168 { 3000, "Xe3_LPG", &graphics_xe2 }, 169 { 3001, "Xe3_LPG", &graphics_xe2 }, 170 { 3003, "Xe3_LPG", &graphics_xe2 }, 171 { 3004, "Xe3_LPG", &graphics_xe2 }, 172 { 3005, "Xe3_LPG", &graphics_xe2 }, 173 { 3510, "Xe3p_LPG", &graphics_xe3p_lpg }, 174 { 3511, "Xe3p_XPC", &graphics_xe3p_xpc }, 175 }; 176 177 /* Pre-GMDID Media IPs */ 178 static const struct xe_ip media_ip_xem = { 1200, "Xe_M", &media_xem }; 179 static const struct xe_ip media_ip_xehpm = { 1255, "Xe_HPM", &media_xem }; 180 181 /* GMDID-based Media IPs */ 182 static const struct xe_ip media_ips[] = { 183 { 1300, "Xe_LPM+", &media_xelpmp }, 184 { 1301, "Xe2_HPM", &media_xelpmp }, 185 { 2000, "Xe2_LPM", &media_xelpmp }, 186 { 3000, "Xe3_LPM", &media_xelpmp }, 187 { 3002, "Xe3_LPM", &media_xelpmp }, 188 { 3500, "Xe3p_LPM", &media_xelpmp }, 189 { 3503, "Xe3p_HPM", &media_xelpmp }, 190 }; 191 192 #define MULTI_LRC_MASK \ 193 .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE) | \ 194 BIT(XE_ENGINE_CLASS_VIDEO_ENHANCE) 195 196 static const struct xe_device_desc tgl_desc = { 197 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 198 .pre_gmdid_media_ip = &media_ip_xem, 199 PLATFORM(TIGERLAKE), 200 .dma_mask_size = 39, 201 .has_cached_pt = true, 202 .has_display = true, 203 .has_llc = true, 204 .has_sriov = true, 205 .max_gt_per_tile = 1, 206 MULTI_LRC_MASK, 207 .require_force_probe = true, 208 .va_bits = 48, 209 .vm_max_level = 3, 210 }; 211 212 static const struct xe_device_desc rkl_desc = { 213 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 214 .pre_gmdid_media_ip = &media_ip_xem, 215 PLATFORM(ROCKETLAKE), 216 .dma_mask_size = 39, 217 .has_cached_pt = true, 218 .has_display = true, 219 .has_llc = true, 220 .max_gt_per_tile = 1, 221 MULTI_LRC_MASK, 222 .require_force_probe = true, 223 .va_bits = 48, 224 .vm_max_level = 3, 225 }; 226 227 static const u16 adls_rpls_ids[] = { INTEL_RPLS_IDS(NOP), 0 }; 228 229 static const struct xe_device_desc adl_s_desc = { 230 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 231 .pre_gmdid_media_ip = &media_ip_xem, 232 PLATFORM(ALDERLAKE_S), 233 .dma_mask_size = 39, 234 .has_cached_pt = true, 235 .has_display = true, 236 .has_llc = true, 237 .has_sriov = true, 238 .max_gt_per_tile = 1, 239 MULTI_LRC_MASK, 240 .require_force_probe = true, 241 .subplatforms = (const struct xe_subplatform_desc[]) { 242 { XE_SUBPLATFORM_ALDERLAKE_S_RPLS, "RPLS", adls_rpls_ids }, 243 {}, 244 }, 245 .va_bits = 48, 246 .vm_max_level = 3, 247 }; 248 249 static const u16 adlp_rplu_ids[] = { INTEL_RPLU_IDS(NOP), 0 }; 250 251 static const struct xe_device_desc adl_p_desc = { 252 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 253 .pre_gmdid_media_ip = &media_ip_xem, 254 PLATFORM(ALDERLAKE_P), 255 .dma_mask_size = 39, 256 .has_cached_pt = true, 257 .has_display = true, 258 .has_llc = true, 259 .has_sriov = true, 260 .max_gt_per_tile = 1, 261 MULTI_LRC_MASK, 262 .require_force_probe = true, 263 .subplatforms = (const struct xe_subplatform_desc[]) { 264 { XE_SUBPLATFORM_ALDERLAKE_P_RPLU, "RPLU", adlp_rplu_ids }, 265 {}, 266 }, 267 .va_bits = 48, 268 .vm_max_level = 3, 269 }; 270 271 static const struct xe_device_desc adl_n_desc = { 272 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 273 .pre_gmdid_media_ip = &media_ip_xem, 274 PLATFORM(ALDERLAKE_N), 275 .dma_mask_size = 39, 276 .has_cached_pt = true, 277 .has_display = true, 278 .has_llc = true, 279 .has_sriov = true, 280 .max_gt_per_tile = 1, 281 MULTI_LRC_MASK, 282 .require_force_probe = true, 283 .va_bits = 48, 284 .vm_max_level = 3, 285 }; 286 287 #define DGFX_FEATURES \ 288 .is_dgfx = 1 289 290 static const struct xe_device_desc dg1_desc = { 291 .pre_gmdid_graphics_ip = &graphics_ip_xelpp, 292 .pre_gmdid_media_ip = &media_ip_xem, 293 DGFX_FEATURES, 294 PLATFORM(DG1), 295 .dma_mask_size = 39, 296 .has_display = true, 297 .has_gsc_nvm = 1, 298 .has_heci_gscfi = 1, 299 .max_gt_per_tile = 1, 300 MULTI_LRC_MASK, 301 .require_force_probe = true, 302 .va_bits = 48, 303 .vm_max_level = 3, 304 }; 305 306 static const u16 dg2_g10_ids[] = { INTEL_DG2_G10_IDS(NOP), INTEL_ATS_M150_IDS(NOP), 0 }; 307 static const u16 dg2_g11_ids[] = { INTEL_DG2_G11_IDS(NOP), INTEL_ATS_M75_IDS(NOP), 0 }; 308 static const u16 dg2_g12_ids[] = { INTEL_DG2_G12_IDS(NOP), 0 }; 309 310 #define DG2_FEATURES \ 311 DGFX_FEATURES, \ 312 PLATFORM(DG2), \ 313 .has_flat_ccs = 1, \ 314 .has_gsc_nvm = 1, \ 315 .has_heci_gscfi = 1, \ 316 .subplatforms = (const struct xe_subplatform_desc[]) { \ 317 { XE_SUBPLATFORM_DG2_G10, "G10", dg2_g10_ids }, \ 318 { XE_SUBPLATFORM_DG2_G11, "G11", dg2_g11_ids }, \ 319 { XE_SUBPLATFORM_DG2_G12, "G12", dg2_g12_ids }, \ 320 { } \ 321 }, \ 322 .va_bits = 48, \ 323 .vm_max_level = 3, \ 324 .vram_flags = XE_VRAM_FLAGS_NEED64K 325 326 static const struct xe_device_desc ats_m_desc = { 327 .pre_gmdid_graphics_ip = &graphics_ip_xehpg, 328 .pre_gmdid_media_ip = &media_ip_xehpm, 329 .dma_mask_size = 46, 330 .max_gt_per_tile = 1, 331 MULTI_LRC_MASK, 332 .require_force_probe = true, 333 334 DG2_FEATURES, 335 .has_display = false, 336 .has_sriov = true, 337 }; 338 339 static const struct xe_device_desc dg2_desc = { 340 .pre_gmdid_graphics_ip = &graphics_ip_xehpg, 341 .pre_gmdid_media_ip = &media_ip_xehpm, 342 .dma_mask_size = 46, 343 .max_gt_per_tile = 1, 344 MULTI_LRC_MASK, 345 .require_force_probe = true, 346 347 DG2_FEATURES, 348 .has_display = true, 349 .has_fan_control = true, 350 .has_mbx_power_limits = false, 351 }; 352 353 static const __maybe_unused struct xe_device_desc pvc_desc = { 354 .pre_gmdid_graphics_ip = &graphics_ip_xehpc, 355 DGFX_FEATURES, 356 PLATFORM(PVC), 357 .dma_mask_size = 52, 358 .has_display = false, 359 .has_drm_ras = true, 360 .has_gsc_nvm = 1, 361 .has_heci_gscfi = 1, 362 .max_gt_per_tile = 1, 363 .max_remote_tiles = 1, 364 MULTI_LRC_MASK, 365 .require_force_probe = true, 366 .va_bits = 57, 367 .vm_max_level = 4, 368 .vram_flags = XE_VRAM_FLAGS_NEED64K, 369 .has_mbx_power_limits = false, 370 }; 371 372 static const struct xe_device_desc mtl_desc = { 373 /* .graphics and .media determined via GMD_ID */ 374 .require_force_probe = true, 375 PLATFORM(METEORLAKE), 376 .dma_mask_size = 46, 377 .has_display = true, 378 .has_pxp = true, 379 .max_gt_per_tile = 2, 380 MULTI_LRC_MASK, 381 .va_bits = 48, 382 .vm_max_level = 3, 383 }; 384 385 static const struct xe_device_desc lnl_desc = { 386 PLATFORM(LUNARLAKE), 387 .dma_mask_size = 46, 388 .has_display = true, 389 .has_flat_ccs = 1, 390 .has_pxp = true, 391 .max_gt_per_tile = 2, 392 MULTI_LRC_MASK, 393 .needs_scratch = true, 394 .va_bits = 48, 395 .vm_max_level = 4, 396 }; 397 398 static const u16 bmg_g21_ids[] = { INTEL_BMG_G21_IDS(NOP), 0 }; 399 400 static const struct xe_device_desc bmg_desc = { 401 DGFX_FEATURES, 402 PLATFORM(BATTLEMAGE), 403 .dma_mask_size = 46, 404 .has_display = true, 405 .has_fan_control = true, 406 .has_flat_ccs = 1, 407 .has_mbx_power_limits = true, 408 .has_mbx_thermal_info = true, 409 .has_gsc_nvm = 1, 410 .has_heci_cscfi = 1, 411 .has_i2c = true, 412 .has_late_bind = true, 413 .has_pre_prod_wa = 1, 414 .has_soc_remapper_telem = true, 415 .has_sriov = true, 416 .max_gt_per_tile = 2, 417 MULTI_LRC_MASK, 418 .needs_scratch = true, 419 .subplatforms = (const struct xe_subplatform_desc[]) { 420 { XE_SUBPLATFORM_BATTLEMAGE_G21, "G21", bmg_g21_ids }, 421 { } 422 }, 423 .va_bits = 48, 424 .vm_max_level = 4, 425 }; 426 427 static const struct xe_device_desc ptl_desc = { 428 PLATFORM(PANTHERLAKE), 429 .dma_mask_size = 46, 430 .has_display = true, 431 .has_flat_ccs = 1, 432 .has_sriov = true, 433 .has_pre_prod_wa = 1, 434 .has_pxp = true, 435 .max_gt_per_tile = 2, 436 MULTI_LRC_MASK, 437 .needs_scratch = true, 438 .needs_shared_vf_gt_wq = true, 439 .va_bits = 48, 440 .vm_max_level = 4, 441 }; 442 443 static const struct xe_device_desc nvls_desc = { 444 PLATFORM(NOVALAKE_S), 445 .dma_mask_size = 46, 446 .has_display = true, 447 .has_flat_ccs = 1, 448 .has_pre_prod_wa = 1, 449 .has_sriov = true, 450 .max_gt_per_tile = 2, 451 MULTI_LRC_MASK, 452 .require_force_probe = true, 453 .va_bits = 48, 454 .vm_max_level = 4, 455 }; 456 457 static const struct xe_device_desc cri_desc = { 458 DGFX_FEATURES, 459 PLATFORM(CRESCENTISLAND), 460 .dma_mask_size = 52, 461 .has_display = false, 462 .has_drm_ras = true, 463 .has_flat_ccs = false, 464 .has_gsc_nvm = 1, 465 .has_i2c = true, 466 .has_mbx_power_limits = true, 467 .has_mbx_thermal_info = true, 468 .has_mert = true, 469 .has_pre_prod_wa = 1, 470 .has_soc_remapper_sysctrl = true, 471 .has_soc_remapper_telem = true, 472 .has_sriov = true, 473 .has_sysctrl = true, 474 .max_gt_per_tile = 2, 475 MULTI_LRC_MASK, 476 .require_force_probe = true, 477 .va_bits = 57, 478 .vm_max_level = 4, 479 }; 480 481 static const struct xe_device_desc nvlp_desc = { 482 PLATFORM(NOVALAKE_P), 483 .dma_mask_size = 46, 484 .has_cached_pt = true, 485 .has_display = true, 486 .has_flat_ccs = 1, 487 .has_page_reclaim_hw_assist = true, 488 .has_pre_prod_wa = true, 489 .has_sriov = true, 490 .max_gt_per_tile = 2, 491 MULTI_LRC_MASK, 492 .require_force_probe = true, 493 .va_bits = 48, 494 .vm_max_level = 4, 495 }; 496 497 #undef PLATFORM 498 __diag_pop(); 499 500 /* 501 * Make sure any device matches here are from most specific to most 502 * general. For example, since the Quanta match is based on the subsystem 503 * and subvendor IDs, we need it to come before the more general IVB 504 * PCI ID matches, otherwise we'll use the wrong info struct above. 505 */ 506 static const struct pci_device_id pciidlist[] = { 507 INTEL_TGL_IDS(INTEL_VGA_DEVICE, &tgl_desc), 508 INTEL_RKL_IDS(INTEL_VGA_DEVICE, &rkl_desc), 509 INTEL_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc), 510 INTEL_ADLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 511 INTEL_ADLN_IDS(INTEL_VGA_DEVICE, &adl_n_desc), 512 INTEL_RPLU_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 513 INTEL_RPLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 514 INTEL_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc), 515 INTEL_DG1_IDS(INTEL_VGA_DEVICE, &dg1_desc), 516 INTEL_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_desc), 517 INTEL_ARL_IDS(INTEL_VGA_DEVICE, &mtl_desc), 518 INTEL_DG2_IDS(INTEL_VGA_DEVICE, &dg2_desc), 519 INTEL_MTL_IDS(INTEL_VGA_DEVICE, &mtl_desc), 520 INTEL_LNL_IDS(INTEL_VGA_DEVICE, &lnl_desc), 521 INTEL_BMG_IDS(INTEL_VGA_DEVICE, &bmg_desc), 522 INTEL_PTL_IDS(INTEL_VGA_DEVICE, &ptl_desc), 523 INTEL_WCL_IDS(INTEL_VGA_DEVICE, &ptl_desc), 524 INTEL_NVLS_IDS(INTEL_VGA_DEVICE, &nvls_desc), 525 INTEL_CRI_IDS(INTEL_PCI_DEVICE, &cri_desc), 526 INTEL_NVLP_IDS(INTEL_VGA_DEVICE, &nvlp_desc), 527 { } 528 }; 529 MODULE_DEVICE_TABLE(pci, pciidlist); 530 531 /* is device_id present in comma separated list of ids */ 532 static bool device_id_in_list(u16 device_id, const char *devices, bool negative) 533 { 534 char *s, *p, *tok; 535 bool ret; 536 537 if (!devices || !*devices) 538 return false; 539 540 /* match everything */ 541 if (negative && strcmp(devices, "!*") == 0) 542 return true; 543 if (!negative && strcmp(devices, "*") == 0) 544 return true; 545 546 s = kstrdup(devices, GFP_KERNEL); 547 if (!s) 548 return false; 549 550 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) { 551 u16 val; 552 553 if (negative && tok[0] == '!') 554 tok++; 555 else if ((negative && tok[0] != '!') || 556 (!negative && tok[0] == '!')) 557 continue; 558 559 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) { 560 ret = true; 561 break; 562 } 563 } 564 565 kfree(s); 566 567 return ret; 568 } 569 570 static bool id_forced(u16 device_id) 571 { 572 return device_id_in_list(device_id, xe_modparam.force_probe, false); 573 } 574 575 static bool id_blocked(u16 device_id) 576 { 577 return device_id_in_list(device_id, xe_modparam.force_probe, true); 578 } 579 580 static const struct xe_subplatform_desc * 581 find_subplatform(const struct xe_device_desc *desc, u16 devid) 582 { 583 const struct xe_subplatform_desc *sp; 584 const u16 *id; 585 586 for (sp = desc->subplatforms; sp && sp->subplatform; sp++) 587 for (id = sp->pciidlist; *id; id++) 588 if (*id == devid) 589 return sp; 590 591 return NULL; 592 } 593 594 enum xe_gmdid_type { 595 GMDID_GRAPHICS, 596 GMDID_MEDIA 597 }; 598 599 static int read_gmdid(struct xe_device *xe, enum xe_gmdid_type type, u32 *ver, u32 *revid) 600 { 601 struct xe_mmio *mmio = xe_root_tile_mmio(xe); 602 struct xe_reg gmdid_reg = GMD_ID; 603 u32 val; 604 605 if (IS_SRIOV_VF(xe)) { 606 /* 607 * To get the value of the GMDID register, VFs must obtain it 608 * from the GuC using MMIO communication. 609 * 610 * Note that at this point the GTs are not initialized and only 611 * tile-level access to MMIO registers is possible. To use our 612 * existing GuC communication functions we must create a dummy 613 * GT structure and perform at least basic xe_gt and xe_guc 614 * initialization. 615 */ 616 struct xe_gt *gt __free(kfree) = NULL; 617 int err; 618 619 /* Don't try to read media ver if media GT is not allowed */ 620 if (type == GMDID_MEDIA && !xe_configfs_media_gt_allowed(to_pci_dev(xe->drm.dev))) { 621 *ver = *revid = 0; 622 return 0; 623 } 624 625 gt = kzalloc(sizeof(*gt), GFP_KERNEL); 626 if (!gt) 627 return -ENOMEM; 628 629 gt->tile = &xe->tiles[0]; 630 if (type == GMDID_MEDIA) { 631 gt->info.id = 1; 632 gt->info.type = XE_GT_TYPE_MEDIA; 633 } else { 634 gt->info.id = 0; 635 gt->info.type = XE_GT_TYPE_MAIN; 636 } 637 638 xe_gt_mmio_init(gt); 639 xe_guc_comm_init_early(>->uc.guc); 640 641 err = xe_gt_sriov_vf_bootstrap(gt); 642 if (err) 643 return err; 644 645 val = xe_gt_sriov_vf_gmdid(gt); 646 } else { 647 /* 648 * GMD_ID is a GT register, but at this point in the driver 649 * init we haven't fully initialized the GT yet so we need to 650 * read the register with the tile's MMIO accessor. That means 651 * we need to apply the GSI offset manually since it won't get 652 * automatically added as it would if we were using a GT mmio 653 * accessor. 654 */ 655 if (type == GMDID_MEDIA) 656 gmdid_reg.addr += MEDIA_GT_GSI_OFFSET; 657 658 val = xe_mmio_read32(mmio, gmdid_reg); 659 } 660 661 *ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val) * 100 + REG_FIELD_GET(GMD_ID_RELEASE_MASK, val); 662 *revid = REG_FIELD_GET(GMD_ID_REVID, val); 663 664 return 0; 665 } 666 667 static const struct xe_ip *find_graphics_ip(unsigned int verx100) 668 { 669 KUNIT_STATIC_STUB_REDIRECT(find_graphics_ip, verx100); 670 671 for (int i = 0; i < ARRAY_SIZE(graphics_ips); i++) 672 if (graphics_ips[i].verx100 == verx100) 673 return &graphics_ips[i]; 674 return NULL; 675 } 676 677 static const struct xe_ip *find_media_ip(unsigned int verx100) 678 { 679 KUNIT_STATIC_STUB_REDIRECT(find_media_ip, verx100); 680 681 for (int i = 0; i < ARRAY_SIZE(media_ips); i++) 682 if (media_ips[i].verx100 == verx100) 683 return &media_ips[i]; 684 return NULL; 685 } 686 687 /* 688 * Read IP version from hardware and select graphics/media IP descriptors 689 * based on the result. 690 */ 691 static int handle_gmdid(struct xe_device *xe, 692 const struct xe_ip **graphics_ip, 693 const struct xe_ip **media_ip, 694 u32 *graphics_revid, 695 u32 *media_revid) 696 { 697 u32 ver; 698 int ret; 699 700 *graphics_ip = NULL; 701 *media_ip = NULL; 702 703 ret = read_gmdid(xe, GMDID_GRAPHICS, &ver, graphics_revid); 704 if (ret) 705 return ret; 706 707 *graphics_ip = find_graphics_ip(ver); 708 if (!*graphics_ip) { 709 drm_err(&xe->drm, "Hardware reports unknown graphics version %u.%02u\n", 710 ver / 100, ver % 100); 711 } 712 713 ret = read_gmdid(xe, GMDID_MEDIA, &ver, media_revid); 714 if (ret) 715 return ret; 716 717 /* Media may legitimately be fused off / not present */ 718 if (ver == 0) 719 return 0; 720 721 *media_ip = find_media_ip(ver); 722 if (!*media_ip) { 723 drm_err(&xe->drm, "Hardware reports unknown media version %u.%02u\n", 724 ver / 100, ver % 100); 725 } 726 727 return 0; 728 } 729 730 struct xe_probed_info { 731 u16 devid; 732 u8 revid; 733 u8 tile_count; 734 struct xe_step_info step; 735 const struct xe_ip *graphics_ip; 736 const struct xe_ip *media_ip; 737 }; 738 739 /* 740 * Probe from the hardware the info required by xe_info_init_early(). 741 */ 742 static int xe_probe_info_early(struct xe_device *xe, 743 const struct xe_device_desc *desc, 744 struct xe_probed_info *probed_info) 745 { 746 struct pci_dev *pdev = to_pci_dev(xe->drm.dev); 747 748 probed_info->devid = pdev->device; 749 probed_info->revid = pdev->revision; 750 751 xe_step_platform_get(desc->platform, probed_info->revid, &probed_info->step); 752 753 return 0; 754 } 755 756 /* 757 * Initialize device info content that only depends on static driver_data 758 * passed to the driver at probe time from PCI ID table. 759 */ 760 static int xe_info_init_early(struct xe_device *xe, 761 const struct xe_device_desc *desc, 762 const struct xe_subplatform_desc *subplatform_desc, 763 struct xe_probed_info *probed_info) 764 { 765 int err; 766 767 xe->info.devid = probed_info->devid; 768 xe->info.revid = probed_info->revid; 769 xe->info.step.platform = probed_info->step.platform; 770 771 xe->info.platform_name = desc->platform_name; 772 xe->info.platform = desc->platform; 773 xe->info.subplatform = subplatform_desc ? 774 subplatform_desc->subplatform : XE_SUBPLATFORM_NONE; 775 776 xe->info.dma_mask_size = desc->dma_mask_size; 777 xe->info.va_bits = desc->va_bits; 778 xe->info.vm_max_level = desc->vm_max_level; 779 xe->info.vram_flags = desc->vram_flags; 780 781 xe->info.is_dgfx = desc->is_dgfx; 782 xe->info.has_cached_pt = desc->has_cached_pt; 783 xe->info.has_drm_ras = desc->has_drm_ras; 784 xe->info.has_fan_control = desc->has_fan_control; 785 /* runtime fusing may force flat_ccs to disabled later */ 786 xe->info.has_flat_ccs = desc->has_flat_ccs; 787 xe->info.has_mbx_power_limits = desc->has_mbx_power_limits; 788 xe->info.has_mbx_thermal_info = desc->has_mbx_thermal_info; 789 xe->info.has_gsc_nvm = desc->has_gsc_nvm; 790 xe->info.has_heci_gscfi = desc->has_heci_gscfi; 791 xe->info.has_heci_cscfi = desc->has_heci_cscfi; 792 xe->info.has_i2c = desc->has_i2c; 793 xe->info.has_late_bind = desc->has_late_bind; 794 xe->info.has_llc = desc->has_llc; 795 xe->info.has_mert = desc->has_mert; 796 xe->info.has_page_reclaim_hw_assist = desc->has_page_reclaim_hw_assist; 797 xe->info.has_pre_prod_wa = desc->has_pre_prod_wa; 798 xe->info.has_pxp = desc->has_pxp; 799 xe->info.has_soc_remapper_sysctrl = desc->has_soc_remapper_sysctrl; 800 xe->info.has_soc_remapper_telem = desc->has_soc_remapper_telem; 801 xe->info.has_sriov = xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev)) && 802 desc->has_sriov; 803 xe->info.has_sysctrl = desc->has_sysctrl; 804 xe->info.skip_guc_pc = desc->skip_guc_pc; 805 xe->info.skip_pcode = desc->skip_pcode; 806 xe->info.needs_scratch = desc->needs_scratch; 807 xe->info.needs_shared_vf_gt_wq = desc->needs_shared_vf_gt_wq; 808 xe->info.multi_lrc_mask = desc->multi_lrc_mask; 809 810 xe->info.probe_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) && 811 xe_modparam.probe_display && 812 desc->has_display; 813 814 xe_assert(xe, desc->max_gt_per_tile > 0); 815 xe_assert(xe, desc->max_gt_per_tile <= XE_MAX_GT_PER_TILE); 816 xe->info.max_gt_per_tile = desc->max_gt_per_tile; 817 818 err = xe_tile_init_early(xe_device_get_root_tile(xe), xe, 0); 819 if (err) 820 return err; 821 822 return 0; 823 } 824 825 static void xe_probe_tile_count(struct xe_device *xe, 826 const struct xe_device_desc *desc, 827 struct xe_probed_info *probed_info) 828 { 829 struct xe_mmio *mmio; 830 u8 tile_count; 831 u32 mtcfg; 832 833 probed_info->tile_count = 1 + desc->max_remote_tiles; 834 835 /* 836 * Probe for tile count only for platforms that support multiple 837 * tiles. 838 */ 839 if (probed_info->tile_count == 1) 840 return; 841 842 mmio = xe_root_tile_mmio(xe); 843 844 /* 845 * Although the per-tile mmio regs are not yet initialized, this 846 * is fine as it's going to the root tile's mmio, that's 847 * guaranteed to be initialized earlier in xe_mmio_probe_early() 848 */ 849 mtcfg = xe_mmio_read32(mmio, XEHP_MTCFG_ADDR); 850 tile_count = REG_FIELD_GET(TILE_COUNT, mtcfg) + 1; 851 852 if (tile_count < probed_info->tile_count) { 853 drm_info(&xe->drm, "tile_count: %d, reduced_tile_count %d\n", 854 probed_info->tile_count, tile_count); 855 probed_info->tile_count = tile_count; 856 } 857 } 858 859 static struct xe_gt *alloc_primary_gt(struct xe_tile *tile, 860 const struct xe_graphics_desc *graphics_desc, 861 const struct xe_media_desc *media_desc) 862 { 863 struct xe_device *xe = tile_to_xe(tile); 864 struct xe_gt *gt; 865 866 if (!xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev))) { 867 xe_info(xe, "Primary GT disabled via configfs\n"); 868 return NULL; 869 } 870 871 gt = xe_gt_alloc(tile); 872 if (IS_ERR(gt)) 873 return gt; 874 875 gt->info.type = XE_GT_TYPE_MAIN; 876 gt->info.id = tile->id * xe->info.max_gt_per_tile; 877 gt->info.has_indirect_ring_state = graphics_desc->has_indirect_ring_state; 878 gt->info.multi_queue_engine_class_mask = graphics_desc->multi_queue_engine_class_mask; 879 gt->info.engine_mask = graphics_desc->hw_engine_mask; 880 gt->info.num_geometry_xecore_fuse_regs = graphics_desc->num_geometry_xecore_fuse_regs; 881 gt->info.num_compute_xecore_fuse_regs = graphics_desc->num_compute_xecore_fuse_regs; 882 883 /* 884 * Even if the service copy engines wind up being fused off, their 885 * presence in the IP descriptor indicates that the platform supports 886 * Xe2-style MEM_SET and MEM_COPY functionality. 887 */ 888 if (graphics_desc->hw_engine_mask & GENMASK(XE_HW_ENGINE_BCS8, 889 XE_HW_ENGINE_BCS1)) 890 gt->info.has_xe2_blt_instructions = true; 891 892 /* 893 * Before media version 13, the media IP was part of the primary GT 894 * so we need to add the media engines to the primary GT's engine list. 895 */ 896 if (MEDIA_VER(xe) < 13 && media_desc) 897 gt->info.engine_mask |= media_desc->hw_engine_mask; 898 899 return gt; 900 } 901 902 static struct xe_gt *alloc_media_gt(struct xe_tile *tile, 903 const struct xe_media_desc *media_desc) 904 { 905 struct xe_device *xe = tile_to_xe(tile); 906 struct xe_gt *gt; 907 908 if (!xe_configfs_media_gt_allowed(to_pci_dev(xe->drm.dev))) { 909 xe_info(xe, "Media GT disabled via configfs\n"); 910 return NULL; 911 } 912 913 if (MEDIA_VER(xe) < 13 || !media_desc) 914 return NULL; 915 916 gt = xe_gt_alloc(tile); 917 if (IS_ERR(gt)) 918 return gt; 919 920 gt->info.type = XE_GT_TYPE_MEDIA; 921 gt->info.id = tile->id * xe->info.max_gt_per_tile + 1; 922 gt->info.has_indirect_ring_state = media_desc->has_indirect_ring_state; 923 gt->info.engine_mask = media_desc->hw_engine_mask; 924 925 return gt; 926 } 927 928 static int xe_probe_ips(struct xe_device *xe, 929 const struct xe_device_desc *desc, 930 struct xe_probed_info *probed_info) 931 { 932 /* 933 * If this platform supports GMD_ID, we'll detect the proper IP 934 * descriptor to use from hardware registers. 935 * desc->pre_gmdid_graphics_ip will only ever be set at this point for 936 * platforms before GMD_ID. In that case the IP descriptions and 937 * versions are simply derived from that. 938 */ 939 if (desc->pre_gmdid_graphics_ip) { 940 probed_info->graphics_ip = desc->pre_gmdid_graphics_ip; 941 probed_info->media_ip = desc->pre_gmdid_media_ip; 942 xe_step_pre_gmdid_get(xe, &probed_info->step); 943 } else { 944 int err; 945 u32 graphics_revid, media_revid; 946 947 xe_assert(xe, !desc->pre_gmdid_media_ip); 948 949 err = handle_gmdid(xe, &probed_info->graphics_ip, &probed_info->media_ip, 950 &graphics_revid, &media_revid); 951 if (err) 952 return err; 953 954 xe_step_gmdid_get(xe, graphics_revid, media_revid, &probed_info->step); 955 } 956 957 /* 958 * If we couldn't detect the graphics IP, that's considered a fatal 959 * error and we should abort driver load. Failing to detect media 960 * IP is non-fatal; we'll just proceed without enabling media support. 961 */ 962 if (!probed_info->graphics_ip) 963 return -ENODEV; 964 965 return 0; 966 } 967 968 /* 969 * Probe from the hardware the info required by xe_info_init(). 970 */ 971 static int xe_probe_info(struct xe_device *xe, 972 const struct xe_device_desc *desc, 973 struct xe_probed_info *probed_info) 974 { 975 int err; 976 977 xe_probe_tile_count(xe, desc, probed_info); 978 979 err = xe_probe_ips(xe, desc, probed_info); 980 if (err) 981 return err; 982 983 return 0; 984 } 985 986 /* 987 * Initialize device info content that does require knowledge about 988 * graphics / media IP version. 989 * Make sure that GT / tile structures allocated by the driver match the data 990 * present in device info. 991 */ 992 static int xe_info_init(struct xe_device *xe, 993 const struct xe_device_desc *desc, 994 struct xe_probed_info *probed_info) 995 { 996 const struct xe_ip *graphics_ip; 997 const struct xe_ip *media_ip; 998 const struct xe_graphics_desc *graphics_desc; 999 const struct xe_media_desc *media_desc; 1000 struct xe_tile *tile; 1001 struct xe_gt *gt; 1002 u8 id; 1003 1004 graphics_ip = probed_info->graphics_ip; 1005 media_ip = probed_info->media_ip; 1006 1007 xe->info.tile_count = probed_info->tile_count; 1008 xe->info.step.basedie = probed_info->step.basedie; 1009 xe->info.step.graphics = probed_info->step.graphics; 1010 xe->info.step.media = probed_info->step.media; 1011 1012 xe->info.graphics_verx100 = graphics_ip->verx100; 1013 xe->info.graphics_name = graphics_ip->name; 1014 graphics_desc = graphics_ip->desc; 1015 1016 if (media_ip) { 1017 xe->info.media_verx100 = media_ip->verx100; 1018 xe->info.media_name = media_ip->name; 1019 media_desc = media_ip->desc; 1020 } else { 1021 xe->info.media_name = "none"; 1022 media_desc = NULL; 1023 } 1024 1025 xe->info.has_access_counter = graphics_desc->has_access_counter; 1026 xe->info.has_asid = graphics_desc->has_asid; 1027 xe->info.has_atomic_enable_pte_bit = graphics_desc->has_atomic_enable_pte_bit; 1028 if (xe->info.platform != XE_PVC) 1029 xe->info.has_device_atomics_on_smem = 1; 1030 1031 xe->info.has_range_tlb_inval = graphics_desc->has_range_tlb_inval; 1032 xe->info.has_ctx_tlb_inval = graphics_desc->has_ctx_tlb_inval; 1033 xe->info.has_usm = graphics_desc->has_usm; 1034 xe->info.has_64bit_timestamp = graphics_desc->has_64bit_timestamp; 1035 xe->info.has_mem_copy_instr = GRAPHICS_VER(xe) >= 20; 1036 1037 if (IS_SRIOV_VF(xe)) { 1038 xe->info.has_sysctrl = 0; 1039 xe->info.has_soc_remapper_sysctrl = 0; 1040 xe->info.has_soc_remapper_telem = 0; 1041 } 1042 1043 for_each_remote_tile(tile, xe, id) { 1044 int err; 1045 1046 err = xe_tile_init_early(tile, xe, id); 1047 if (err) 1048 return err; 1049 } 1050 1051 /* Allocate any GT and VRAM structures necessary for the platform. */ 1052 for_each_tile(tile, xe, id) { 1053 int err; 1054 1055 err = xe_tile_alloc_vram(tile); 1056 if (err) 1057 return err; 1058 1059 tile->primary_gt = alloc_primary_gt(tile, graphics_desc, media_desc); 1060 if (IS_ERR(tile->primary_gt)) 1061 return PTR_ERR(tile->primary_gt); 1062 1063 /* 1064 * It's not currently possible to probe a device with the 1065 * primary GT disabled. With some work, this may be future in 1066 * the possible for igpu platforms (although probably not for 1067 * dgpu's since access to the primary GT's BCS engines is 1068 * required for VRAM management). 1069 */ 1070 if (!tile->primary_gt) { 1071 drm_err(&xe->drm, "Cannot probe device with without a primary GT\n"); 1072 return -ENODEV; 1073 } 1074 1075 tile->media_gt = alloc_media_gt(tile, media_desc); 1076 if (IS_ERR(tile->media_gt)) 1077 return PTR_ERR(tile->media_gt); 1078 } 1079 1080 /* 1081 * Now that we have tiles and GTs defined, let's loop over valid GTs 1082 * in order to define gt_count. 1083 */ 1084 for_each_gt(gt, xe, id) 1085 xe->info.gt_count++; 1086 1087 return 0; 1088 } 1089 1090 static void xe_pci_remove(struct pci_dev *pdev) 1091 { 1092 struct xe_device *xe = pdev_to_xe_device(pdev); 1093 1094 if (IS_SRIOV_PF(xe)) 1095 xe_pci_sriov_configure(pdev, 0); 1096 1097 if (xe_survivability_mode_is_boot_enabled(xe)) 1098 return; 1099 1100 xe_device_remove(xe); 1101 xe_pm_fini(xe); 1102 } 1103 1104 /* 1105 * Probe the PCI device, initialize various parts of the driver. 1106 * 1107 * Fault injection is used to test the error paths of some initialization 1108 * functions called either directly from xe_pci_probe() or indirectly for 1109 * example through xe_device_probe(). Those functions use the kernel fault 1110 * injection capabilities infrastructure, see 1111 * Documentation/fault-injection/fault-injection.rst for details. The macro 1112 * ALLOW_ERROR_INJECTION() is used to conditionally skip function execution 1113 * at runtime and use a provided return value. The first requirement for 1114 * error injectable functions is proper handling of the error code by the 1115 * caller for recovery, which is always the case here. The second 1116 * requirement is that no state is changed before the first error return. 1117 * It is not strictly fulfilled for all initialization functions using the 1118 * ALLOW_ERROR_INJECTION() macro but this is acceptable because for those 1119 * error cases at probe time, the error code is simply propagated up by the 1120 * caller. Therefore there is no consequence on those specific callers when 1121 * function error injection skips the whole function. 1122 */ 1123 static int xe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1124 { 1125 struct xe_probed_info probed_info = {}; 1126 const struct xe_device_desc *desc = (const void *)ent->driver_data; 1127 const struct xe_subplatform_desc *subplatform_desc; 1128 struct xe_device *xe; 1129 void *group; 1130 int err; 1131 1132 subplatform_desc = find_subplatform(desc, pdev->device); 1133 1134 xe_configfs_check_device(pdev); 1135 1136 if (desc->require_force_probe && !id_forced(pdev->device)) { 1137 dev_info(&pdev->dev, 1138 "Your graphics device %04x is not officially supported\n" 1139 "by xe driver in this kernel version. To force Xe probe,\n" 1140 "use xe.force_probe='%04x' and i915.force_probe='!%04x'\n" 1141 "module parameters or CONFIG_DRM_XE_FORCE_PROBE='%04x' and\n" 1142 "CONFIG_DRM_I915_FORCE_PROBE='!%04x' configuration options.\n", 1143 pdev->device, pdev->device, pdev->device, 1144 pdev->device, pdev->device); 1145 return -ENODEV; 1146 } 1147 1148 if (id_blocked(pdev->device)) { 1149 dev_info(&pdev->dev, "Probe blocked for device [%04x:%04x].\n", 1150 pdev->vendor, pdev->device); 1151 return -ENODEV; 1152 } 1153 1154 if (xe_display_driver_probe_defer(pdev)) 1155 return -EPROBE_DEFER; 1156 1157 /* Group all devres so xe_pci_error_slot_reset() can release them as a unit. */ 1158 group = devres_open_group(&pdev->dev, NULL, GFP_KERNEL); 1159 if (!group) 1160 return -ENOMEM; 1161 1162 err = pcim_enable_device(pdev); 1163 if (err) 1164 return err; 1165 1166 xe = xe_device_create(pdev); 1167 if (IS_ERR(xe)) 1168 return PTR_ERR(xe); 1169 1170 xe->devres_group = group; 1171 1172 pci_set_drvdata(pdev, &xe->drm); 1173 1174 xe_pm_assert_unbounded_bridge(xe); 1175 1176 pci_set_master(pdev); 1177 1178 err = xe_probe_info_early(xe, desc, &probed_info); 1179 if (err) 1180 return err; 1181 1182 err = xe_info_init_early(xe, desc, subplatform_desc, &probed_info); 1183 if (err) 1184 return err; 1185 1186 xe_pci_rebar_resize(xe); 1187 1188 err = xe_device_probe_early(xe); 1189 /* 1190 * In Boot Survivability mode, no drm card is exposed and driver 1191 * is loaded with bare minimum to allow for firmware to be 1192 * flashed through mei. Return success, if survivability mode 1193 * is enabled due to pcode failure or configfs being set 1194 */ 1195 if (xe_survivability_mode_is_boot_enabled(xe)) 1196 return 0; 1197 1198 if (err) 1199 return err; 1200 1201 err = xe_probe_info(xe, desc, &probed_info); 1202 if (err) 1203 return err; 1204 1205 err = xe_info_init(xe, desc, &probed_info); 1206 if (err) 1207 return err; 1208 1209 err = xe_display_probe(xe); 1210 if (err) 1211 return err; 1212 1213 drm_dbg(&xe->drm, "%s %s %04x:%04x dgfx:%d gfx:%s (%d.%02d) media:%s (%d.%02d) display:%s dma_m_s:%d tc:%d gscfi:%d cscfi:%d", 1214 desc->platform_name, 1215 subplatform_desc ? subplatform_desc->name : "", 1216 xe->info.devid, xe->info.revid, 1217 xe->info.is_dgfx, 1218 xe->info.graphics_name, 1219 xe->info.graphics_verx100 / 100, 1220 xe->info.graphics_verx100 % 100, 1221 xe->info.media_name, 1222 xe->info.media_verx100 / 100, 1223 xe->info.media_verx100 % 100, 1224 str_yes_no(xe->info.probe_display), 1225 xe->info.dma_mask_size, xe->info.tile_count, 1226 xe->info.has_heci_gscfi, xe->info.has_heci_cscfi); 1227 1228 drm_dbg(&xe->drm, "Stepping = (G:%s, M:%s, B:%s)\n", 1229 xe_step_name(xe->info.step.graphics), 1230 xe_step_name(xe->info.step.media), 1231 xe_step_name(xe->info.step.basedie)); 1232 1233 drm_dbg(&xe->drm, "SR-IOV support: %s (mode: %s)\n", 1234 str_yes_no(xe_device_has_sriov(xe)), 1235 xe_sriov_mode_to_string(xe_device_sriov_mode(xe))); 1236 1237 err = xe_pm_probe(xe); 1238 if (err) 1239 return err; 1240 1241 err = xe_device_probe(xe); 1242 if (err) 1243 return err; 1244 1245 err = xe_pm_init(xe); 1246 if (err) 1247 goto err_driver_cleanup; 1248 1249 return 0; 1250 1251 err_driver_cleanup: 1252 xe_pci_remove(pdev); 1253 return err; 1254 } 1255 1256 static void xe_pci_shutdown(struct pci_dev *pdev) 1257 { 1258 xe_device_shutdown(pdev_to_xe_device(pdev)); 1259 } 1260 1261 #ifdef CONFIG_PM_SLEEP 1262 static void d3cold_toggle(struct pci_dev *pdev, enum toggle_d3cold toggle) 1263 { 1264 struct xe_device *xe = pdev_to_xe_device(pdev); 1265 struct pci_dev *root_pdev; 1266 1267 if (!xe->d3cold.capable) 1268 return; 1269 1270 root_pdev = pcie_find_root_port(pdev); 1271 if (!root_pdev) 1272 return; 1273 1274 switch (toggle) { 1275 case D3COLD_DISABLE: 1276 pci_d3cold_disable(root_pdev); 1277 break; 1278 case D3COLD_ENABLE: 1279 pci_d3cold_enable(root_pdev); 1280 break; 1281 } 1282 } 1283 1284 static int xe_pci_suspend(struct device *dev) 1285 { 1286 struct pci_dev *pdev = to_pci_dev(dev); 1287 struct xe_device *xe = pdev_to_xe_device(pdev); 1288 int err; 1289 1290 if (xe_survivability_mode_is_boot_enabled(xe)) 1291 return -EBUSY; 1292 1293 err = xe_pm_suspend(xe); 1294 if (err) 1295 return err; 1296 1297 /* 1298 * Enabling D3Cold is needed for S2Idle/S0ix. 1299 * It is save to allow here since xe_pm_suspend has evicted 1300 * the local memory and the direct complete optimization is disabled. 1301 */ 1302 d3cold_toggle(pdev, D3COLD_ENABLE); 1303 1304 pci_save_state(pdev); 1305 pci_disable_device(pdev); 1306 pci_set_power_state(pdev, PCI_D3cold); 1307 1308 return 0; 1309 } 1310 1311 static int xe_pci_resume(struct device *dev) 1312 { 1313 struct pci_dev *pdev = to_pci_dev(dev); 1314 int err; 1315 1316 /* Give back the D3Cold decision to the runtime P M*/ 1317 d3cold_toggle(pdev, D3COLD_DISABLE); 1318 1319 err = pci_set_power_state(pdev, PCI_D0); 1320 if (err) 1321 return err; 1322 1323 pci_restore_state(pdev); 1324 1325 err = pci_enable_device(pdev); 1326 if (err) 1327 return err; 1328 1329 pci_set_master(pdev); 1330 1331 err = xe_pm_resume(pdev_to_xe_device(pdev)); 1332 if (err) 1333 return err; 1334 1335 return 0; 1336 } 1337 1338 static int xe_pci_runtime_suspend(struct device *dev) 1339 { 1340 struct pci_dev *pdev = to_pci_dev(dev); 1341 struct xe_device *xe = pdev_to_xe_device(pdev); 1342 int err; 1343 1344 /* 1345 * We hold an additional reference to the runtime PM to keep PF in D0 1346 * during VFs lifetime, as our VFs do not implement the PM capability. 1347 * This means we should never be runtime suspending as long as VFs are 1348 * enabled. 1349 */ 1350 xe_assert(xe, !IS_SRIOV_VF(xe)); 1351 xe_assert(xe, !pci_num_vf(pdev)); 1352 1353 err = xe_pm_runtime_suspend(xe); 1354 if (err) 1355 return err; 1356 1357 pci_save_state(pdev); 1358 1359 if (xe->d3cold.allowed) { 1360 d3cold_toggle(pdev, D3COLD_ENABLE); 1361 pci_disable_device(pdev); 1362 pci_ignore_hotplug(pdev); 1363 pci_set_power_state(pdev, PCI_D3cold); 1364 } else { 1365 d3cold_toggle(pdev, D3COLD_DISABLE); 1366 pci_set_power_state(pdev, PCI_D3hot); 1367 } 1368 1369 return 0; 1370 } 1371 1372 static int xe_pci_runtime_resume(struct device *dev) 1373 { 1374 struct pci_dev *pdev = to_pci_dev(dev); 1375 struct xe_device *xe = pdev_to_xe_device(pdev); 1376 int err; 1377 1378 err = pci_set_power_state(pdev, PCI_D0); 1379 if (err) 1380 return err; 1381 1382 pci_restore_state(pdev); 1383 1384 if (xe->d3cold.allowed) { 1385 err = pci_enable_device(pdev); 1386 if (err) 1387 return err; 1388 1389 pci_set_master(pdev); 1390 } 1391 1392 return xe_pm_runtime_resume(xe); 1393 } 1394 1395 static int xe_pci_runtime_idle(struct device *dev) 1396 { 1397 struct pci_dev *pdev = to_pci_dev(dev); 1398 struct xe_device *xe = pdev_to_xe_device(pdev); 1399 1400 xe_pm_d3cold_allowed_toggle(xe); 1401 1402 return 0; 1403 } 1404 1405 static const struct dev_pm_ops xe_pm_ops = { 1406 SET_SYSTEM_SLEEP_PM_OPS(xe_pci_suspend, xe_pci_resume) 1407 SET_RUNTIME_PM_OPS(xe_pci_runtime_suspend, xe_pci_runtime_resume, xe_pci_runtime_idle) 1408 }; 1409 #endif 1410 1411 static struct pci_driver xe_pci_driver = { 1412 .name = DRIVER_NAME, 1413 .id_table = pciidlist, 1414 .probe = xe_pci_probe, 1415 .remove = xe_pci_remove, 1416 .shutdown = xe_pci_shutdown, 1417 .sriov_configure = xe_pci_sriov_configure, 1418 .err_handler = &xe_pci_error_handlers, 1419 #ifdef CONFIG_PM_SLEEP 1420 .driver.pm = &xe_pm_ops, 1421 #endif 1422 }; 1423 1424 /** 1425 * xe_pci_to_pf_device() - Get PF &xe_device. 1426 * @pdev: the VF &pci_dev device 1427 * 1428 * Return: pointer to PF &xe_device, NULL otherwise. 1429 */ 1430 struct xe_device *xe_pci_to_pf_device(struct pci_dev *pdev) 1431 { 1432 struct drm_device *drm; 1433 1434 drm = pci_iov_get_pf_drvdata(pdev, &xe_pci_driver); 1435 if (IS_ERR(drm)) 1436 return NULL; 1437 1438 return to_xe_device(drm); 1439 } 1440 1441 int xe_register_pci_driver(void) 1442 { 1443 return pci_register_driver(&xe_pci_driver); 1444 } 1445 1446 void xe_unregister_pci_driver(void) 1447 { 1448 pci_unregister_driver(&xe_pci_driver); 1449 } 1450 1451 #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST) 1452 #include "tests/xe_pci.c" 1453 #endif 1454