1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 #include "xe_pci.h" 7 8 #include <kunit/static_stub.h> 9 #include <linux/device/driver.h> 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/pm_runtime.h> 13 14 #include <drm/drm_color_mgmt.h> 15 #include <drm/drm_drv.h> 16 #include <drm/intel/pciids.h> 17 18 #include "display/xe_display.h" 19 #include "regs/xe_gt_regs.h" 20 #include "regs/xe_regs.h" 21 #include "xe_configfs.h" 22 #include "xe_device.h" 23 #include "xe_drv.h" 24 #include "xe_gt.h" 25 #include "xe_gt_sriov_vf.h" 26 #include "xe_guc.h" 27 #include "xe_mmio.h" 28 #include "xe_module.h" 29 #include "xe_pci_rebar.h" 30 #include "xe_pci_sriov.h" 31 #include "xe_pci_types.h" 32 #include "xe_pm.h" 33 #include "xe_printk.h" 34 #include "xe_sriov.h" 35 #include "xe_step.h" 36 #include "xe_survivability_mode.h" 37 #include "xe_tile.h" 38 39 enum toggle_d3cold { 40 D3COLD_DISABLE, 41 D3COLD_ENABLE, 42 }; 43 44 __diag_push(); 45 __diag_ignore_all("-Woverride-init", "Allow field overrides in table"); 46 47 #define PLATFORM(x) \ 48 .platform = XE_##x, \ 49 .platform_name = #x 50 51 #define NOP(x) x 52 53 static const struct xe_graphics_desc graphics_xelp = { 54 .hw_engine_mask = BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0), 55 .num_geometry_xecore_fuse_regs = 1, 56 }; 57 58 #define XE_HP_FEATURES \ 59 .has_range_tlb_inval = true 60 61 static const struct xe_graphics_desc graphics_xehpg = { 62 .hw_engine_mask = 63 BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) | 64 BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) | 65 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3), 66 .num_geometry_xecore_fuse_regs = 1, 67 .num_compute_xecore_fuse_regs = 1, 68 69 XE_HP_FEATURES, 70 }; 71 72 static const struct xe_graphics_desc graphics_xehpc = { 73 .hw_engine_mask = 74 BIT(XE_HW_ENGINE_BCS0) | BIT(XE_HW_ENGINE_BCS1) | 75 BIT(XE_HW_ENGINE_BCS2) | BIT(XE_HW_ENGINE_BCS3) | 76 BIT(XE_HW_ENGINE_BCS4) | BIT(XE_HW_ENGINE_BCS5) | 77 BIT(XE_HW_ENGINE_BCS6) | BIT(XE_HW_ENGINE_BCS7) | 78 BIT(XE_HW_ENGINE_BCS8) | 79 BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) | 80 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3), 81 82 XE_HP_FEATURES, 83 84 .has_access_counter = 1, 85 .has_asid = 1, 86 .has_atomic_enable_pte_bit = 1, 87 .has_usm = 1, 88 .num_compute_xecore_fuse_regs = 2, 89 }; 90 91 static const struct xe_graphics_desc graphics_xelpg = { 92 .hw_engine_mask = 93 BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) | 94 BIT(XE_HW_ENGINE_CCS0), 95 .num_geometry_xecore_fuse_regs = 1, 96 .num_compute_xecore_fuse_regs = 1, 97 98 XE_HP_FEATURES, 99 }; 100 101 #define XE2_GFX_FEATURES \ 102 .has_access_counter = 1, \ 103 .has_asid = 1, \ 104 .has_atomic_enable_pte_bit = 1, \ 105 .has_range_tlb_inval = 1, \ 106 .has_usm = 1, \ 107 .has_64bit_timestamp = 1, \ 108 .hw_engine_mask = \ 109 BIT(XE_HW_ENGINE_RCS0) | \ 110 BIT(XE_HW_ENGINE_BCS8) | BIT(XE_HW_ENGINE_BCS0) | \ 111 GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0) 112 113 static const struct xe_graphics_desc graphics_xe2 = { 114 XE2_GFX_FEATURES, 115 .num_geometry_xecore_fuse_regs = 3, 116 .num_compute_xecore_fuse_regs = 3, 117 }; 118 119 static const struct xe_graphics_desc graphics_xe3p_lpg = { 120 XE2_GFX_FEATURES, 121 .multi_queue_engine_class_mask = BIT(XE_ENGINE_CLASS_COPY) | BIT(XE_ENGINE_CLASS_COMPUTE), 122 .num_geometry_xecore_fuse_regs = 3, 123 .num_compute_xecore_fuse_regs = 3, 124 }; 125 126 static const struct xe_graphics_desc graphics_xe3p_xpc = { 127 XE2_GFX_FEATURES, 128 .has_access_counter = 0, 129 .has_indirect_ring_state = 1, 130 .hw_engine_mask = 131 GENMASK(XE_HW_ENGINE_BCS8, XE_HW_ENGINE_BCS1) | 132 GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0), 133 .multi_queue_engine_class_mask = BIT(XE_ENGINE_CLASS_COPY) | 134 BIT(XE_ENGINE_CLASS_COMPUTE), 135 .num_geometry_xecore_fuse_regs = 4, 136 .num_compute_xecore_fuse_regs = 4, 137 }; 138 139 static const struct xe_media_desc media_xem = { 140 .hw_engine_mask = 141 GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) | 142 GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0), 143 }; 144 145 static const struct xe_media_desc media_xelpmp = { 146 .hw_engine_mask = 147 GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) | 148 GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0) | 149 BIT(XE_HW_ENGINE_GSCCS0) 150 }; 151 152 /* Pre-GMDID Graphics IPs */ 153 static const struct xe_ip graphics_ip_xelp = { 1200, "Xe_LP", &graphics_xelp }; 154 static const struct xe_ip graphics_ip_xelpp = { 1210, "Xe_LP+", &graphics_xelp }; 155 static const struct xe_ip graphics_ip_xehpg = { 1255, "Xe_HPG", &graphics_xehpg }; 156 static const struct xe_ip graphics_ip_xehpc = { 1260, "Xe_HPC", &graphics_xehpc }; 157 158 /* GMDID-based Graphics IPs */ 159 static const struct xe_ip graphics_ips[] = { 160 { 1270, "Xe_LPG", &graphics_xelpg }, 161 { 1271, "Xe_LPG", &graphics_xelpg }, 162 { 1274, "Xe_LPG+", &graphics_xelpg }, 163 { 2001, "Xe2_HPG", &graphics_xe2 }, 164 { 2002, "Xe2_HPG", &graphics_xe2 }, 165 { 2004, "Xe2_LPG", &graphics_xe2 }, 166 { 3000, "Xe3_LPG", &graphics_xe2 }, 167 { 3001, "Xe3_LPG", &graphics_xe2 }, 168 { 3003, "Xe3_LPG", &graphics_xe2 }, 169 { 3004, "Xe3_LPG", &graphics_xe2 }, 170 { 3005, "Xe3_LPG", &graphics_xe2 }, 171 { 3510, "Xe3p_LPG", &graphics_xe3p_lpg }, 172 { 3511, "Xe3p_XPC", &graphics_xe3p_xpc }, 173 }; 174 175 /* Pre-GMDID Media IPs */ 176 static const struct xe_ip media_ip_xem = { 1200, "Xe_M", &media_xem }; 177 static const struct xe_ip media_ip_xehpm = { 1255, "Xe_HPM", &media_xem }; 178 179 /* GMDID-based Media IPs */ 180 static const struct xe_ip media_ips[] = { 181 { 1300, "Xe_LPM+", &media_xelpmp }, 182 { 1301, "Xe2_HPM", &media_xelpmp }, 183 { 2000, "Xe2_LPM", &media_xelpmp }, 184 { 3000, "Xe3_LPM", &media_xelpmp }, 185 { 3002, "Xe3_LPM", &media_xelpmp }, 186 { 3500, "Xe3p_LPM", &media_xelpmp }, 187 { 3503, "Xe3p_HPM", &media_xelpmp }, 188 }; 189 190 #define MULTI_LRC_MASK \ 191 .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE) | \ 192 BIT(XE_ENGINE_CLASS_VIDEO_ENHANCE) 193 194 static const struct xe_device_desc tgl_desc = { 195 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 196 .pre_gmdid_media_ip = &media_ip_xem, 197 PLATFORM(TIGERLAKE), 198 .dma_mask_size = 39, 199 .has_cached_pt = true, 200 .has_display = true, 201 .has_llc = true, 202 .has_sriov = true, 203 .max_gt_per_tile = 1, 204 MULTI_LRC_MASK, 205 .require_force_probe = true, 206 .va_bits = 48, 207 .vm_max_level = 3, 208 }; 209 210 static const struct xe_device_desc rkl_desc = { 211 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 212 .pre_gmdid_media_ip = &media_ip_xem, 213 PLATFORM(ROCKETLAKE), 214 .dma_mask_size = 39, 215 .has_cached_pt = true, 216 .has_display = true, 217 .has_llc = true, 218 .max_gt_per_tile = 1, 219 MULTI_LRC_MASK, 220 .require_force_probe = true, 221 .va_bits = 48, 222 .vm_max_level = 3, 223 }; 224 225 static const u16 adls_rpls_ids[] = { INTEL_RPLS_IDS(NOP), 0 }; 226 227 static const struct xe_device_desc adl_s_desc = { 228 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 229 .pre_gmdid_media_ip = &media_ip_xem, 230 PLATFORM(ALDERLAKE_S), 231 .dma_mask_size = 39, 232 .has_cached_pt = true, 233 .has_display = true, 234 .has_llc = true, 235 .has_sriov = true, 236 .max_gt_per_tile = 1, 237 MULTI_LRC_MASK, 238 .require_force_probe = true, 239 .subplatforms = (const struct xe_subplatform_desc[]) { 240 { XE_SUBPLATFORM_ALDERLAKE_S_RPLS, "RPLS", adls_rpls_ids }, 241 {}, 242 }, 243 .va_bits = 48, 244 .vm_max_level = 3, 245 }; 246 247 static const u16 adlp_rplu_ids[] = { INTEL_RPLU_IDS(NOP), 0 }; 248 249 static const struct xe_device_desc adl_p_desc = { 250 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 251 .pre_gmdid_media_ip = &media_ip_xem, 252 PLATFORM(ALDERLAKE_P), 253 .dma_mask_size = 39, 254 .has_cached_pt = true, 255 .has_display = true, 256 .has_llc = true, 257 .has_sriov = true, 258 .max_gt_per_tile = 1, 259 MULTI_LRC_MASK, 260 .require_force_probe = true, 261 .subplatforms = (const struct xe_subplatform_desc[]) { 262 { XE_SUBPLATFORM_ALDERLAKE_P_RPLU, "RPLU", adlp_rplu_ids }, 263 {}, 264 }, 265 .va_bits = 48, 266 .vm_max_level = 3, 267 }; 268 269 static const struct xe_device_desc adl_n_desc = { 270 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 271 .pre_gmdid_media_ip = &media_ip_xem, 272 PLATFORM(ALDERLAKE_N), 273 .dma_mask_size = 39, 274 .has_cached_pt = true, 275 .has_display = true, 276 .has_llc = true, 277 .has_sriov = true, 278 .max_gt_per_tile = 1, 279 MULTI_LRC_MASK, 280 .require_force_probe = true, 281 .va_bits = 48, 282 .vm_max_level = 3, 283 }; 284 285 #define DGFX_FEATURES \ 286 .is_dgfx = 1 287 288 static const struct xe_device_desc dg1_desc = { 289 .pre_gmdid_graphics_ip = &graphics_ip_xelpp, 290 .pre_gmdid_media_ip = &media_ip_xem, 291 DGFX_FEATURES, 292 PLATFORM(DG1), 293 .dma_mask_size = 39, 294 .has_display = true, 295 .has_gsc_nvm = 1, 296 .has_heci_gscfi = 1, 297 .max_gt_per_tile = 1, 298 MULTI_LRC_MASK, 299 .require_force_probe = true, 300 .va_bits = 48, 301 .vm_max_level = 3, 302 }; 303 304 static const u16 dg2_g10_ids[] = { INTEL_DG2_G10_IDS(NOP), INTEL_ATS_M150_IDS(NOP), 0 }; 305 static const u16 dg2_g11_ids[] = { INTEL_DG2_G11_IDS(NOP), INTEL_ATS_M75_IDS(NOP), 0 }; 306 static const u16 dg2_g12_ids[] = { INTEL_DG2_G12_IDS(NOP), 0 }; 307 308 #define DG2_FEATURES \ 309 DGFX_FEATURES, \ 310 PLATFORM(DG2), \ 311 .has_flat_ccs = 1, \ 312 .has_gsc_nvm = 1, \ 313 .has_heci_gscfi = 1, \ 314 .subplatforms = (const struct xe_subplatform_desc[]) { \ 315 { XE_SUBPLATFORM_DG2_G10, "G10", dg2_g10_ids }, \ 316 { XE_SUBPLATFORM_DG2_G11, "G11", dg2_g11_ids }, \ 317 { XE_SUBPLATFORM_DG2_G12, "G12", dg2_g12_ids }, \ 318 { } \ 319 }, \ 320 .va_bits = 48, \ 321 .vm_max_level = 3, \ 322 .vram_flags = XE_VRAM_FLAGS_NEED64K 323 324 static const struct xe_device_desc ats_m_desc = { 325 .pre_gmdid_graphics_ip = &graphics_ip_xehpg, 326 .pre_gmdid_media_ip = &media_ip_xehpm, 327 .dma_mask_size = 46, 328 .max_gt_per_tile = 1, 329 MULTI_LRC_MASK, 330 .require_force_probe = true, 331 332 DG2_FEATURES, 333 .has_display = false, 334 .has_sriov = true, 335 }; 336 337 static const struct xe_device_desc dg2_desc = { 338 .pre_gmdid_graphics_ip = &graphics_ip_xehpg, 339 .pre_gmdid_media_ip = &media_ip_xehpm, 340 .dma_mask_size = 46, 341 .max_gt_per_tile = 1, 342 MULTI_LRC_MASK, 343 .require_force_probe = true, 344 345 DG2_FEATURES, 346 .has_display = true, 347 .has_fan_control = true, 348 .has_mbx_power_limits = false, 349 }; 350 351 static const __maybe_unused struct xe_device_desc pvc_desc = { 352 .pre_gmdid_graphics_ip = &graphics_ip_xehpc, 353 DGFX_FEATURES, 354 PLATFORM(PVC), 355 .dma_mask_size = 52, 356 .has_display = false, 357 .has_gsc_nvm = 1, 358 .has_heci_gscfi = 1, 359 .max_gt_per_tile = 1, 360 .max_remote_tiles = 1, 361 MULTI_LRC_MASK, 362 .require_force_probe = true, 363 .va_bits = 57, 364 .vm_max_level = 4, 365 .vram_flags = XE_VRAM_FLAGS_NEED64K, 366 .has_mbx_power_limits = false, 367 }; 368 369 static const struct xe_device_desc mtl_desc = { 370 /* .graphics and .media determined via GMD_ID */ 371 .require_force_probe = true, 372 PLATFORM(METEORLAKE), 373 .dma_mask_size = 46, 374 .has_display = true, 375 .has_pxp = true, 376 .max_gt_per_tile = 2, 377 MULTI_LRC_MASK, 378 .va_bits = 48, 379 .vm_max_level = 3, 380 }; 381 382 static const struct xe_device_desc lnl_desc = { 383 PLATFORM(LUNARLAKE), 384 .dma_mask_size = 46, 385 .has_display = true, 386 .has_flat_ccs = 1, 387 .has_pxp = true, 388 .max_gt_per_tile = 2, 389 MULTI_LRC_MASK, 390 .needs_scratch = true, 391 .va_bits = 48, 392 .vm_max_level = 4, 393 }; 394 395 static const u16 bmg_g21_ids[] = { INTEL_BMG_G21_IDS(NOP), 0 }; 396 397 static const struct xe_device_desc bmg_desc = { 398 DGFX_FEATURES, 399 PLATFORM(BATTLEMAGE), 400 .dma_mask_size = 46, 401 .has_display = true, 402 .has_fan_control = true, 403 .has_flat_ccs = 1, 404 .has_mbx_power_limits = true, 405 .has_mbx_thermal_info = true, 406 .has_gsc_nvm = 1, 407 .has_heci_cscfi = 1, 408 .has_i2c = true, 409 .has_late_bind = true, 410 .has_pre_prod_wa = 1, 411 .has_soc_remapper_telem = true, 412 .has_sriov = true, 413 .max_gt_per_tile = 2, 414 MULTI_LRC_MASK, 415 .needs_scratch = true, 416 .subplatforms = (const struct xe_subplatform_desc[]) { 417 { XE_SUBPLATFORM_BATTLEMAGE_G21, "G21", bmg_g21_ids }, 418 { } 419 }, 420 .va_bits = 48, 421 .vm_max_level = 4, 422 }; 423 424 static const struct xe_device_desc ptl_desc = { 425 PLATFORM(PANTHERLAKE), 426 .dma_mask_size = 46, 427 .has_display = true, 428 .has_flat_ccs = 1, 429 .has_sriov = true, 430 .has_pre_prod_wa = 1, 431 .has_pxp = true, 432 .max_gt_per_tile = 2, 433 MULTI_LRC_MASK, 434 .needs_scratch = true, 435 .needs_shared_vf_gt_wq = true, 436 .va_bits = 48, 437 .vm_max_level = 4, 438 }; 439 440 static const struct xe_device_desc nvls_desc = { 441 PLATFORM(NOVALAKE_S), 442 .dma_mask_size = 46, 443 .has_display = true, 444 .has_flat_ccs = 1, 445 .has_pre_prod_wa = 1, 446 .max_gt_per_tile = 2, 447 MULTI_LRC_MASK, 448 .require_force_probe = true, 449 .va_bits = 48, 450 .vm_max_level = 4, 451 }; 452 453 static const struct xe_device_desc cri_desc = { 454 DGFX_FEATURES, 455 PLATFORM(CRESCENTISLAND), 456 .dma_mask_size = 52, 457 .has_display = false, 458 .has_flat_ccs = false, 459 .has_gsc_nvm = 1, 460 .has_i2c = true, 461 .has_mbx_power_limits = true, 462 .has_mbx_thermal_info = true, 463 .has_mert = true, 464 .has_pre_prod_wa = 1, 465 .has_soc_remapper_sysctrl = true, 466 .has_soc_remapper_telem = true, 467 .has_sriov = true, 468 .max_gt_per_tile = 2, 469 MULTI_LRC_MASK, 470 .require_force_probe = true, 471 .va_bits = 57, 472 .vm_max_level = 4, 473 }; 474 475 static const struct xe_device_desc nvlp_desc = { 476 PLATFORM(NOVALAKE_P), 477 .dma_mask_size = 46, 478 .has_cached_pt = true, 479 .has_display = true, 480 .has_flat_ccs = 1, 481 .has_page_reclaim_hw_assist = true, 482 .has_pre_prod_wa = true, 483 .max_gt_per_tile = 2, 484 MULTI_LRC_MASK, 485 .require_force_probe = true, 486 .va_bits = 48, 487 .vm_max_level = 4, 488 }; 489 490 #undef PLATFORM 491 __diag_pop(); 492 493 /* 494 * Make sure any device matches here are from most specific to most 495 * general. For example, since the Quanta match is based on the subsystem 496 * and subvendor IDs, we need it to come before the more general IVB 497 * PCI ID matches, otherwise we'll use the wrong info struct above. 498 */ 499 static const struct pci_device_id pciidlist[] = { 500 INTEL_TGL_IDS(INTEL_VGA_DEVICE, &tgl_desc), 501 INTEL_RKL_IDS(INTEL_VGA_DEVICE, &rkl_desc), 502 INTEL_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc), 503 INTEL_ADLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 504 INTEL_ADLN_IDS(INTEL_VGA_DEVICE, &adl_n_desc), 505 INTEL_RPLU_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 506 INTEL_RPLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 507 INTEL_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc), 508 INTEL_DG1_IDS(INTEL_VGA_DEVICE, &dg1_desc), 509 INTEL_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_desc), 510 INTEL_ARL_IDS(INTEL_VGA_DEVICE, &mtl_desc), 511 INTEL_DG2_IDS(INTEL_VGA_DEVICE, &dg2_desc), 512 INTEL_MTL_IDS(INTEL_VGA_DEVICE, &mtl_desc), 513 INTEL_LNL_IDS(INTEL_VGA_DEVICE, &lnl_desc), 514 INTEL_BMG_IDS(INTEL_VGA_DEVICE, &bmg_desc), 515 INTEL_PTL_IDS(INTEL_VGA_DEVICE, &ptl_desc), 516 INTEL_WCL_IDS(INTEL_VGA_DEVICE, &ptl_desc), 517 INTEL_NVLS_IDS(INTEL_VGA_DEVICE, &nvls_desc), 518 INTEL_CRI_IDS(INTEL_PCI_DEVICE, &cri_desc), 519 INTEL_NVLP_IDS(INTEL_VGA_DEVICE, &nvlp_desc), 520 { } 521 }; 522 MODULE_DEVICE_TABLE(pci, pciidlist); 523 524 /* is device_id present in comma separated list of ids */ 525 static bool device_id_in_list(u16 device_id, const char *devices, bool negative) 526 { 527 char *s, *p, *tok; 528 bool ret; 529 530 if (!devices || !*devices) 531 return false; 532 533 /* match everything */ 534 if (negative && strcmp(devices, "!*") == 0) 535 return true; 536 if (!negative && strcmp(devices, "*") == 0) 537 return true; 538 539 s = kstrdup(devices, GFP_KERNEL); 540 if (!s) 541 return false; 542 543 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) { 544 u16 val; 545 546 if (negative && tok[0] == '!') 547 tok++; 548 else if ((negative && tok[0] != '!') || 549 (!negative && tok[0] == '!')) 550 continue; 551 552 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) { 553 ret = true; 554 break; 555 } 556 } 557 558 kfree(s); 559 560 return ret; 561 } 562 563 static bool id_forced(u16 device_id) 564 { 565 return device_id_in_list(device_id, xe_modparam.force_probe, false); 566 } 567 568 static bool id_blocked(u16 device_id) 569 { 570 return device_id_in_list(device_id, xe_modparam.force_probe, true); 571 } 572 573 static const struct xe_subplatform_desc * 574 find_subplatform(const struct xe_device *xe, const struct xe_device_desc *desc) 575 { 576 const struct xe_subplatform_desc *sp; 577 const u16 *id; 578 579 for (sp = desc->subplatforms; sp && sp->subplatform; sp++) 580 for (id = sp->pciidlist; *id; id++) 581 if (*id == xe->info.devid) 582 return sp; 583 584 return NULL; 585 } 586 587 enum xe_gmdid_type { 588 GMDID_GRAPHICS, 589 GMDID_MEDIA 590 }; 591 592 static int read_gmdid(struct xe_device *xe, enum xe_gmdid_type type, u32 *ver, u32 *revid) 593 { 594 struct xe_mmio *mmio = xe_root_tile_mmio(xe); 595 struct xe_reg gmdid_reg = GMD_ID; 596 u32 val; 597 598 KUNIT_STATIC_STUB_REDIRECT(read_gmdid, xe, type, ver, revid); 599 600 if (IS_SRIOV_VF(xe)) { 601 /* 602 * To get the value of the GMDID register, VFs must obtain it 603 * from the GuC using MMIO communication. 604 * 605 * Note that at this point the GTs are not initialized and only 606 * tile-level access to MMIO registers is possible. To use our 607 * existing GuC communication functions we must create a dummy 608 * GT structure and perform at least basic xe_gt and xe_guc 609 * initialization. 610 */ 611 struct xe_gt *gt __free(kfree) = NULL; 612 int err; 613 614 /* Don't try to read media ver if media GT is not allowed */ 615 if (type == GMDID_MEDIA && !xe_configfs_media_gt_allowed(to_pci_dev(xe->drm.dev))) { 616 *ver = *revid = 0; 617 return 0; 618 } 619 620 gt = kzalloc(sizeof(*gt), GFP_KERNEL); 621 if (!gt) 622 return -ENOMEM; 623 624 gt->tile = &xe->tiles[0]; 625 if (type == GMDID_MEDIA) { 626 gt->info.id = 1; 627 gt->info.type = XE_GT_TYPE_MEDIA; 628 } else { 629 gt->info.id = 0; 630 gt->info.type = XE_GT_TYPE_MAIN; 631 } 632 633 xe_gt_mmio_init(gt); 634 xe_guc_comm_init_early(>->uc.guc); 635 636 err = xe_gt_sriov_vf_bootstrap(gt); 637 if (err) 638 return err; 639 640 val = xe_gt_sriov_vf_gmdid(gt); 641 } else { 642 /* 643 * GMD_ID is a GT register, but at this point in the driver 644 * init we haven't fully initialized the GT yet so we need to 645 * read the register with the tile's MMIO accessor. That means 646 * we need to apply the GSI offset manually since it won't get 647 * automatically added as it would if we were using a GT mmio 648 * accessor. 649 */ 650 if (type == GMDID_MEDIA) 651 gmdid_reg.addr += MEDIA_GT_GSI_OFFSET; 652 653 val = xe_mmio_read32(mmio, gmdid_reg); 654 } 655 656 *ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val) * 100 + REG_FIELD_GET(GMD_ID_RELEASE_MASK, val); 657 *revid = REG_FIELD_GET(GMD_ID_REVID, val); 658 659 return 0; 660 } 661 662 static const struct xe_ip *find_graphics_ip(unsigned int verx100) 663 { 664 KUNIT_STATIC_STUB_REDIRECT(find_graphics_ip, verx100); 665 666 for (int i = 0; i < ARRAY_SIZE(graphics_ips); i++) 667 if (graphics_ips[i].verx100 == verx100) 668 return &graphics_ips[i]; 669 return NULL; 670 } 671 672 static const struct xe_ip *find_media_ip(unsigned int verx100) 673 { 674 KUNIT_STATIC_STUB_REDIRECT(find_media_ip, verx100); 675 676 for (int i = 0; i < ARRAY_SIZE(media_ips); i++) 677 if (media_ips[i].verx100 == verx100) 678 return &media_ips[i]; 679 return NULL; 680 } 681 682 /* 683 * Read IP version from hardware and select graphics/media IP descriptors 684 * based on the result. 685 */ 686 static int handle_gmdid(struct xe_device *xe, 687 const struct xe_ip **graphics_ip, 688 const struct xe_ip **media_ip, 689 u32 *graphics_revid, 690 u32 *media_revid) 691 { 692 u32 ver; 693 int ret; 694 695 *graphics_ip = NULL; 696 *media_ip = NULL; 697 698 ret = read_gmdid(xe, GMDID_GRAPHICS, &ver, graphics_revid); 699 if (ret) 700 return ret; 701 702 *graphics_ip = find_graphics_ip(ver); 703 if (!*graphics_ip) { 704 drm_err(&xe->drm, "Hardware reports unknown graphics version %u.%02u\n", 705 ver / 100, ver % 100); 706 } 707 708 ret = read_gmdid(xe, GMDID_MEDIA, &ver, media_revid); 709 if (ret) 710 return ret; 711 712 /* Media may legitimately be fused off / not present */ 713 if (ver == 0) 714 return 0; 715 716 *media_ip = find_media_ip(ver); 717 if (!*media_ip) { 718 drm_err(&xe->drm, "Hardware reports unknown media version %u.%02u\n", 719 ver / 100, ver % 100); 720 } 721 722 return 0; 723 } 724 725 /* 726 * Initialize device info content that only depends on static driver_data 727 * passed to the driver at probe time from PCI ID table. 728 */ 729 static int xe_info_init_early(struct xe_device *xe, 730 const struct xe_device_desc *desc, 731 const struct xe_subplatform_desc *subplatform_desc) 732 { 733 int err; 734 735 xe->info.platform_name = desc->platform_name; 736 xe->info.platform = desc->platform; 737 xe->info.subplatform = subplatform_desc ? 738 subplatform_desc->subplatform : XE_SUBPLATFORM_NONE; 739 740 xe->info.dma_mask_size = desc->dma_mask_size; 741 xe->info.va_bits = desc->va_bits; 742 xe->info.vm_max_level = desc->vm_max_level; 743 xe->info.vram_flags = desc->vram_flags; 744 745 xe->info.is_dgfx = desc->is_dgfx; 746 xe->info.has_cached_pt = desc->has_cached_pt; 747 xe->info.has_fan_control = desc->has_fan_control; 748 /* runtime fusing may force flat_ccs to disabled later */ 749 xe->info.has_flat_ccs = desc->has_flat_ccs; 750 xe->info.has_mbx_power_limits = desc->has_mbx_power_limits; 751 xe->info.has_mbx_thermal_info = desc->has_mbx_thermal_info; 752 xe->info.has_gsc_nvm = desc->has_gsc_nvm; 753 xe->info.has_heci_gscfi = desc->has_heci_gscfi; 754 xe->info.has_heci_cscfi = desc->has_heci_cscfi; 755 xe->info.has_i2c = desc->has_i2c; 756 xe->info.has_late_bind = desc->has_late_bind; 757 xe->info.has_llc = desc->has_llc; 758 xe->info.has_mert = desc->has_mert; 759 xe->info.has_page_reclaim_hw_assist = desc->has_page_reclaim_hw_assist; 760 xe->info.has_pre_prod_wa = desc->has_pre_prod_wa; 761 xe->info.has_pxp = desc->has_pxp; 762 xe->info.has_soc_remapper_sysctrl = desc->has_soc_remapper_sysctrl; 763 xe->info.has_soc_remapper_telem = desc->has_soc_remapper_telem; 764 xe->info.has_sriov = xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev)) && 765 desc->has_sriov; 766 xe->info.skip_guc_pc = desc->skip_guc_pc; 767 xe->info.skip_mtcfg = desc->skip_mtcfg; 768 xe->info.skip_pcode = desc->skip_pcode; 769 xe->info.needs_scratch = desc->needs_scratch; 770 xe->info.needs_shared_vf_gt_wq = desc->needs_shared_vf_gt_wq; 771 xe->info.multi_lrc_mask = desc->multi_lrc_mask; 772 773 xe->info.probe_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) && 774 xe_modparam.probe_display && 775 desc->has_display; 776 777 xe_assert(xe, desc->max_gt_per_tile > 0); 778 xe_assert(xe, desc->max_gt_per_tile <= XE_MAX_GT_PER_TILE); 779 xe->info.max_gt_per_tile = desc->max_gt_per_tile; 780 xe->info.tile_count = 1 + desc->max_remote_tiles; 781 782 xe_step_platform_get(xe); 783 784 err = xe_tile_init_early(xe_device_get_root_tile(xe), xe, 0); 785 if (err) 786 return err; 787 788 return 0; 789 } 790 791 /* 792 * Possibly override number of tile based on configuration register. 793 */ 794 static void xe_info_probe_tile_count(struct xe_device *xe) 795 { 796 struct xe_mmio *mmio; 797 u8 tile_count; 798 u32 mtcfg; 799 800 KUNIT_STATIC_STUB_REDIRECT(xe_info_probe_tile_count, xe); 801 802 /* 803 * Probe for tile count only for platforms that support multiple 804 * tiles. 805 */ 806 if (xe->info.tile_count == 1) 807 return; 808 809 if (xe->info.skip_mtcfg) 810 return; 811 812 mmio = xe_root_tile_mmio(xe); 813 814 /* 815 * Although the per-tile mmio regs are not yet initialized, this 816 * is fine as it's going to the root tile's mmio, that's 817 * guaranteed to be initialized earlier in xe_mmio_probe_early() 818 */ 819 mtcfg = xe_mmio_read32(mmio, XEHP_MTCFG_ADDR); 820 tile_count = REG_FIELD_GET(TILE_COUNT, mtcfg) + 1; 821 822 if (tile_count < xe->info.tile_count) { 823 drm_info(&xe->drm, "tile_count: %d, reduced_tile_count %d\n", 824 xe->info.tile_count, tile_count); 825 xe->info.tile_count = tile_count; 826 } 827 } 828 829 static struct xe_gt *alloc_primary_gt(struct xe_tile *tile, 830 const struct xe_graphics_desc *graphics_desc, 831 const struct xe_media_desc *media_desc) 832 { 833 struct xe_device *xe = tile_to_xe(tile); 834 struct xe_gt *gt; 835 836 if (!xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev))) { 837 xe_info(xe, "Primary GT disabled via configfs\n"); 838 return NULL; 839 } 840 841 gt = xe_gt_alloc(tile); 842 if (IS_ERR(gt)) 843 return gt; 844 845 gt->info.type = XE_GT_TYPE_MAIN; 846 gt->info.id = tile->id * xe->info.max_gt_per_tile; 847 gt->info.has_indirect_ring_state = graphics_desc->has_indirect_ring_state; 848 gt->info.multi_queue_engine_class_mask = graphics_desc->multi_queue_engine_class_mask; 849 gt->info.engine_mask = graphics_desc->hw_engine_mask; 850 gt->info.num_geometry_xecore_fuse_regs = graphics_desc->num_geometry_xecore_fuse_regs; 851 gt->info.num_compute_xecore_fuse_regs = graphics_desc->num_compute_xecore_fuse_regs; 852 853 /* 854 * Before media version 13, the media IP was part of the primary GT 855 * so we need to add the media engines to the primary GT's engine list. 856 */ 857 if (MEDIA_VER(xe) < 13 && media_desc) 858 gt->info.engine_mask |= media_desc->hw_engine_mask; 859 860 return gt; 861 } 862 863 static struct xe_gt *alloc_media_gt(struct xe_tile *tile, 864 const struct xe_media_desc *media_desc) 865 { 866 struct xe_device *xe = tile_to_xe(tile); 867 struct xe_gt *gt; 868 869 if (!xe_configfs_media_gt_allowed(to_pci_dev(xe->drm.dev))) { 870 xe_info(xe, "Media GT disabled via configfs\n"); 871 return NULL; 872 } 873 874 if (MEDIA_VER(xe) < 13 || !media_desc) 875 return NULL; 876 877 gt = xe_gt_alloc(tile); 878 if (IS_ERR(gt)) 879 return gt; 880 881 gt->info.type = XE_GT_TYPE_MEDIA; 882 gt->info.id = tile->id * xe->info.max_gt_per_tile + 1; 883 gt->info.has_indirect_ring_state = media_desc->has_indirect_ring_state; 884 gt->info.engine_mask = media_desc->hw_engine_mask; 885 886 return gt; 887 } 888 889 /* 890 * Initialize device info content that does require knowledge about 891 * graphics / media IP version. 892 * Make sure that GT / tile structures allocated by the driver match the data 893 * present in device info. 894 */ 895 static int xe_info_init(struct xe_device *xe, 896 const struct xe_device_desc *desc) 897 { 898 u32 graphics_gmdid_revid = 0, media_gmdid_revid = 0; 899 const struct xe_ip *graphics_ip; 900 const struct xe_ip *media_ip; 901 const struct xe_graphics_desc *graphics_desc; 902 const struct xe_media_desc *media_desc; 903 struct xe_tile *tile; 904 struct xe_gt *gt; 905 int ret; 906 u8 id; 907 908 /* 909 * If this platform supports GMD_ID, we'll detect the proper IP 910 * descriptor to use from hardware registers. 911 * desc->pre_gmdid_graphics_ip will only ever be set at this point for 912 * platforms before GMD_ID. In that case the IP descriptions and 913 * versions are simply derived from that. 914 */ 915 if (desc->pre_gmdid_graphics_ip) { 916 graphics_ip = desc->pre_gmdid_graphics_ip; 917 media_ip = desc->pre_gmdid_media_ip; 918 xe_step_pre_gmdid_get(xe); 919 } else { 920 xe_assert(xe, !desc->pre_gmdid_media_ip); 921 ret = handle_gmdid(xe, &graphics_ip, &media_ip, 922 &graphics_gmdid_revid, &media_gmdid_revid); 923 if (ret) 924 return ret; 925 926 xe_step_gmdid_get(xe, graphics_gmdid_revid, media_gmdid_revid); 927 } 928 929 /* 930 * If we couldn't detect the graphics IP, that's considered a fatal 931 * error and we should abort driver load. Failing to detect media 932 * IP is non-fatal; we'll just proceed without enabling media support. 933 */ 934 if (!graphics_ip) 935 return -ENODEV; 936 937 xe->info.graphics_verx100 = graphics_ip->verx100; 938 xe->info.graphics_name = graphics_ip->name; 939 graphics_desc = graphics_ip->desc; 940 941 if (media_ip) { 942 xe->info.media_verx100 = media_ip->verx100; 943 xe->info.media_name = media_ip->name; 944 media_desc = media_ip->desc; 945 } else { 946 xe->info.media_name = "none"; 947 media_desc = NULL; 948 } 949 950 xe->info.has_access_counter = graphics_desc->has_access_counter; 951 xe->info.has_asid = graphics_desc->has_asid; 952 xe->info.has_atomic_enable_pte_bit = graphics_desc->has_atomic_enable_pte_bit; 953 if (xe->info.platform != XE_PVC) 954 xe->info.has_device_atomics_on_smem = 1; 955 956 xe->info.has_range_tlb_inval = graphics_desc->has_range_tlb_inval; 957 xe->info.has_ctx_tlb_inval = graphics_desc->has_ctx_tlb_inval; 958 xe->info.has_usm = graphics_desc->has_usm; 959 xe->info.has_64bit_timestamp = graphics_desc->has_64bit_timestamp; 960 xe->info.has_mem_copy_instr = GRAPHICS_VER(xe) >= 20; 961 962 xe_info_probe_tile_count(xe); 963 964 for_each_remote_tile(tile, xe, id) { 965 int err; 966 967 err = xe_tile_init_early(tile, xe, id); 968 if (err) 969 return err; 970 } 971 972 /* Allocate any GT and VRAM structures necessary for the platform. */ 973 for_each_tile(tile, xe, id) { 974 int err; 975 976 err = xe_tile_alloc_vram(tile); 977 if (err) 978 return err; 979 980 tile->primary_gt = alloc_primary_gt(tile, graphics_desc, media_desc); 981 if (IS_ERR(tile->primary_gt)) 982 return PTR_ERR(tile->primary_gt); 983 984 /* 985 * It's not currently possible to probe a device with the 986 * primary GT disabled. With some work, this may be future in 987 * the possible for igpu platforms (although probably not for 988 * dgpu's since access to the primary GT's BCS engines is 989 * required for VRAM management). 990 */ 991 if (!tile->primary_gt) { 992 drm_err(&xe->drm, "Cannot probe device with without a primary GT\n"); 993 return -ENODEV; 994 } 995 996 tile->media_gt = alloc_media_gt(tile, media_desc); 997 if (IS_ERR(tile->media_gt)) 998 return PTR_ERR(tile->media_gt); 999 } 1000 1001 /* 1002 * Now that we have tiles and GTs defined, let's loop over valid GTs 1003 * in order to define gt_count. 1004 */ 1005 for_each_gt(gt, xe, id) 1006 xe->info.gt_count++; 1007 1008 return 0; 1009 } 1010 1011 static void xe_pci_remove(struct pci_dev *pdev) 1012 { 1013 struct xe_device *xe = pdev_to_xe_device(pdev); 1014 1015 if (IS_SRIOV_PF(xe)) 1016 xe_pci_sriov_configure(pdev, 0); 1017 1018 if (xe_survivability_mode_is_boot_enabled(xe)) 1019 return; 1020 1021 xe_device_remove(xe); 1022 xe_pm_fini(xe); 1023 } 1024 1025 /* 1026 * Probe the PCI device, initialize various parts of the driver. 1027 * 1028 * Fault injection is used to test the error paths of some initialization 1029 * functions called either directly from xe_pci_probe() or indirectly for 1030 * example through xe_device_probe(). Those functions use the kernel fault 1031 * injection capabilities infrastructure, see 1032 * Documentation/fault-injection/fault-injection.rst for details. The macro 1033 * ALLOW_ERROR_INJECTION() is used to conditionally skip function execution 1034 * at runtime and use a provided return value. The first requirement for 1035 * error injectable functions is proper handling of the error code by the 1036 * caller for recovery, which is always the case here. The second 1037 * requirement is that no state is changed before the first error return. 1038 * It is not strictly fulfilled for all initialization functions using the 1039 * ALLOW_ERROR_INJECTION() macro but this is acceptable because for those 1040 * error cases at probe time, the error code is simply propagated up by the 1041 * caller. Therefore there is no consequence on those specific callers when 1042 * function error injection skips the whole function. 1043 */ 1044 static int xe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1045 { 1046 const struct xe_device_desc *desc = (const void *)ent->driver_data; 1047 const struct xe_subplatform_desc *subplatform_desc; 1048 struct xe_device *xe; 1049 int err; 1050 1051 xe_configfs_check_device(pdev); 1052 1053 if (desc->require_force_probe && !id_forced(pdev->device)) { 1054 dev_info(&pdev->dev, 1055 "Your graphics device %04x is not officially supported\n" 1056 "by xe driver in this kernel version. To force Xe probe,\n" 1057 "use xe.force_probe='%04x' and i915.force_probe='!%04x'\n" 1058 "module parameters or CONFIG_DRM_XE_FORCE_PROBE='%04x' and\n" 1059 "CONFIG_DRM_I915_FORCE_PROBE='!%04x' configuration options.\n", 1060 pdev->device, pdev->device, pdev->device, 1061 pdev->device, pdev->device); 1062 return -ENODEV; 1063 } 1064 1065 if (id_blocked(pdev->device)) { 1066 dev_info(&pdev->dev, "Probe blocked for device [%04x:%04x].\n", 1067 pdev->vendor, pdev->device); 1068 return -ENODEV; 1069 } 1070 1071 if (xe_display_driver_probe_defer(pdev)) 1072 return -EPROBE_DEFER; 1073 1074 err = pcim_enable_device(pdev); 1075 if (err) 1076 return err; 1077 1078 xe = xe_device_create(pdev, ent); 1079 if (IS_ERR(xe)) 1080 return PTR_ERR(xe); 1081 1082 pci_set_drvdata(pdev, &xe->drm); 1083 1084 xe_pm_assert_unbounded_bridge(xe); 1085 subplatform_desc = find_subplatform(xe, desc); 1086 1087 pci_set_master(pdev); 1088 1089 err = xe_info_init_early(xe, desc, subplatform_desc); 1090 if (err) 1091 return err; 1092 1093 xe_pci_rebar_resize(xe); 1094 1095 err = xe_device_probe_early(xe); 1096 /* 1097 * In Boot Survivability mode, no drm card is exposed and driver 1098 * is loaded with bare minimum to allow for firmware to be 1099 * flashed through mei. Return success, if survivability mode 1100 * is enabled due to pcode failure or configfs being set 1101 */ 1102 if (xe_survivability_mode_is_boot_enabled(xe)) 1103 return 0; 1104 1105 if (err) 1106 return err; 1107 1108 err = xe_info_init(xe, desc); 1109 if (err) 1110 return err; 1111 1112 err = xe_display_probe(xe); 1113 if (err) 1114 return err; 1115 1116 drm_dbg(&xe->drm, "%s %s %04x:%04x dgfx:%d gfx:%s (%d.%02d) media:%s (%d.%02d) display:%s dma_m_s:%d tc:%d gscfi:%d cscfi:%d", 1117 desc->platform_name, 1118 subplatform_desc ? subplatform_desc->name : "", 1119 xe->info.devid, xe->info.revid, 1120 xe->info.is_dgfx, 1121 xe->info.graphics_name, 1122 xe->info.graphics_verx100 / 100, 1123 xe->info.graphics_verx100 % 100, 1124 xe->info.media_name, 1125 xe->info.media_verx100 / 100, 1126 xe->info.media_verx100 % 100, 1127 str_yes_no(xe->info.probe_display), 1128 xe->info.dma_mask_size, xe->info.tile_count, 1129 xe->info.has_heci_gscfi, xe->info.has_heci_cscfi); 1130 1131 drm_dbg(&xe->drm, "Stepping = (G:%s, M:%s, B:%s)\n", 1132 xe_step_name(xe->info.step.graphics), 1133 xe_step_name(xe->info.step.media), 1134 xe_step_name(xe->info.step.basedie)); 1135 1136 drm_dbg(&xe->drm, "SR-IOV support: %s (mode: %s)\n", 1137 str_yes_no(xe_device_has_sriov(xe)), 1138 xe_sriov_mode_to_string(xe_device_sriov_mode(xe))); 1139 1140 err = xe_pm_init_early(xe); 1141 if (err) 1142 return err; 1143 1144 err = xe_device_probe(xe); 1145 if (err) 1146 return err; 1147 1148 err = xe_pm_init(xe); 1149 if (err) 1150 goto err_driver_cleanup; 1151 1152 drm_dbg(&xe->drm, "d3cold: capable=%s\n", 1153 str_yes_no(xe->d3cold.capable)); 1154 1155 return 0; 1156 1157 err_driver_cleanup: 1158 xe_pci_remove(pdev); 1159 return err; 1160 } 1161 1162 static void xe_pci_shutdown(struct pci_dev *pdev) 1163 { 1164 xe_device_shutdown(pdev_to_xe_device(pdev)); 1165 } 1166 1167 #ifdef CONFIG_PM_SLEEP 1168 static void d3cold_toggle(struct pci_dev *pdev, enum toggle_d3cold toggle) 1169 { 1170 struct xe_device *xe = pdev_to_xe_device(pdev); 1171 struct pci_dev *root_pdev; 1172 1173 if (!xe->d3cold.capable) 1174 return; 1175 1176 root_pdev = pcie_find_root_port(pdev); 1177 if (!root_pdev) 1178 return; 1179 1180 switch (toggle) { 1181 case D3COLD_DISABLE: 1182 pci_d3cold_disable(root_pdev); 1183 break; 1184 case D3COLD_ENABLE: 1185 pci_d3cold_enable(root_pdev); 1186 break; 1187 } 1188 } 1189 1190 static int xe_pci_suspend(struct device *dev) 1191 { 1192 struct pci_dev *pdev = to_pci_dev(dev); 1193 struct xe_device *xe = pdev_to_xe_device(pdev); 1194 int err; 1195 1196 if (xe_survivability_mode_is_boot_enabled(xe)) 1197 return -EBUSY; 1198 1199 err = xe_pm_suspend(xe); 1200 if (err) 1201 return err; 1202 1203 /* 1204 * Enabling D3Cold is needed for S2Idle/S0ix. 1205 * It is save to allow here since xe_pm_suspend has evicted 1206 * the local memory and the direct complete optimization is disabled. 1207 */ 1208 d3cold_toggle(pdev, D3COLD_ENABLE); 1209 1210 pci_save_state(pdev); 1211 pci_disable_device(pdev); 1212 pci_set_power_state(pdev, PCI_D3cold); 1213 1214 return 0; 1215 } 1216 1217 static int xe_pci_resume(struct device *dev) 1218 { 1219 struct pci_dev *pdev = to_pci_dev(dev); 1220 int err; 1221 1222 /* Give back the D3Cold decision to the runtime P M*/ 1223 d3cold_toggle(pdev, D3COLD_DISABLE); 1224 1225 err = pci_set_power_state(pdev, PCI_D0); 1226 if (err) 1227 return err; 1228 1229 pci_restore_state(pdev); 1230 1231 err = pci_enable_device(pdev); 1232 if (err) 1233 return err; 1234 1235 pci_set_master(pdev); 1236 1237 err = xe_pm_resume(pdev_to_xe_device(pdev)); 1238 if (err) 1239 return err; 1240 1241 return 0; 1242 } 1243 1244 static int xe_pci_runtime_suspend(struct device *dev) 1245 { 1246 struct pci_dev *pdev = to_pci_dev(dev); 1247 struct xe_device *xe = pdev_to_xe_device(pdev); 1248 int err; 1249 1250 /* 1251 * We hold an additional reference to the runtime PM to keep PF in D0 1252 * during VFs lifetime, as our VFs do not implement the PM capability. 1253 * This means we should never be runtime suspending as long as VFs are 1254 * enabled. 1255 */ 1256 xe_assert(xe, !IS_SRIOV_VF(xe)); 1257 xe_assert(xe, !pci_num_vf(pdev)); 1258 1259 err = xe_pm_runtime_suspend(xe); 1260 if (err) 1261 return err; 1262 1263 pci_save_state(pdev); 1264 1265 if (xe->d3cold.allowed) { 1266 d3cold_toggle(pdev, D3COLD_ENABLE); 1267 pci_disable_device(pdev); 1268 pci_ignore_hotplug(pdev); 1269 pci_set_power_state(pdev, PCI_D3cold); 1270 } else { 1271 d3cold_toggle(pdev, D3COLD_DISABLE); 1272 pci_set_power_state(pdev, PCI_D3hot); 1273 } 1274 1275 return 0; 1276 } 1277 1278 static int xe_pci_runtime_resume(struct device *dev) 1279 { 1280 struct pci_dev *pdev = to_pci_dev(dev); 1281 struct xe_device *xe = pdev_to_xe_device(pdev); 1282 int err; 1283 1284 err = pci_set_power_state(pdev, PCI_D0); 1285 if (err) 1286 return err; 1287 1288 pci_restore_state(pdev); 1289 1290 if (xe->d3cold.allowed) { 1291 err = pci_enable_device(pdev); 1292 if (err) 1293 return err; 1294 1295 pci_set_master(pdev); 1296 } 1297 1298 return xe_pm_runtime_resume(xe); 1299 } 1300 1301 static int xe_pci_runtime_idle(struct device *dev) 1302 { 1303 struct pci_dev *pdev = to_pci_dev(dev); 1304 struct xe_device *xe = pdev_to_xe_device(pdev); 1305 1306 xe_pm_d3cold_allowed_toggle(xe); 1307 1308 return 0; 1309 } 1310 1311 static const struct dev_pm_ops xe_pm_ops = { 1312 SET_SYSTEM_SLEEP_PM_OPS(xe_pci_suspend, xe_pci_resume) 1313 SET_RUNTIME_PM_OPS(xe_pci_runtime_suspend, xe_pci_runtime_resume, xe_pci_runtime_idle) 1314 }; 1315 #endif 1316 1317 static struct pci_driver xe_pci_driver = { 1318 .name = DRIVER_NAME, 1319 .id_table = pciidlist, 1320 .probe = xe_pci_probe, 1321 .remove = xe_pci_remove, 1322 .shutdown = xe_pci_shutdown, 1323 .sriov_configure = xe_pci_sriov_configure, 1324 #ifdef CONFIG_PM_SLEEP 1325 .driver.pm = &xe_pm_ops, 1326 #endif 1327 }; 1328 1329 /** 1330 * xe_pci_to_pf_device() - Get PF &xe_device. 1331 * @pdev: the VF &pci_dev device 1332 * 1333 * Return: pointer to PF &xe_device, NULL otherwise. 1334 */ 1335 struct xe_device *xe_pci_to_pf_device(struct pci_dev *pdev) 1336 { 1337 struct drm_device *drm; 1338 1339 drm = pci_iov_get_pf_drvdata(pdev, &xe_pci_driver); 1340 if (IS_ERR(drm)) 1341 return NULL; 1342 1343 return to_xe_device(drm); 1344 } 1345 1346 int xe_register_pci_driver(void) 1347 { 1348 return pci_register_driver(&xe_pci_driver); 1349 } 1350 1351 void xe_unregister_pci_driver(void) 1352 { 1353 pci_unregister_driver(&xe_pci_driver); 1354 } 1355 1356 #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST) 1357 #include "tests/xe_pci.c" 1358 #endif 1359