1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 #include "xe_pci.h" 7 8 #include <kunit/static_stub.h> 9 #include <linux/device/driver.h> 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/pm_runtime.h> 13 14 #include <drm/drm_color_mgmt.h> 15 #include <drm/drm_drv.h> 16 #include <drm/intel/pciids.h> 17 18 #include "display/xe_display.h" 19 #include "regs/xe_gt_regs.h" 20 #include "regs/xe_regs.h" 21 #include "xe_configfs.h" 22 #include "xe_device.h" 23 #include "xe_drv.h" 24 #include "xe_gt.h" 25 #include "xe_gt_sriov_vf.h" 26 #include "xe_guc.h" 27 #include "xe_macros.h" 28 #include "xe_mmio.h" 29 #include "xe_module.h" 30 #include "xe_pci_sriov.h" 31 #include "xe_pci_types.h" 32 #include "xe_pm.h" 33 #include "xe_sriov.h" 34 #include "xe_step.h" 35 #include "xe_survivability_mode.h" 36 #include "xe_tile.h" 37 38 enum toggle_d3cold { 39 D3COLD_DISABLE, 40 D3COLD_ENABLE, 41 }; 42 43 __diag_push(); 44 __diag_ignore_all("-Woverride-init", "Allow field overrides in table"); 45 46 #define PLATFORM(x) \ 47 .platform = XE_##x, \ 48 .platform_name = #x 49 50 #define NOP(x) x 51 52 static const struct xe_graphics_desc graphics_xelp = { 53 .hw_engine_mask = BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0), 54 55 .va_bits = 48, 56 .vm_max_level = 3, 57 }; 58 59 #define XE_HP_FEATURES \ 60 .has_range_tlb_inval = true, \ 61 .va_bits = 48, \ 62 .vm_max_level = 3 63 64 static const struct xe_graphics_desc graphics_xehpg = { 65 .hw_engine_mask = 66 BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) | 67 BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) | 68 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3), 69 70 XE_HP_FEATURES, 71 .vram_flags = XE_VRAM_FLAGS_NEED64K, 72 73 .has_flat_ccs = 1, 74 }; 75 76 static const struct xe_graphics_desc graphics_xehpc = { 77 .hw_engine_mask = 78 BIT(XE_HW_ENGINE_BCS0) | BIT(XE_HW_ENGINE_BCS1) | 79 BIT(XE_HW_ENGINE_BCS2) | BIT(XE_HW_ENGINE_BCS3) | 80 BIT(XE_HW_ENGINE_BCS4) | BIT(XE_HW_ENGINE_BCS5) | 81 BIT(XE_HW_ENGINE_BCS6) | BIT(XE_HW_ENGINE_BCS7) | 82 BIT(XE_HW_ENGINE_BCS8) | 83 BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) | 84 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3), 85 86 XE_HP_FEATURES, 87 .va_bits = 57, 88 .vm_max_level = 4, 89 .vram_flags = XE_VRAM_FLAGS_NEED64K, 90 91 .has_asid = 1, 92 .has_atomic_enable_pte_bit = 1, 93 .has_usm = 1, 94 }; 95 96 static const struct xe_graphics_desc graphics_xelpg = { 97 .hw_engine_mask = 98 BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) | 99 BIT(XE_HW_ENGINE_CCS0), 100 101 XE_HP_FEATURES, 102 }; 103 104 #define XE2_GFX_FEATURES \ 105 .has_asid = 1, \ 106 .has_atomic_enable_pte_bit = 1, \ 107 .has_flat_ccs = 1, \ 108 .has_range_tlb_inval = 1, \ 109 .has_usm = 1, \ 110 .has_64bit_timestamp = 1, \ 111 .va_bits = 48, \ 112 .vm_max_level = 4, \ 113 .hw_engine_mask = \ 114 BIT(XE_HW_ENGINE_RCS0) | \ 115 BIT(XE_HW_ENGINE_BCS8) | BIT(XE_HW_ENGINE_BCS0) | \ 116 GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0) 117 118 static const struct xe_graphics_desc graphics_xe2 = { 119 XE2_GFX_FEATURES, 120 }; 121 122 static const struct xe_media_desc media_xem = { 123 .hw_engine_mask = 124 GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) | 125 GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0), 126 }; 127 128 static const struct xe_media_desc media_xelpmp = { 129 .hw_engine_mask = 130 GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) | 131 GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0) | 132 BIT(XE_HW_ENGINE_GSCCS0) 133 }; 134 135 /* Pre-GMDID Graphics IPs */ 136 static const struct xe_ip graphics_ip_xelp = { 1200, "Xe_LP", &graphics_xelp }; 137 static const struct xe_ip graphics_ip_xelpp = { 1210, "Xe_LP+", &graphics_xelp }; 138 static const struct xe_ip graphics_ip_xehpg = { 1255, "Xe_HPG", &graphics_xehpg }; 139 static const struct xe_ip graphics_ip_xehpc = { 1260, "Xe_HPC", &graphics_xehpc }; 140 141 /* GMDID-based Graphics IPs */ 142 static const struct xe_ip graphics_ips[] = { 143 { 1270, "Xe_LPG", &graphics_xelpg }, 144 { 1271, "Xe_LPG", &graphics_xelpg }, 145 { 1274, "Xe_LPG+", &graphics_xelpg }, 146 { 2001, "Xe2_HPG", &graphics_xe2 }, 147 { 2002, "Xe2_HPG", &graphics_xe2 }, 148 { 2004, "Xe2_LPG", &graphics_xe2 }, 149 { 3000, "Xe3_LPG", &graphics_xe2 }, 150 { 3001, "Xe3_LPG", &graphics_xe2 }, 151 { 3003, "Xe3_LPG", &graphics_xe2 }, 152 }; 153 154 /* Pre-GMDID Media IPs */ 155 static const struct xe_ip media_ip_xem = { 1200, "Xe_M", &media_xem }; 156 static const struct xe_ip media_ip_xehpm = { 1255, "Xe_HPM", &media_xem }; 157 158 /* GMDID-based Media IPs */ 159 static const struct xe_ip media_ips[] = { 160 { 1300, "Xe_LPM+", &media_xelpmp }, 161 { 1301, "Xe2_HPM", &media_xelpmp }, 162 { 2000, "Xe2_LPM", &media_xelpmp }, 163 { 3000, "Xe3_LPM", &media_xelpmp }, 164 { 3002, "Xe3_LPM", &media_xelpmp }, 165 }; 166 167 static const struct xe_device_desc tgl_desc = { 168 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 169 .pre_gmdid_media_ip = &media_ip_xem, 170 PLATFORM(TIGERLAKE), 171 .dma_mask_size = 39, 172 .has_display = true, 173 .has_llc = true, 174 .has_sriov = true, 175 .max_gt_per_tile = 1, 176 .require_force_probe = true, 177 }; 178 179 static const struct xe_device_desc rkl_desc = { 180 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 181 .pre_gmdid_media_ip = &media_ip_xem, 182 PLATFORM(ROCKETLAKE), 183 .dma_mask_size = 39, 184 .has_display = true, 185 .has_llc = true, 186 .max_gt_per_tile = 1, 187 .require_force_probe = true, 188 }; 189 190 static const u16 adls_rpls_ids[] = { INTEL_RPLS_IDS(NOP), 0 }; 191 192 static const struct xe_device_desc adl_s_desc = { 193 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 194 .pre_gmdid_media_ip = &media_ip_xem, 195 PLATFORM(ALDERLAKE_S), 196 .dma_mask_size = 39, 197 .has_display = true, 198 .has_llc = true, 199 .has_sriov = true, 200 .max_gt_per_tile = 1, 201 .require_force_probe = true, 202 .subplatforms = (const struct xe_subplatform_desc[]) { 203 { XE_SUBPLATFORM_ALDERLAKE_S_RPLS, "RPLS", adls_rpls_ids }, 204 {}, 205 }, 206 }; 207 208 static const u16 adlp_rplu_ids[] = { INTEL_RPLU_IDS(NOP), 0 }; 209 210 static const struct xe_device_desc adl_p_desc = { 211 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 212 .pre_gmdid_media_ip = &media_ip_xem, 213 PLATFORM(ALDERLAKE_P), 214 .dma_mask_size = 39, 215 .has_display = true, 216 .has_llc = true, 217 .has_sriov = true, 218 .max_gt_per_tile = 1, 219 .require_force_probe = true, 220 .subplatforms = (const struct xe_subplatform_desc[]) { 221 { XE_SUBPLATFORM_ALDERLAKE_P_RPLU, "RPLU", adlp_rplu_ids }, 222 {}, 223 }, 224 }; 225 226 static const struct xe_device_desc adl_n_desc = { 227 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 228 .pre_gmdid_media_ip = &media_ip_xem, 229 PLATFORM(ALDERLAKE_N), 230 .dma_mask_size = 39, 231 .has_display = true, 232 .has_llc = true, 233 .has_sriov = true, 234 .max_gt_per_tile = 1, 235 .require_force_probe = true, 236 }; 237 238 #define DGFX_FEATURES \ 239 .is_dgfx = 1 240 241 static const struct xe_device_desc dg1_desc = { 242 .pre_gmdid_graphics_ip = &graphics_ip_xelpp, 243 .pre_gmdid_media_ip = &media_ip_xem, 244 DGFX_FEATURES, 245 PLATFORM(DG1), 246 .dma_mask_size = 39, 247 .has_display = true, 248 .has_gsc_nvm = 1, 249 .has_heci_gscfi = 1, 250 .max_gt_per_tile = 1, 251 .require_force_probe = true, 252 }; 253 254 static const u16 dg2_g10_ids[] = { INTEL_DG2_G10_IDS(NOP), INTEL_ATS_M150_IDS(NOP), 0 }; 255 static const u16 dg2_g11_ids[] = { INTEL_DG2_G11_IDS(NOP), INTEL_ATS_M75_IDS(NOP), 0 }; 256 static const u16 dg2_g12_ids[] = { INTEL_DG2_G12_IDS(NOP), 0 }; 257 258 #define DG2_FEATURES \ 259 DGFX_FEATURES, \ 260 PLATFORM(DG2), \ 261 .has_gsc_nvm = 1, \ 262 .has_heci_gscfi = 1, \ 263 .subplatforms = (const struct xe_subplatform_desc[]) { \ 264 { XE_SUBPLATFORM_DG2_G10, "G10", dg2_g10_ids }, \ 265 { XE_SUBPLATFORM_DG2_G11, "G11", dg2_g11_ids }, \ 266 { XE_SUBPLATFORM_DG2_G12, "G12", dg2_g12_ids }, \ 267 { } \ 268 } 269 270 static const struct xe_device_desc ats_m_desc = { 271 .pre_gmdid_graphics_ip = &graphics_ip_xehpg, 272 .pre_gmdid_media_ip = &media_ip_xehpm, 273 .dma_mask_size = 46, 274 .max_gt_per_tile = 1, 275 .require_force_probe = true, 276 277 DG2_FEATURES, 278 .has_display = false, 279 .has_sriov = true, 280 }; 281 282 static const struct xe_device_desc dg2_desc = { 283 .pre_gmdid_graphics_ip = &graphics_ip_xehpg, 284 .pre_gmdid_media_ip = &media_ip_xehpm, 285 .dma_mask_size = 46, 286 .max_gt_per_tile = 1, 287 .require_force_probe = true, 288 289 DG2_FEATURES, 290 .has_display = true, 291 .has_fan_control = true, 292 .has_mbx_power_limits = false, 293 }; 294 295 static const __maybe_unused struct xe_device_desc pvc_desc = { 296 .pre_gmdid_graphics_ip = &graphics_ip_xehpc, 297 DGFX_FEATURES, 298 PLATFORM(PVC), 299 .dma_mask_size = 52, 300 .has_display = false, 301 .has_gsc_nvm = 1, 302 .has_heci_gscfi = 1, 303 .max_gt_per_tile = 1, 304 .max_remote_tiles = 1, 305 .require_force_probe = true, 306 .has_mbx_power_limits = false, 307 }; 308 309 static const struct xe_device_desc mtl_desc = { 310 /* .graphics and .media determined via GMD_ID */ 311 .require_force_probe = true, 312 PLATFORM(METEORLAKE), 313 .dma_mask_size = 46, 314 .has_display = true, 315 .has_pxp = true, 316 .max_gt_per_tile = 2, 317 }; 318 319 static const struct xe_device_desc lnl_desc = { 320 PLATFORM(LUNARLAKE), 321 .dma_mask_size = 46, 322 .has_display = true, 323 .has_pxp = true, 324 .max_gt_per_tile = 2, 325 .needs_scratch = true, 326 }; 327 328 static const struct xe_device_desc bmg_desc = { 329 DGFX_FEATURES, 330 PLATFORM(BATTLEMAGE), 331 .dma_mask_size = 46, 332 .has_display = true, 333 .has_fan_control = true, 334 .has_mbx_power_limits = true, 335 .has_gsc_nvm = 1, 336 .has_heci_cscfi = 1, 337 .has_sriov = true, 338 .max_gt_per_tile = 2, 339 .needs_scratch = true, 340 }; 341 342 static const struct xe_device_desc ptl_desc = { 343 PLATFORM(PANTHERLAKE), 344 .dma_mask_size = 46, 345 .has_display = true, 346 .has_sriov = true, 347 .max_gt_per_tile = 2, 348 .needs_scratch = true, 349 }; 350 351 #undef PLATFORM 352 __diag_pop(); 353 354 /* 355 * Make sure any device matches here are from most specific to most 356 * general. For example, since the Quanta match is based on the subsystem 357 * and subvendor IDs, we need it to come before the more general IVB 358 * PCI ID matches, otherwise we'll use the wrong info struct above. 359 */ 360 static const struct pci_device_id pciidlist[] = { 361 INTEL_TGL_IDS(INTEL_VGA_DEVICE, &tgl_desc), 362 INTEL_RKL_IDS(INTEL_VGA_DEVICE, &rkl_desc), 363 INTEL_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc), 364 INTEL_ADLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 365 INTEL_ADLN_IDS(INTEL_VGA_DEVICE, &adl_n_desc), 366 INTEL_RPLU_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 367 INTEL_RPLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 368 INTEL_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc), 369 INTEL_DG1_IDS(INTEL_VGA_DEVICE, &dg1_desc), 370 INTEL_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_desc), 371 INTEL_ARL_IDS(INTEL_VGA_DEVICE, &mtl_desc), 372 INTEL_DG2_IDS(INTEL_VGA_DEVICE, &dg2_desc), 373 INTEL_MTL_IDS(INTEL_VGA_DEVICE, &mtl_desc), 374 INTEL_LNL_IDS(INTEL_VGA_DEVICE, &lnl_desc), 375 INTEL_BMG_IDS(INTEL_VGA_DEVICE, &bmg_desc), 376 INTEL_PTL_IDS(INTEL_VGA_DEVICE, &ptl_desc), 377 { } 378 }; 379 MODULE_DEVICE_TABLE(pci, pciidlist); 380 381 /* is device_id present in comma separated list of ids */ 382 static bool device_id_in_list(u16 device_id, const char *devices, bool negative) 383 { 384 char *s, *p, *tok; 385 bool ret; 386 387 if (!devices || !*devices) 388 return false; 389 390 /* match everything */ 391 if (negative && strcmp(devices, "!*") == 0) 392 return true; 393 if (!negative && strcmp(devices, "*") == 0) 394 return true; 395 396 s = kstrdup(devices, GFP_KERNEL); 397 if (!s) 398 return false; 399 400 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) { 401 u16 val; 402 403 if (negative && tok[0] == '!') 404 tok++; 405 else if ((negative && tok[0] != '!') || 406 (!negative && tok[0] == '!')) 407 continue; 408 409 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) { 410 ret = true; 411 break; 412 } 413 } 414 415 kfree(s); 416 417 return ret; 418 } 419 420 static bool id_forced(u16 device_id) 421 { 422 return device_id_in_list(device_id, xe_modparam.force_probe, false); 423 } 424 425 static bool id_blocked(u16 device_id) 426 { 427 return device_id_in_list(device_id, xe_modparam.force_probe, true); 428 } 429 430 static const struct xe_subplatform_desc * 431 find_subplatform(const struct xe_device *xe, const struct xe_device_desc *desc) 432 { 433 const struct xe_subplatform_desc *sp; 434 const u16 *id; 435 436 for (sp = desc->subplatforms; sp && sp->subplatform; sp++) 437 for (id = sp->pciidlist; *id; id++) 438 if (*id == xe->info.devid) 439 return sp; 440 441 return NULL; 442 } 443 444 enum xe_gmdid_type { 445 GMDID_GRAPHICS, 446 GMDID_MEDIA 447 }; 448 449 static void read_gmdid(struct xe_device *xe, enum xe_gmdid_type type, u32 *ver, u32 *revid) 450 { 451 struct xe_mmio *mmio = xe_root_tile_mmio(xe); 452 struct xe_reg gmdid_reg = GMD_ID; 453 u32 val; 454 455 KUNIT_STATIC_STUB_REDIRECT(read_gmdid, xe, type, ver, revid); 456 457 if (IS_SRIOV_VF(xe)) { 458 struct xe_gt *gt = xe_root_mmio_gt(xe); 459 460 /* 461 * To get the value of the GMDID register, VFs must obtain it 462 * from the GuC using MMIO communication. 463 * 464 * Note that at this point the xe_gt is not fully uninitialized 465 * and only basic access to MMIO registers is possible. To use 466 * our existing GuC communication functions we must perform at 467 * least basic xe_gt and xe_guc initialization. 468 * 469 * Since to obtain the value of GMDID_MEDIA we need to use the 470 * media GuC, temporarily tweak the gt type. 471 */ 472 xe_gt_assert(gt, gt->info.type == XE_GT_TYPE_UNINITIALIZED); 473 474 if (type == GMDID_MEDIA) { 475 gt->info.id = 1; 476 gt->info.type = XE_GT_TYPE_MEDIA; 477 } else { 478 gt->info.id = 0; 479 gt->info.type = XE_GT_TYPE_MAIN; 480 } 481 482 xe_gt_mmio_init(gt); 483 xe_guc_comm_init_early(>->uc.guc); 484 485 /* Don't bother with GMDID if failed to negotiate the GuC ABI */ 486 val = xe_gt_sriov_vf_bootstrap(gt) ? 0 : xe_gt_sriov_vf_gmdid(gt); 487 488 /* 489 * Only undo xe_gt.info here, the remaining changes made above 490 * will be overwritten as part of the regular initialization. 491 */ 492 gt->info.id = 0; 493 gt->info.type = XE_GT_TYPE_UNINITIALIZED; 494 } else { 495 /* 496 * GMD_ID is a GT register, but at this point in the driver 497 * init we haven't fully initialized the GT yet so we need to 498 * read the register with the tile's MMIO accessor. That means 499 * we need to apply the GSI offset manually since it won't get 500 * automatically added as it would if we were using a GT mmio 501 * accessor. 502 */ 503 if (type == GMDID_MEDIA) 504 gmdid_reg.addr += MEDIA_GT_GSI_OFFSET; 505 506 val = xe_mmio_read32(mmio, gmdid_reg); 507 } 508 509 *ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val) * 100 + REG_FIELD_GET(GMD_ID_RELEASE_MASK, val); 510 *revid = REG_FIELD_GET(GMD_ID_REVID, val); 511 } 512 513 /* 514 * Read IP version from hardware and select graphics/media IP descriptors 515 * based on the result. 516 */ 517 static void handle_gmdid(struct xe_device *xe, 518 const struct xe_ip **graphics_ip, 519 const struct xe_ip **media_ip, 520 u32 *graphics_revid, 521 u32 *media_revid) 522 { 523 u32 ver; 524 525 *graphics_ip = NULL; 526 *media_ip = NULL; 527 528 read_gmdid(xe, GMDID_GRAPHICS, &ver, graphics_revid); 529 530 for (int i = 0; i < ARRAY_SIZE(graphics_ips); i++) { 531 if (ver == graphics_ips[i].verx100) { 532 *graphics_ip = &graphics_ips[i]; 533 534 break; 535 } 536 } 537 538 if (!*graphics_ip) { 539 drm_err(&xe->drm, "Hardware reports unknown graphics version %u.%02u\n", 540 ver / 100, ver % 100); 541 } 542 543 read_gmdid(xe, GMDID_MEDIA, &ver, media_revid); 544 /* Media may legitimately be fused off / not present */ 545 if (ver == 0) 546 return; 547 548 for (int i = 0; i < ARRAY_SIZE(media_ips); i++) { 549 if (ver == media_ips[i].verx100) { 550 *media_ip = &media_ips[i]; 551 552 break; 553 } 554 } 555 556 if (!*media_ip) { 557 drm_err(&xe->drm, "Hardware reports unknown media version %u.%02u\n", 558 ver / 100, ver % 100); 559 } 560 } 561 562 /* 563 * Initialize device info content that only depends on static driver_data 564 * passed to the driver at probe time from PCI ID table. 565 */ 566 static int xe_info_init_early(struct xe_device *xe, 567 const struct xe_device_desc *desc, 568 const struct xe_subplatform_desc *subplatform_desc) 569 { 570 int err; 571 572 xe->info.platform_name = desc->platform_name; 573 xe->info.platform = desc->platform; 574 xe->info.subplatform = subplatform_desc ? 575 subplatform_desc->subplatform : XE_SUBPLATFORM_NONE; 576 577 xe->info.dma_mask_size = desc->dma_mask_size; 578 xe->info.is_dgfx = desc->is_dgfx; 579 xe->info.has_fan_control = desc->has_fan_control; 580 xe->info.has_mbx_power_limits = desc->has_mbx_power_limits; 581 xe->info.has_gsc_nvm = desc->has_gsc_nvm; 582 xe->info.has_heci_gscfi = desc->has_heci_gscfi; 583 xe->info.has_heci_cscfi = desc->has_heci_cscfi; 584 xe->info.has_llc = desc->has_llc; 585 xe->info.has_pxp = desc->has_pxp; 586 xe->info.has_sriov = desc->has_sriov; 587 xe->info.skip_guc_pc = desc->skip_guc_pc; 588 xe->info.skip_mtcfg = desc->skip_mtcfg; 589 xe->info.skip_pcode = desc->skip_pcode; 590 xe->info.needs_scratch = desc->needs_scratch; 591 592 xe->info.probe_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) && 593 xe_modparam.probe_display && 594 desc->has_display; 595 596 xe_assert(xe, desc->max_gt_per_tile > 0); 597 xe_assert(xe, desc->max_gt_per_tile <= XE_MAX_GT_PER_TILE); 598 xe->info.max_gt_per_tile = desc->max_gt_per_tile; 599 xe->info.tile_count = 1 + desc->max_remote_tiles; 600 601 err = xe_tile_init_early(xe_device_get_root_tile(xe), xe, 0); 602 if (err) 603 return err; 604 605 return 0; 606 } 607 608 /* 609 * Possibly override number of tile based on configuration register. 610 */ 611 static void xe_info_probe_tile_count(struct xe_device *xe) 612 { 613 struct xe_mmio *mmio; 614 u8 tile_count; 615 u32 mtcfg; 616 617 KUNIT_STATIC_STUB_REDIRECT(xe_info_probe_tile_count, xe); 618 619 /* 620 * Probe for tile count only for platforms that support multiple 621 * tiles. 622 */ 623 if (xe->info.tile_count == 1) 624 return; 625 626 if (xe->info.skip_mtcfg) 627 return; 628 629 mmio = xe_root_tile_mmio(xe); 630 631 /* 632 * Although the per-tile mmio regs are not yet initialized, this 633 * is fine as it's going to the root tile's mmio, that's 634 * guaranteed to be initialized earlier in xe_mmio_probe_early() 635 */ 636 mtcfg = xe_mmio_read32(mmio, XEHP_MTCFG_ADDR); 637 tile_count = REG_FIELD_GET(TILE_COUNT, mtcfg) + 1; 638 639 if (tile_count < xe->info.tile_count) { 640 drm_info(&xe->drm, "tile_count: %d, reduced_tile_count %d\n", 641 xe->info.tile_count, tile_count); 642 xe->info.tile_count = tile_count; 643 } 644 } 645 646 /* 647 * Initialize device info content that does require knowledge about 648 * graphics / media IP version. 649 * Make sure that GT / tile structures allocated by the driver match the data 650 * present in device info. 651 */ 652 static int xe_info_init(struct xe_device *xe, 653 const struct xe_device_desc *desc) 654 { 655 u32 graphics_gmdid_revid = 0, media_gmdid_revid = 0; 656 const struct xe_ip *graphics_ip; 657 const struct xe_ip *media_ip; 658 const struct xe_graphics_desc *graphics_desc; 659 const struct xe_media_desc *media_desc; 660 struct xe_tile *tile; 661 struct xe_gt *gt; 662 u8 id; 663 664 /* 665 * If this platform supports GMD_ID, we'll detect the proper IP 666 * descriptor to use from hardware registers. 667 * desc->pre_gmdid_graphics_ip will only ever be set at this point for 668 * platforms before GMD_ID. In that case the IP descriptions and 669 * versions are simply derived from that. 670 */ 671 if (desc->pre_gmdid_graphics_ip) { 672 graphics_ip = desc->pre_gmdid_graphics_ip; 673 media_ip = desc->pre_gmdid_media_ip; 674 xe->info.step = xe_step_pre_gmdid_get(xe); 675 } else { 676 xe_assert(xe, !desc->pre_gmdid_media_ip); 677 handle_gmdid(xe, &graphics_ip, &media_ip, 678 &graphics_gmdid_revid, &media_gmdid_revid); 679 xe->info.step = xe_step_gmdid_get(xe, 680 graphics_gmdid_revid, 681 media_gmdid_revid); 682 } 683 684 /* 685 * If we couldn't detect the graphics IP, that's considered a fatal 686 * error and we should abort driver load. Failing to detect media 687 * IP is non-fatal; we'll just proceed without enabling media support. 688 */ 689 if (!graphics_ip) 690 return -ENODEV; 691 692 xe->info.graphics_verx100 = graphics_ip->verx100; 693 xe->info.graphics_name = graphics_ip->name; 694 graphics_desc = graphics_ip->desc; 695 696 if (media_ip) { 697 xe->info.media_verx100 = media_ip->verx100; 698 xe->info.media_name = media_ip->name; 699 media_desc = media_ip->desc; 700 } else { 701 xe->info.media_name = "none"; 702 media_desc = NULL; 703 } 704 705 xe->info.vram_flags = graphics_desc->vram_flags; 706 xe->info.va_bits = graphics_desc->va_bits; 707 xe->info.vm_max_level = graphics_desc->vm_max_level; 708 xe->info.has_asid = graphics_desc->has_asid; 709 xe->info.has_atomic_enable_pte_bit = graphics_desc->has_atomic_enable_pte_bit; 710 if (xe->info.platform != XE_PVC) 711 xe->info.has_device_atomics_on_smem = 1; 712 713 /* Runtime detection may change this later */ 714 xe->info.has_flat_ccs = graphics_desc->has_flat_ccs; 715 716 xe->info.has_range_tlb_inval = graphics_desc->has_range_tlb_inval; 717 xe->info.has_usm = graphics_desc->has_usm; 718 xe->info.has_64bit_timestamp = graphics_desc->has_64bit_timestamp; 719 720 xe_info_probe_tile_count(xe); 721 722 for_each_remote_tile(tile, xe, id) { 723 int err; 724 725 err = xe_tile_init_early(tile, xe, id); 726 if (err) 727 return err; 728 } 729 730 /* 731 * All platforms have at least one primary GT. Any platform with media 732 * version 13 or higher has an additional dedicated media GT. And 733 * depending on the graphics IP there may be additional "remote tiles." 734 * All of these together determine the overall GT count. 735 */ 736 for_each_tile(tile, xe, id) { 737 int err; 738 739 gt = tile->primary_gt; 740 gt->info.type = XE_GT_TYPE_MAIN; 741 gt->info.id = tile->id * xe->info.max_gt_per_tile; 742 gt->info.has_indirect_ring_state = graphics_desc->has_indirect_ring_state; 743 gt->info.engine_mask = graphics_desc->hw_engine_mask; 744 745 err = xe_tile_alloc_vram(tile); 746 if (err) 747 return err; 748 749 if (MEDIA_VER(xe) < 13 && media_desc) 750 gt->info.engine_mask |= media_desc->hw_engine_mask; 751 752 if (MEDIA_VER(xe) < 13 || !media_desc) 753 continue; 754 755 /* 756 * Allocate and setup media GT for platforms with standalone 757 * media. 758 */ 759 tile->media_gt = xe_gt_alloc(tile); 760 if (IS_ERR(tile->media_gt)) 761 return PTR_ERR(tile->media_gt); 762 763 gt = tile->media_gt; 764 gt->info.type = XE_GT_TYPE_MEDIA; 765 gt->info.id = tile->id * xe->info.max_gt_per_tile + 1; 766 gt->info.has_indirect_ring_state = media_desc->has_indirect_ring_state; 767 gt->info.engine_mask = media_desc->hw_engine_mask; 768 } 769 770 /* 771 * Now that we have tiles and GTs defined, let's loop over valid GTs 772 * in order to define gt_count. 773 */ 774 for_each_gt(gt, xe, id) 775 xe->info.gt_count++; 776 777 return 0; 778 } 779 780 static void xe_pci_remove(struct pci_dev *pdev) 781 { 782 struct xe_device *xe = pdev_to_xe_device(pdev); 783 784 if (IS_SRIOV_PF(xe)) 785 xe_pci_sriov_configure(pdev, 0); 786 787 if (xe_survivability_mode_is_boot_enabled(xe)) 788 return; 789 790 xe_device_remove(xe); 791 xe_pm_fini(xe); 792 } 793 794 /* 795 * Probe the PCI device, initialize various parts of the driver. 796 * 797 * Fault injection is used to test the error paths of some initialization 798 * functions called either directly from xe_pci_probe() or indirectly for 799 * example through xe_device_probe(). Those functions use the kernel fault 800 * injection capabilities infrastructure, see 801 * Documentation/fault-injection/fault-injection.rst for details. The macro 802 * ALLOW_ERROR_INJECTION() is used to conditionally skip function execution 803 * at runtime and use a provided return value. The first requirement for 804 * error injectable functions is proper handling of the error code by the 805 * caller for recovery, which is always the case here. The second 806 * requirement is that no state is changed before the first error return. 807 * It is not strictly fulfilled for all initialization functions using the 808 * ALLOW_ERROR_INJECTION() macro but this is acceptable because for those 809 * error cases at probe time, the error code is simply propagated up by the 810 * caller. Therefore there is no consequence on those specific callers when 811 * function error injection skips the whole function. 812 */ 813 static int xe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 814 { 815 const struct xe_device_desc *desc = (const void *)ent->driver_data; 816 const struct xe_subplatform_desc *subplatform_desc; 817 struct xe_device *xe; 818 int err; 819 820 xe_configfs_check_device(pdev); 821 822 if (desc->require_force_probe && !id_forced(pdev->device)) { 823 dev_info(&pdev->dev, 824 "Your graphics device %04x is not officially supported\n" 825 "by xe driver in this kernel version. To force Xe probe,\n" 826 "use xe.force_probe='%04x' and i915.force_probe='!%04x'\n" 827 "module parameters or CONFIG_DRM_XE_FORCE_PROBE='%04x' and\n" 828 "CONFIG_DRM_I915_FORCE_PROBE='!%04x' configuration options.\n", 829 pdev->device, pdev->device, pdev->device, 830 pdev->device, pdev->device); 831 return -ENODEV; 832 } 833 834 if (id_blocked(pdev->device)) { 835 dev_info(&pdev->dev, "Probe blocked for device [%04x:%04x].\n", 836 pdev->vendor, pdev->device); 837 return -ENODEV; 838 } 839 840 if (xe_display_driver_probe_defer(pdev)) 841 return -EPROBE_DEFER; 842 843 err = pcim_enable_device(pdev); 844 if (err) 845 return err; 846 847 xe = xe_device_create(pdev, ent); 848 if (IS_ERR(xe)) 849 return PTR_ERR(xe); 850 851 pci_set_drvdata(pdev, &xe->drm); 852 853 xe_pm_assert_unbounded_bridge(xe); 854 subplatform_desc = find_subplatform(xe, desc); 855 856 pci_set_master(pdev); 857 858 err = xe_info_init_early(xe, desc, subplatform_desc); 859 if (err) 860 return err; 861 862 err = xe_device_probe_early(xe); 863 /* 864 * In Boot Survivability mode, no drm card is exposed and driver 865 * is loaded with bare minimum to allow for firmware to be 866 * flashed through mei. Return success, if survivability mode 867 * is enabled due to pcode failure or configfs being set 868 */ 869 if (xe_survivability_mode_is_boot_enabled(xe)) 870 return 0; 871 872 if (err) 873 return err; 874 875 err = xe_info_init(xe, desc); 876 if (err) 877 return err; 878 879 err = xe_display_probe(xe); 880 if (err) 881 return err; 882 883 drm_dbg(&xe->drm, "%s %s %04x:%04x dgfx:%d gfx:%s (%d.%02d) media:%s (%d.%02d) display:%s dma_m_s:%d tc:%d gscfi:%d cscfi:%d", 884 desc->platform_name, 885 subplatform_desc ? subplatform_desc->name : "", 886 xe->info.devid, xe->info.revid, 887 xe->info.is_dgfx, 888 xe->info.graphics_name, 889 xe->info.graphics_verx100 / 100, 890 xe->info.graphics_verx100 % 100, 891 xe->info.media_name, 892 xe->info.media_verx100 / 100, 893 xe->info.media_verx100 % 100, 894 str_yes_no(xe->info.probe_display), 895 xe->info.dma_mask_size, xe->info.tile_count, 896 xe->info.has_heci_gscfi, xe->info.has_heci_cscfi); 897 898 drm_dbg(&xe->drm, "Stepping = (G:%s, M:%s, B:%s)\n", 899 xe_step_name(xe->info.step.graphics), 900 xe_step_name(xe->info.step.media), 901 xe_step_name(xe->info.step.basedie)); 902 903 drm_dbg(&xe->drm, "SR-IOV support: %s (mode: %s)\n", 904 str_yes_no(xe_device_has_sriov(xe)), 905 xe_sriov_mode_to_string(xe_device_sriov_mode(xe))); 906 907 err = xe_pm_init_early(xe); 908 if (err) 909 return err; 910 911 err = xe_device_probe(xe); 912 if (err) 913 return err; 914 915 err = xe_pm_init(xe); 916 if (err) 917 goto err_driver_cleanup; 918 919 drm_dbg(&xe->drm, "d3cold: capable=%s\n", 920 str_yes_no(xe->d3cold.capable)); 921 922 return 0; 923 924 err_driver_cleanup: 925 xe_pci_remove(pdev); 926 return err; 927 } 928 929 static void xe_pci_shutdown(struct pci_dev *pdev) 930 { 931 xe_device_shutdown(pdev_to_xe_device(pdev)); 932 } 933 934 #ifdef CONFIG_PM_SLEEP 935 static void d3cold_toggle(struct pci_dev *pdev, enum toggle_d3cold toggle) 936 { 937 struct xe_device *xe = pdev_to_xe_device(pdev); 938 struct pci_dev *root_pdev; 939 940 if (!xe->d3cold.capable) 941 return; 942 943 root_pdev = pcie_find_root_port(pdev); 944 if (!root_pdev) 945 return; 946 947 switch (toggle) { 948 case D3COLD_DISABLE: 949 pci_d3cold_disable(root_pdev); 950 break; 951 case D3COLD_ENABLE: 952 pci_d3cold_enable(root_pdev); 953 break; 954 } 955 } 956 957 static int xe_pci_suspend(struct device *dev) 958 { 959 struct pci_dev *pdev = to_pci_dev(dev); 960 struct xe_device *xe = pdev_to_xe_device(pdev); 961 int err; 962 963 if (xe_survivability_mode_is_boot_enabled(xe)) 964 return -EBUSY; 965 966 err = xe_pm_suspend(xe); 967 if (err) 968 return err; 969 970 /* 971 * Enabling D3Cold is needed for S2Idle/S0ix. 972 * It is save to allow here since xe_pm_suspend has evicted 973 * the local memory and the direct complete optimization is disabled. 974 */ 975 d3cold_toggle(pdev, D3COLD_ENABLE); 976 977 pci_save_state(pdev); 978 pci_disable_device(pdev); 979 pci_set_power_state(pdev, PCI_D3cold); 980 981 return 0; 982 } 983 984 static int xe_pci_resume(struct device *dev) 985 { 986 struct pci_dev *pdev = to_pci_dev(dev); 987 int err; 988 989 /* Give back the D3Cold decision to the runtime P M*/ 990 d3cold_toggle(pdev, D3COLD_DISABLE); 991 992 err = pci_set_power_state(pdev, PCI_D0); 993 if (err) 994 return err; 995 996 pci_restore_state(pdev); 997 998 err = pci_enable_device(pdev); 999 if (err) 1000 return err; 1001 1002 pci_set_master(pdev); 1003 1004 err = xe_pm_resume(pdev_to_xe_device(pdev)); 1005 if (err) 1006 return err; 1007 1008 return 0; 1009 } 1010 1011 static int xe_pci_runtime_suspend(struct device *dev) 1012 { 1013 struct pci_dev *pdev = to_pci_dev(dev); 1014 struct xe_device *xe = pdev_to_xe_device(pdev); 1015 int err; 1016 1017 err = xe_pm_runtime_suspend(xe); 1018 if (err) 1019 return err; 1020 1021 pci_save_state(pdev); 1022 1023 if (xe->d3cold.allowed) { 1024 d3cold_toggle(pdev, D3COLD_ENABLE); 1025 pci_disable_device(pdev); 1026 pci_ignore_hotplug(pdev); 1027 pci_set_power_state(pdev, PCI_D3cold); 1028 } else { 1029 d3cold_toggle(pdev, D3COLD_DISABLE); 1030 pci_set_power_state(pdev, PCI_D3hot); 1031 } 1032 1033 return 0; 1034 } 1035 1036 static int xe_pci_runtime_resume(struct device *dev) 1037 { 1038 struct pci_dev *pdev = to_pci_dev(dev); 1039 struct xe_device *xe = pdev_to_xe_device(pdev); 1040 int err; 1041 1042 err = pci_set_power_state(pdev, PCI_D0); 1043 if (err) 1044 return err; 1045 1046 pci_restore_state(pdev); 1047 1048 if (xe->d3cold.allowed) { 1049 err = pci_enable_device(pdev); 1050 if (err) 1051 return err; 1052 1053 pci_set_master(pdev); 1054 } 1055 1056 return xe_pm_runtime_resume(xe); 1057 } 1058 1059 static int xe_pci_runtime_idle(struct device *dev) 1060 { 1061 struct pci_dev *pdev = to_pci_dev(dev); 1062 struct xe_device *xe = pdev_to_xe_device(pdev); 1063 1064 xe_pm_d3cold_allowed_toggle(xe); 1065 1066 return 0; 1067 } 1068 1069 static const struct dev_pm_ops xe_pm_ops = { 1070 SET_SYSTEM_SLEEP_PM_OPS(xe_pci_suspend, xe_pci_resume) 1071 SET_RUNTIME_PM_OPS(xe_pci_runtime_suspend, xe_pci_runtime_resume, xe_pci_runtime_idle) 1072 }; 1073 #endif 1074 1075 static struct pci_driver xe_pci_driver = { 1076 .name = DRIVER_NAME, 1077 .id_table = pciidlist, 1078 .probe = xe_pci_probe, 1079 .remove = xe_pci_remove, 1080 .shutdown = xe_pci_shutdown, 1081 .sriov_configure = xe_pci_sriov_configure, 1082 #ifdef CONFIG_PM_SLEEP 1083 .driver.pm = &xe_pm_ops, 1084 #endif 1085 }; 1086 1087 int xe_register_pci_driver(void) 1088 { 1089 return pci_register_driver(&xe_pci_driver); 1090 } 1091 1092 void xe_unregister_pci_driver(void) 1093 { 1094 pci_unregister_driver(&xe_pci_driver); 1095 } 1096 1097 #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST) 1098 #include "tests/xe_pci.c" 1099 #endif 1100