1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 #include "xe_pci.h" 7 8 #include <kunit/static_stub.h> 9 #include <linux/device/driver.h> 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/pm_runtime.h> 13 14 #include <drm/drm_color_mgmt.h> 15 #include <drm/drm_drv.h> 16 #include <drm/xe_pciids.h> 17 18 #include "display/xe_display.h" 19 #include "regs/xe_gt_regs.h" 20 #include "xe_device.h" 21 #include "xe_drv.h" 22 #include "xe_gt.h" 23 #include "xe_macros.h" 24 #include "xe_mmio.h" 25 #include "xe_module.h" 26 #include "xe_pci_types.h" 27 #include "xe_pm.h" 28 #include "xe_sriov.h" 29 #include "xe_step.h" 30 #include "xe_tile.h" 31 32 enum toggle_d3cold { 33 D3COLD_DISABLE, 34 D3COLD_ENABLE, 35 }; 36 37 struct xe_subplatform_desc { 38 enum xe_subplatform subplatform; 39 const char *name; 40 const u16 *pciidlist; 41 }; 42 43 struct xe_gt_desc { 44 enum xe_gt_type type; 45 u32 mmio_adj_limit; 46 u32 mmio_adj_offset; 47 }; 48 49 struct xe_device_desc { 50 /* Should only ever be set for platforms without GMD_ID */ 51 const struct xe_graphics_desc *graphics; 52 /* Should only ever be set for platforms without GMD_ID */ 53 const struct xe_media_desc *media; 54 55 const char *platform_name; 56 const struct xe_subplatform_desc *subplatforms; 57 58 enum xe_platform platform; 59 60 u8 require_force_probe:1; 61 u8 is_dgfx:1; 62 63 u8 has_display:1; 64 u8 has_heci_gscfi:1; 65 u8 has_llc:1; 66 u8 has_mmio_ext:1; 67 u8 has_sriov:1; 68 u8 skip_guc_pc:1; 69 u8 skip_mtcfg:1; 70 u8 skip_pcode:1; 71 }; 72 73 __diag_push(); 74 __diag_ignore_all("-Woverride-init", "Allow field overrides in table"); 75 76 #define PLATFORM(x) \ 77 .platform = (x), \ 78 .platform_name = #x 79 80 #define NOP(x) x 81 82 static const struct xe_graphics_desc graphics_xelp = { 83 .name = "Xe_LP", 84 .ver = 12, 85 .rel = 0, 86 87 .hw_engine_mask = BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0), 88 89 .dma_mask_size = 39, 90 .va_bits = 48, 91 .vm_max_level = 3, 92 }; 93 94 static const struct xe_graphics_desc graphics_xelpp = { 95 .name = "Xe_LP+", 96 .ver = 12, 97 .rel = 10, 98 99 .hw_engine_mask = BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0), 100 101 .dma_mask_size = 39, 102 .va_bits = 48, 103 .vm_max_level = 3, 104 }; 105 106 #define XE_HP_FEATURES \ 107 .has_range_tlb_invalidation = true, \ 108 .has_flat_ccs = true, \ 109 .dma_mask_size = 46, \ 110 .va_bits = 48, \ 111 .vm_max_level = 3 112 113 static const struct xe_graphics_desc graphics_xehpg = { 114 .name = "Xe_HPG", 115 .ver = 12, 116 .rel = 55, 117 118 .hw_engine_mask = 119 BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) | 120 BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) | 121 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3), 122 123 XE_HP_FEATURES, 124 .vram_flags = XE_VRAM_FLAGS_NEED64K, 125 }; 126 127 static const struct xe_graphics_desc graphics_xehpc = { 128 .name = "Xe_HPC", 129 .ver = 12, 130 .rel = 60, 131 132 .hw_engine_mask = 133 BIT(XE_HW_ENGINE_BCS0) | BIT(XE_HW_ENGINE_BCS1) | 134 BIT(XE_HW_ENGINE_BCS2) | BIT(XE_HW_ENGINE_BCS3) | 135 BIT(XE_HW_ENGINE_BCS4) | BIT(XE_HW_ENGINE_BCS5) | 136 BIT(XE_HW_ENGINE_BCS6) | BIT(XE_HW_ENGINE_BCS7) | 137 BIT(XE_HW_ENGINE_BCS8) | 138 BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) | 139 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3), 140 141 XE_HP_FEATURES, 142 .dma_mask_size = 52, 143 .max_remote_tiles = 1, 144 .va_bits = 57, 145 .vm_max_level = 4, 146 .vram_flags = XE_VRAM_FLAGS_NEED64K, 147 148 .has_asid = 1, 149 .has_flat_ccs = 0, 150 .has_usm = 1, 151 }; 152 153 static const struct xe_graphics_desc graphics_xelpg = { 154 .name = "Xe_LPG", 155 .hw_engine_mask = 156 BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) | 157 BIT(XE_HW_ENGINE_CCS0), 158 159 XE_HP_FEATURES, 160 .has_flat_ccs = 0, 161 }; 162 163 #define XE2_GFX_FEATURES \ 164 .dma_mask_size = 46, \ 165 .has_asid = 1, \ 166 .has_flat_ccs = 1, \ 167 .has_range_tlb_invalidation = 1, \ 168 .has_usm = 1, \ 169 .va_bits = 48, \ 170 .vm_max_level = 4, \ 171 .hw_engine_mask = \ 172 BIT(XE_HW_ENGINE_RCS0) | \ 173 BIT(XE_HW_ENGINE_BCS8) | BIT(XE_HW_ENGINE_BCS0) | \ 174 GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0) 175 176 static const struct xe_graphics_desc graphics_xe2 = { 177 .name = "Xe2_LPG", 178 179 XE2_GFX_FEATURES, 180 }; 181 182 static const struct xe_media_desc media_xem = { 183 .name = "Xe_M", 184 .ver = 12, 185 .rel = 0, 186 187 .hw_engine_mask = 188 BIT(XE_HW_ENGINE_VCS0) | BIT(XE_HW_ENGINE_VCS2) | 189 BIT(XE_HW_ENGINE_VECS0), 190 }; 191 192 static const struct xe_media_desc media_xehpm = { 193 .name = "Xe_HPM", 194 .ver = 12, 195 .rel = 55, 196 197 .hw_engine_mask = 198 BIT(XE_HW_ENGINE_VCS0) | BIT(XE_HW_ENGINE_VCS2) | 199 BIT(XE_HW_ENGINE_VECS0) | BIT(XE_HW_ENGINE_VECS1), 200 }; 201 202 static const struct xe_media_desc media_xelpmp = { 203 .name = "Xe_LPM+", 204 .hw_engine_mask = 205 BIT(XE_HW_ENGINE_VCS0) | BIT(XE_HW_ENGINE_VCS2) | 206 BIT(XE_HW_ENGINE_VECS0) | BIT(XE_HW_ENGINE_GSCCS0) 207 }; 208 209 static const struct xe_media_desc media_xe2 = { 210 .name = "Xe2_LPM", 211 .hw_engine_mask = 212 BIT(XE_HW_ENGINE_VCS0) | BIT(XE_HW_ENGINE_VECS0), /* TODO: GSC0 */ 213 }; 214 215 static const struct xe_device_desc tgl_desc = { 216 .graphics = &graphics_xelp, 217 .media = &media_xem, 218 PLATFORM(XE_TIGERLAKE), 219 .has_display = true, 220 .has_llc = true, 221 .require_force_probe = true, 222 }; 223 224 static const struct xe_device_desc rkl_desc = { 225 .graphics = &graphics_xelp, 226 .media = &media_xem, 227 PLATFORM(XE_ROCKETLAKE), 228 .has_display = true, 229 .has_llc = true, 230 .require_force_probe = true, 231 }; 232 233 static const u16 adls_rpls_ids[] = { XE_RPLS_IDS(NOP), 0 }; 234 235 static const struct xe_device_desc adl_s_desc = { 236 .graphics = &graphics_xelp, 237 .media = &media_xem, 238 PLATFORM(XE_ALDERLAKE_S), 239 .has_display = true, 240 .has_llc = true, 241 .require_force_probe = true, 242 .subplatforms = (const struct xe_subplatform_desc[]) { 243 { XE_SUBPLATFORM_ALDERLAKE_S_RPLS, "RPLS", adls_rpls_ids }, 244 {}, 245 }, 246 }; 247 248 static const u16 adlp_rplu_ids[] = { XE_RPLU_IDS(NOP), 0 }; 249 250 static const struct xe_device_desc adl_p_desc = { 251 .graphics = &graphics_xelp, 252 .media = &media_xem, 253 PLATFORM(XE_ALDERLAKE_P), 254 .has_display = true, 255 .has_llc = true, 256 .require_force_probe = true, 257 .subplatforms = (const struct xe_subplatform_desc[]) { 258 { XE_SUBPLATFORM_ALDERLAKE_P_RPLU, "RPLU", adlp_rplu_ids }, 259 {}, 260 }, 261 }; 262 263 static const struct xe_device_desc adl_n_desc = { 264 .graphics = &graphics_xelp, 265 .media = &media_xem, 266 PLATFORM(XE_ALDERLAKE_N), 267 .has_display = true, 268 .has_llc = true, 269 .require_force_probe = true, 270 }; 271 272 #define DGFX_FEATURES \ 273 .is_dgfx = 1 274 275 static const struct xe_device_desc dg1_desc = { 276 .graphics = &graphics_xelpp, 277 .media = &media_xem, 278 DGFX_FEATURES, 279 PLATFORM(XE_DG1), 280 .has_display = true, 281 .has_heci_gscfi = 1, 282 .require_force_probe = true, 283 }; 284 285 static const u16 dg2_g10_ids[] = { XE_DG2_G10_IDS(NOP), XE_ATS_M150_IDS(NOP), 0 }; 286 static const u16 dg2_g11_ids[] = { XE_DG2_G11_IDS(NOP), XE_ATS_M75_IDS(NOP), 0 }; 287 static const u16 dg2_g12_ids[] = { XE_DG2_G12_IDS(NOP), 0 }; 288 289 #define DG2_FEATURES \ 290 DGFX_FEATURES, \ 291 PLATFORM(XE_DG2), \ 292 .has_heci_gscfi = 1, \ 293 .subplatforms = (const struct xe_subplatform_desc[]) { \ 294 { XE_SUBPLATFORM_DG2_G10, "G10", dg2_g10_ids }, \ 295 { XE_SUBPLATFORM_DG2_G11, "G11", dg2_g11_ids }, \ 296 { XE_SUBPLATFORM_DG2_G12, "G12", dg2_g12_ids }, \ 297 { } \ 298 } 299 300 static const struct xe_device_desc ats_m_desc = { 301 .graphics = &graphics_xehpg, 302 .media = &media_xehpm, 303 .require_force_probe = true, 304 305 DG2_FEATURES, 306 .has_display = false, 307 }; 308 309 static const struct xe_device_desc dg2_desc = { 310 .graphics = &graphics_xehpg, 311 .media = &media_xehpm, 312 .require_force_probe = true, 313 314 DG2_FEATURES, 315 .has_display = true, 316 }; 317 318 static const __maybe_unused struct xe_device_desc pvc_desc = { 319 .graphics = &graphics_xehpc, 320 DGFX_FEATURES, 321 PLATFORM(XE_PVC), 322 .has_display = false, 323 .has_heci_gscfi = 1, 324 .require_force_probe = true, 325 }; 326 327 static const struct xe_device_desc mtl_desc = { 328 /* .graphics and .media determined via GMD_ID */ 329 .require_force_probe = true, 330 PLATFORM(XE_METEORLAKE), 331 .has_display = true, 332 }; 333 334 static const struct xe_device_desc lnl_desc = { 335 PLATFORM(XE_LUNARLAKE), 336 .has_display = true, 337 .require_force_probe = true, 338 }; 339 340 #undef PLATFORM 341 __diag_pop(); 342 343 /* Map of GMD_ID values to graphics IP */ 344 static const struct gmdid_map graphics_ip_map[] = { 345 { 1270, &graphics_xelpg }, 346 { 1271, &graphics_xelpg }, 347 { 2004, &graphics_xe2 }, 348 }; 349 350 /* Map of GMD_ID values to media IP */ 351 static const struct gmdid_map media_ip_map[] = { 352 { 1300, &media_xelpmp }, 353 { 2000, &media_xe2 }, 354 }; 355 356 #define INTEL_VGA_DEVICE(id, info) { \ 357 PCI_DEVICE(PCI_VENDOR_ID_INTEL, id), \ 358 PCI_BASE_CLASS_DISPLAY << 16, 0xff << 16, \ 359 (unsigned long) info } 360 361 /* 362 * Make sure any device matches here are from most specific to most 363 * general. For example, since the Quanta match is based on the subsystem 364 * and subvendor IDs, we need it to come before the more general IVB 365 * PCI ID matches, otherwise we'll use the wrong info struct above. 366 */ 367 static const struct pci_device_id pciidlist[] = { 368 XE_TGL_IDS(INTEL_VGA_DEVICE, &tgl_desc), 369 XE_RKL_IDS(INTEL_VGA_DEVICE, &rkl_desc), 370 XE_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc), 371 XE_ADLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 372 XE_ADLN_IDS(INTEL_VGA_DEVICE, &adl_n_desc), 373 XE_RPLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 374 XE_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc), 375 XE_DG1_IDS(INTEL_VGA_DEVICE, &dg1_desc), 376 XE_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_desc), 377 XE_DG2_IDS(INTEL_VGA_DEVICE, &dg2_desc), 378 XE_MTL_IDS(INTEL_VGA_DEVICE, &mtl_desc), 379 XE_LNL_IDS(INTEL_VGA_DEVICE, &lnl_desc), 380 { } 381 }; 382 MODULE_DEVICE_TABLE(pci, pciidlist); 383 384 #undef INTEL_VGA_DEVICE 385 386 /* is device_id present in comma separated list of ids */ 387 static bool device_id_in_list(u16 device_id, const char *devices, bool negative) 388 { 389 char *s, *p, *tok; 390 bool ret; 391 392 if (!devices || !*devices) 393 return false; 394 395 /* match everything */ 396 if (negative && strcmp(devices, "!*") == 0) 397 return true; 398 if (!negative && strcmp(devices, "*") == 0) 399 return true; 400 401 s = kstrdup(devices, GFP_KERNEL); 402 if (!s) 403 return false; 404 405 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) { 406 u16 val; 407 408 if (negative && tok[0] == '!') 409 tok++; 410 else if ((negative && tok[0] != '!') || 411 (!negative && tok[0] == '!')) 412 continue; 413 414 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) { 415 ret = true; 416 break; 417 } 418 } 419 420 kfree(s); 421 422 return ret; 423 } 424 425 static bool id_forced(u16 device_id) 426 { 427 return device_id_in_list(device_id, xe_modparam.force_probe, false); 428 } 429 430 static bool id_blocked(u16 device_id) 431 { 432 return device_id_in_list(device_id, xe_modparam.force_probe, true); 433 } 434 435 static const struct xe_subplatform_desc * 436 find_subplatform(const struct xe_device *xe, const struct xe_device_desc *desc) 437 { 438 const struct xe_subplatform_desc *sp; 439 const u16 *id; 440 441 for (sp = desc->subplatforms; sp && sp->subplatform; sp++) 442 for (id = sp->pciidlist; *id; id++) 443 if (*id == xe->info.devid) 444 return sp; 445 446 return NULL; 447 } 448 449 enum xe_gmdid_type { 450 GMDID_GRAPHICS, 451 GMDID_MEDIA 452 }; 453 454 static void read_gmdid(struct xe_device *xe, enum xe_gmdid_type type, u32 *ver, u32 *revid) 455 { 456 struct xe_gt *gt = xe_root_mmio_gt(xe); 457 struct xe_reg gmdid_reg = GMD_ID; 458 u32 val; 459 460 KUNIT_STATIC_STUB_REDIRECT(read_gmdid, xe, type, ver, revid); 461 462 if (type == GMDID_MEDIA) 463 gmdid_reg.addr += MEDIA_GT_GSI_OFFSET; 464 465 val = xe_mmio_read32(gt, gmdid_reg); 466 *ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val) * 100 + REG_FIELD_GET(GMD_ID_RELEASE_MASK, val); 467 *revid = REG_FIELD_GET(GMD_ID_REVID, val); 468 } 469 470 /* 471 * Pre-GMD_ID platform: device descriptor already points to the appropriate 472 * graphics descriptor. Simply forward the description and calculate the version 473 * appropriately. "graphics" should be present in all such platforms, while 474 * media is optional. 475 */ 476 static void handle_pre_gmdid(struct xe_device *xe, 477 const struct xe_graphics_desc *graphics, 478 const struct xe_media_desc *media) 479 { 480 xe->info.graphics_verx100 = graphics->ver * 100 + graphics->rel; 481 482 if (media) 483 xe->info.media_verx100 = media->ver * 100 + media->rel; 484 485 } 486 487 /* 488 * GMD_ID platform: read IP version from hardware and select graphics descriptor 489 * based on the result. 490 */ 491 static void handle_gmdid(struct xe_device *xe, 492 const struct xe_graphics_desc **graphics, 493 const struct xe_media_desc **media, 494 u32 *graphics_revid, 495 u32 *media_revid) 496 { 497 u32 ver; 498 499 read_gmdid(xe, GMDID_GRAPHICS, &ver, graphics_revid); 500 501 for (int i = 0; i < ARRAY_SIZE(graphics_ip_map); i++) { 502 if (ver == graphics_ip_map[i].ver) { 503 xe->info.graphics_verx100 = ver; 504 *graphics = graphics_ip_map[i].ip; 505 506 break; 507 } 508 } 509 510 if (!xe->info.graphics_verx100) { 511 drm_err(&xe->drm, "Hardware reports unknown graphics version %u.%02u\n", 512 ver / 100, ver % 100); 513 } 514 515 read_gmdid(xe, GMDID_MEDIA, &ver, media_revid); 516 517 /* Media may legitimately be fused off / not present */ 518 if (ver == 0) 519 return; 520 521 for (int i = 0; i < ARRAY_SIZE(media_ip_map); i++) { 522 if (ver == media_ip_map[i].ver) { 523 xe->info.media_verx100 = ver; 524 *media = media_ip_map[i].ip; 525 526 break; 527 } 528 } 529 530 if (!xe->info.media_verx100) { 531 drm_err(&xe->drm, "Hardware reports unknown media version %u.%02u\n", 532 ver / 100, ver % 100); 533 } 534 } 535 536 /* 537 * Initialize device info content that only depends on static driver_data 538 * passed to the driver at probe time from PCI ID table. 539 */ 540 static int xe_info_init_early(struct xe_device *xe, 541 const struct xe_device_desc *desc, 542 const struct xe_subplatform_desc *subplatform_desc) 543 { 544 int err; 545 546 xe->info.platform = desc->platform; 547 xe->info.subplatform = subplatform_desc ? 548 subplatform_desc->subplatform : XE_SUBPLATFORM_NONE; 549 550 xe->info.is_dgfx = desc->is_dgfx; 551 xe->info.has_heci_gscfi = desc->has_heci_gscfi; 552 xe->info.has_llc = desc->has_llc; 553 xe->info.has_mmio_ext = desc->has_mmio_ext; 554 xe->info.has_sriov = desc->has_sriov; 555 xe->info.skip_guc_pc = desc->skip_guc_pc; 556 xe->info.skip_mtcfg = desc->skip_mtcfg; 557 xe->info.skip_pcode = desc->skip_pcode; 558 559 xe->info.enable_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) && 560 xe_modparam.enable_display && 561 desc->has_display; 562 563 err = xe_tile_init_early(xe_device_get_root_tile(xe), xe, 0); 564 if (err) 565 return err; 566 567 return 0; 568 } 569 570 /* 571 * Initialize device info content that does require knowledge about 572 * graphics / media IP version. 573 * Make sure that GT / tile structures allocated by the driver match the data 574 * present in device info. 575 */ 576 static int xe_info_init(struct xe_device *xe, 577 const struct xe_graphics_desc *graphics_desc, 578 const struct xe_media_desc *media_desc) 579 { 580 u32 graphics_gmdid_revid = 0, media_gmdid_revid = 0; 581 struct xe_tile *tile; 582 struct xe_gt *gt; 583 u8 id; 584 585 /* 586 * If this platform supports GMD_ID, we'll detect the proper IP 587 * descriptor to use from hardware registers. desc->graphics will only 588 * ever be set at this point for platforms before GMD_ID. In that case 589 * the IP descriptions and versions are simply derived from that. 590 */ 591 if (graphics_desc) { 592 handle_pre_gmdid(xe, graphics_desc, media_desc); 593 xe->info.step = xe_step_pre_gmdid_get(xe); 594 } else { 595 xe_assert(xe, !media_desc); 596 handle_gmdid(xe, &graphics_desc, &media_desc, 597 &graphics_gmdid_revid, &media_gmdid_revid); 598 xe->info.step = xe_step_gmdid_get(xe, 599 graphics_gmdid_revid, 600 media_gmdid_revid); 601 } 602 603 /* 604 * If we couldn't detect the graphics IP, that's considered a fatal 605 * error and we should abort driver load. Failing to detect media 606 * IP is non-fatal; we'll just proceed without enabling media support. 607 */ 608 if (!graphics_desc) 609 return -ENODEV; 610 611 xe->info.graphics_name = graphics_desc->name; 612 xe->info.media_name = media_desc ? media_desc->name : "none"; 613 xe->info.tile_mmio_ext_size = graphics_desc->tile_mmio_ext_size; 614 615 xe->info.dma_mask_size = graphics_desc->dma_mask_size; 616 xe->info.vram_flags = graphics_desc->vram_flags; 617 xe->info.va_bits = graphics_desc->va_bits; 618 xe->info.vm_max_level = graphics_desc->vm_max_level; 619 xe->info.has_asid = graphics_desc->has_asid; 620 xe->info.has_flat_ccs = graphics_desc->has_flat_ccs; 621 xe->info.has_range_tlb_invalidation = graphics_desc->has_range_tlb_invalidation; 622 xe->info.has_usm = graphics_desc->has_usm; 623 624 /* 625 * All platforms have at least one primary GT. Any platform with media 626 * version 13 or higher has an additional dedicated media GT. And 627 * depending on the graphics IP there may be additional "remote tiles." 628 * All of these together determine the overall GT count. 629 * 630 * FIXME: 'tile_count' here is misnamed since the rest of the driver 631 * treats it as the number of GTs rather than just the number of tiles. 632 */ 633 xe->info.tile_count = 1 + graphics_desc->max_remote_tiles; 634 635 for_each_remote_tile(tile, xe, id) { 636 int err; 637 638 err = xe_tile_init_early(tile, xe, id); 639 if (err) 640 return err; 641 } 642 643 for_each_tile(tile, xe, id) { 644 gt = tile->primary_gt; 645 gt->info.id = xe->info.gt_count++; 646 gt->info.type = XE_GT_TYPE_MAIN; 647 gt->info.__engine_mask = graphics_desc->hw_engine_mask; 648 if (MEDIA_VER(xe) < 13 && media_desc) 649 gt->info.__engine_mask |= media_desc->hw_engine_mask; 650 651 if (MEDIA_VER(xe) < 13 || !media_desc) 652 continue; 653 654 /* 655 * Allocate and setup media GT for platforms with standalone 656 * media. 657 */ 658 tile->media_gt = xe_gt_alloc(tile); 659 if (IS_ERR(tile->media_gt)) 660 return PTR_ERR(tile->media_gt); 661 662 gt = tile->media_gt; 663 gt->info.type = XE_GT_TYPE_MEDIA; 664 gt->info.__engine_mask = media_desc->hw_engine_mask; 665 gt->mmio.adj_offset = MEDIA_GT_GSI_OFFSET; 666 gt->mmio.adj_limit = MEDIA_GT_GSI_LENGTH; 667 668 /* 669 * FIXME: At the moment multi-tile and standalone media are 670 * mutually exclusive on current platforms. We'll need to 671 * come up with a better way to number GTs if we ever wind 672 * up with platforms that support both together. 673 */ 674 drm_WARN_ON(&xe->drm, id != 0); 675 gt->info.id = xe->info.gt_count++; 676 } 677 678 return 0; 679 } 680 681 static void xe_pci_remove(struct pci_dev *pdev) 682 { 683 struct xe_device *xe; 684 685 xe = pci_get_drvdata(pdev); 686 if (!xe) /* driver load aborted, nothing to cleanup */ 687 return; 688 689 xe_device_remove(xe); 690 xe_pm_runtime_fini(xe); 691 pci_set_drvdata(pdev, NULL); 692 } 693 694 static int xe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 695 { 696 const struct xe_device_desc *desc = (const void *)ent->driver_data; 697 const struct xe_subplatform_desc *subplatform_desc; 698 struct xe_device *xe; 699 int err; 700 701 if (desc->require_force_probe && !id_forced(pdev->device)) { 702 dev_info(&pdev->dev, 703 "Your graphics device %04x is not officially supported\n" 704 "by xe driver in this kernel version. To force Xe probe,\n" 705 "use xe.force_probe='%04x' and i915.force_probe='!%04x'\n" 706 "module parameters or CONFIG_DRM_XE_FORCE_PROBE='%04x' and\n" 707 "CONFIG_DRM_I915_FORCE_PROBE='!%04x' configuration options.\n", 708 pdev->device, pdev->device, pdev->device, 709 pdev->device, pdev->device); 710 return -ENODEV; 711 } 712 713 if (id_blocked(pdev->device)) { 714 dev_info(&pdev->dev, "Probe blocked for device [%04x:%04x].\n", 715 pdev->vendor, pdev->device); 716 return -ENODEV; 717 } 718 719 if (xe_display_driver_probe_defer(pdev)) 720 return -EPROBE_DEFER; 721 722 err = pcim_enable_device(pdev); 723 if (err) 724 return err; 725 726 xe = xe_device_create(pdev, ent); 727 if (IS_ERR(xe)) 728 return PTR_ERR(xe); 729 730 pci_set_drvdata(pdev, xe); 731 732 xe_pm_assert_unbounded_bridge(xe); 733 subplatform_desc = find_subplatform(xe, desc); 734 735 pci_set_master(pdev); 736 737 err = xe_info_init_early(xe, desc, subplatform_desc); 738 if (err) 739 return err; 740 741 xe_sriov_probe_early(xe, desc->has_sriov); 742 743 err = xe_device_probe_early(xe); 744 if (err) 745 return err; 746 747 err = xe_info_init(xe, desc->graphics, desc->media); 748 if (err) 749 return err; 750 751 xe_display_probe(xe); 752 753 drm_dbg(&xe->drm, "%s %s %04x:%04x dgfx:%d gfx:%s (%d.%02d) media:%s (%d.%02d) display:%s dma_m_s:%d tc:%d gscfi:%d", 754 desc->platform_name, 755 subplatform_desc ? subplatform_desc->name : "", 756 xe->info.devid, xe->info.revid, 757 xe->info.is_dgfx, 758 xe->info.graphics_name, 759 xe->info.graphics_verx100 / 100, 760 xe->info.graphics_verx100 % 100, 761 xe->info.media_name, 762 xe->info.media_verx100 / 100, 763 xe->info.media_verx100 % 100, 764 str_yes_no(xe->info.enable_display), 765 xe->info.dma_mask_size, xe->info.tile_count, 766 xe->info.has_heci_gscfi); 767 768 drm_dbg(&xe->drm, "Stepping = (G:%s, M:%s, D:%s, B:%s)\n", 769 xe_step_name(xe->info.step.graphics), 770 xe_step_name(xe->info.step.media), 771 xe_step_name(xe->info.step.display), 772 xe_step_name(xe->info.step.basedie)); 773 774 drm_dbg(&xe->drm, "SR-IOV support: %s (mode: %s)\n", 775 str_yes_no(xe_device_has_sriov(xe)), 776 xe_sriov_mode_to_string(xe_device_sriov_mode(xe))); 777 778 xe_pm_init_early(xe); 779 780 err = xe_device_probe(xe); 781 if (err) 782 return err; 783 784 xe_pm_init(xe); 785 786 drm_dbg(&xe->drm, "d3cold: capable=%s\n", 787 str_yes_no(xe->d3cold.capable)); 788 789 return 0; 790 } 791 792 static void xe_pci_shutdown(struct pci_dev *pdev) 793 { 794 xe_device_shutdown(pdev_to_xe_device(pdev)); 795 } 796 797 #ifdef CONFIG_PM_SLEEP 798 static void d3cold_toggle(struct pci_dev *pdev, enum toggle_d3cold toggle) 799 { 800 struct xe_device *xe = pdev_to_xe_device(pdev); 801 struct pci_dev *root_pdev; 802 803 if (!xe->d3cold.capable) 804 return; 805 806 root_pdev = pcie_find_root_port(pdev); 807 if (!root_pdev) 808 return; 809 810 switch (toggle) { 811 case D3COLD_DISABLE: 812 pci_d3cold_disable(root_pdev); 813 break; 814 case D3COLD_ENABLE: 815 pci_d3cold_enable(root_pdev); 816 break; 817 } 818 } 819 820 static int xe_pci_suspend(struct device *dev) 821 { 822 struct pci_dev *pdev = to_pci_dev(dev); 823 int err; 824 825 err = xe_pm_suspend(pdev_to_xe_device(pdev)); 826 if (err) 827 return err; 828 829 /* 830 * Enabling D3Cold is needed for S2Idle/S0ix. 831 * It is save to allow here since xe_pm_suspend has evicted 832 * the local memory and the direct complete optimization is disabled. 833 */ 834 d3cold_toggle(pdev, D3COLD_ENABLE); 835 836 pci_save_state(pdev); 837 pci_disable_device(pdev); 838 839 return 0; 840 } 841 842 static int xe_pci_resume(struct device *dev) 843 { 844 struct pci_dev *pdev = to_pci_dev(dev); 845 int err; 846 847 /* Give back the D3Cold decision to the runtime P M*/ 848 d3cold_toggle(pdev, D3COLD_DISABLE); 849 850 err = pci_set_power_state(pdev, PCI_D0); 851 if (err) 852 return err; 853 854 err = pci_enable_device(pdev); 855 if (err) 856 return err; 857 858 pci_set_master(pdev); 859 860 err = xe_pm_resume(pdev_to_xe_device(pdev)); 861 if (err) 862 return err; 863 864 return 0; 865 } 866 867 static int xe_pci_runtime_suspend(struct device *dev) 868 { 869 struct pci_dev *pdev = to_pci_dev(dev); 870 struct xe_device *xe = pdev_to_xe_device(pdev); 871 int err; 872 873 err = xe_pm_runtime_suspend(xe); 874 if (err) 875 return err; 876 877 pci_save_state(pdev); 878 879 if (xe->d3cold.allowed) { 880 d3cold_toggle(pdev, D3COLD_ENABLE); 881 pci_disable_device(pdev); 882 pci_ignore_hotplug(pdev); 883 pci_set_power_state(pdev, PCI_D3cold); 884 } else { 885 d3cold_toggle(pdev, D3COLD_DISABLE); 886 pci_set_power_state(pdev, PCI_D3hot); 887 } 888 889 return 0; 890 } 891 892 static int xe_pci_runtime_resume(struct device *dev) 893 { 894 struct pci_dev *pdev = to_pci_dev(dev); 895 struct xe_device *xe = pdev_to_xe_device(pdev); 896 int err; 897 898 err = pci_set_power_state(pdev, PCI_D0); 899 if (err) 900 return err; 901 902 pci_restore_state(pdev); 903 904 if (xe->d3cold.allowed) { 905 err = pci_enable_device(pdev); 906 if (err) 907 return err; 908 909 pci_set_master(pdev); 910 } 911 912 return xe_pm_runtime_resume(xe); 913 } 914 915 static int xe_pci_runtime_idle(struct device *dev) 916 { 917 struct pci_dev *pdev = to_pci_dev(dev); 918 struct xe_device *xe = pdev_to_xe_device(pdev); 919 920 xe_pm_d3cold_allowed_toggle(xe); 921 922 return 0; 923 } 924 925 static const struct dev_pm_ops xe_pm_ops = { 926 SET_SYSTEM_SLEEP_PM_OPS(xe_pci_suspend, xe_pci_resume) 927 SET_RUNTIME_PM_OPS(xe_pci_runtime_suspend, xe_pci_runtime_resume, xe_pci_runtime_idle) 928 }; 929 #endif 930 931 static struct pci_driver xe_pci_driver = { 932 .name = DRIVER_NAME, 933 .id_table = pciidlist, 934 .probe = xe_pci_probe, 935 .remove = xe_pci_remove, 936 .shutdown = xe_pci_shutdown, 937 #ifdef CONFIG_PM_SLEEP 938 .driver.pm = &xe_pm_ops, 939 #endif 940 }; 941 942 int xe_register_pci_driver(void) 943 { 944 return pci_register_driver(&xe_pci_driver); 945 } 946 947 void xe_unregister_pci_driver(void) 948 { 949 pci_unregister_driver(&xe_pci_driver); 950 } 951 952 #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST) 953 #include "tests/xe_pci.c" 954 #endif 955