1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 #include "xe_pci.h" 7 8 #include <kunit/static_stub.h> 9 #include <linux/device/driver.h> 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/pm_runtime.h> 13 14 #include <drm/drm_color_mgmt.h> 15 #include <drm/drm_drv.h> 16 #include <drm/intel/pciids.h> 17 18 #include "display/xe_display.h" 19 #include "regs/xe_gt_regs.h" 20 #include "xe_device.h" 21 #include "xe_drv.h" 22 #include "xe_gt.h" 23 #include "xe_gt_sriov_vf.h" 24 #include "xe_guc.h" 25 #include "xe_macros.h" 26 #include "xe_mmio.h" 27 #include "xe_module.h" 28 #include "xe_pci_sriov.h" 29 #include "xe_pci_types.h" 30 #include "xe_pm.h" 31 #include "xe_sriov.h" 32 #include "xe_step.h" 33 #include "xe_survivability_mode.h" 34 #include "xe_tile.h" 35 36 enum toggle_d3cold { 37 D3COLD_DISABLE, 38 D3COLD_ENABLE, 39 }; 40 41 struct xe_subplatform_desc { 42 enum xe_subplatform subplatform; 43 const char *name; 44 const u16 *pciidlist; 45 }; 46 47 struct xe_device_desc { 48 /* Should only ever be set for platforms without GMD_ID */ 49 const struct xe_ip *pre_gmdid_graphics_ip; 50 /* Should only ever be set for platforms without GMD_ID */ 51 const struct xe_ip *pre_gmdid_media_ip; 52 53 const char *platform_name; 54 const struct xe_subplatform_desc *subplatforms; 55 56 enum xe_platform platform; 57 58 u8 dma_mask_size; 59 u8 max_remote_tiles:2; 60 61 u8 require_force_probe:1; 62 u8 is_dgfx:1; 63 64 u8 has_display:1; 65 u8 has_heci_gscfi:1; 66 u8 has_heci_cscfi:1; 67 u8 has_llc:1; 68 u8 has_pxp:1; 69 u8 has_sriov:1; 70 u8 skip_guc_pc:1; 71 u8 skip_mtcfg:1; 72 u8 skip_pcode:1; 73 }; 74 75 __diag_push(); 76 __diag_ignore_all("-Woverride-init", "Allow field overrides in table"); 77 78 #define PLATFORM(x) \ 79 .platform = XE_##x, \ 80 .platform_name = #x 81 82 #define NOP(x) x 83 84 static const struct xe_graphics_desc graphics_xelp = { 85 .hw_engine_mask = BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0), 86 87 .va_bits = 48, 88 .vm_max_level = 3, 89 }; 90 91 #define XE_HP_FEATURES \ 92 .has_range_tlb_invalidation = true, \ 93 .va_bits = 48, \ 94 .vm_max_level = 3 95 96 static const struct xe_graphics_desc graphics_xehpg = { 97 .hw_engine_mask = 98 BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) | 99 BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) | 100 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3), 101 102 XE_HP_FEATURES, 103 .vram_flags = XE_VRAM_FLAGS_NEED64K, 104 105 .has_flat_ccs = 1, 106 }; 107 108 static const struct xe_graphics_desc graphics_xehpc = { 109 .hw_engine_mask = 110 BIT(XE_HW_ENGINE_BCS0) | BIT(XE_HW_ENGINE_BCS1) | 111 BIT(XE_HW_ENGINE_BCS2) | BIT(XE_HW_ENGINE_BCS3) | 112 BIT(XE_HW_ENGINE_BCS4) | BIT(XE_HW_ENGINE_BCS5) | 113 BIT(XE_HW_ENGINE_BCS6) | BIT(XE_HW_ENGINE_BCS7) | 114 BIT(XE_HW_ENGINE_BCS8) | 115 BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) | 116 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3), 117 118 XE_HP_FEATURES, 119 .va_bits = 57, 120 .vm_max_level = 4, 121 .vram_flags = XE_VRAM_FLAGS_NEED64K, 122 123 .has_asid = 1, 124 .has_atomic_enable_pte_bit = 1, 125 .has_usm = 1, 126 }; 127 128 static const struct xe_graphics_desc graphics_xelpg = { 129 .hw_engine_mask = 130 BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) | 131 BIT(XE_HW_ENGINE_CCS0), 132 133 XE_HP_FEATURES, 134 }; 135 136 #define XE2_GFX_FEATURES \ 137 .has_asid = 1, \ 138 .has_atomic_enable_pte_bit = 1, \ 139 .has_flat_ccs = 1, \ 140 .has_indirect_ring_state = 1, \ 141 .has_range_tlb_invalidation = 1, \ 142 .has_usm = 1, \ 143 .has_64bit_timestamp = 1, \ 144 .va_bits = 48, \ 145 .vm_max_level = 4, \ 146 .hw_engine_mask = \ 147 BIT(XE_HW_ENGINE_RCS0) | \ 148 BIT(XE_HW_ENGINE_BCS8) | BIT(XE_HW_ENGINE_BCS0) | \ 149 GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0) 150 151 static const struct xe_graphics_desc graphics_xe2 = { 152 XE2_GFX_FEATURES, 153 }; 154 155 static const struct xe_media_desc media_xem = { 156 .hw_engine_mask = 157 GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) | 158 GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0), 159 }; 160 161 static const struct xe_media_desc media_xelpmp = { 162 .hw_engine_mask = 163 GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) | 164 GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0) | 165 BIT(XE_HW_ENGINE_GSCCS0) 166 }; 167 168 /* Pre-GMDID Graphics IPs */ 169 static const struct xe_ip graphics_ip_xelp = { 1200, "Xe_LP", &graphics_xelp }; 170 static const struct xe_ip graphics_ip_xelpp = { 1210, "Xe_LP+", &graphics_xelp }; 171 static const struct xe_ip graphics_ip_xehpg = { 1255, "Xe_HPG", &graphics_xehpg }; 172 static const struct xe_ip graphics_ip_xehpc = { 1260, "Xe_HPC", &graphics_xehpc }; 173 174 /* GMDID-based Graphics IPs */ 175 static const struct xe_ip graphics_ips[] = { 176 { 1270, "Xe_LPG", &graphics_xelpg }, 177 { 1271, "Xe_LPG", &graphics_xelpg }, 178 { 1274, "Xe_LPG+", &graphics_xelpg }, 179 { 2001, "Xe2_HPG", &graphics_xe2 }, 180 { 2004, "Xe2_LPG", &graphics_xe2 }, 181 { 3000, "Xe3_LPG", &graphics_xe2 }, 182 { 3001, "Xe3_LPG", &graphics_xe2 }, 183 }; 184 185 /* Pre-GMDID Media IPs */ 186 static const struct xe_ip media_ip_xem = { 1200, "Xe_M", &media_xem }; 187 static const struct xe_ip media_ip_xehpm = { 1255, "Xe_HPM", &media_xem }; 188 189 /* GMDID-based Media IPs */ 190 static const struct xe_ip media_ips[] = { 191 { 1300, "Xe_LPM+", &media_xelpmp }, 192 { 1301, "Xe2_HPM", &media_xelpmp }, 193 { 2000, "Xe2_LPM", &media_xelpmp }, 194 { 3000, "Xe3_LPM", &media_xelpmp }, 195 }; 196 197 static const struct xe_device_desc tgl_desc = { 198 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 199 .pre_gmdid_media_ip = &media_ip_xem, 200 PLATFORM(TIGERLAKE), 201 .dma_mask_size = 39, 202 .has_display = true, 203 .has_llc = true, 204 .require_force_probe = true, 205 }; 206 207 static const struct xe_device_desc rkl_desc = { 208 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 209 .pre_gmdid_media_ip = &media_ip_xem, 210 PLATFORM(ROCKETLAKE), 211 .dma_mask_size = 39, 212 .has_display = true, 213 .has_llc = true, 214 .require_force_probe = true, 215 }; 216 217 static const u16 adls_rpls_ids[] = { INTEL_RPLS_IDS(NOP), 0 }; 218 219 static const struct xe_device_desc adl_s_desc = { 220 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 221 .pre_gmdid_media_ip = &media_ip_xem, 222 PLATFORM(ALDERLAKE_S), 223 .dma_mask_size = 39, 224 .has_display = true, 225 .has_llc = true, 226 .require_force_probe = true, 227 .subplatforms = (const struct xe_subplatform_desc[]) { 228 { XE_SUBPLATFORM_ALDERLAKE_S_RPLS, "RPLS", adls_rpls_ids }, 229 {}, 230 }, 231 }; 232 233 static const u16 adlp_rplu_ids[] = { INTEL_RPLU_IDS(NOP), 0 }; 234 235 static const struct xe_device_desc adl_p_desc = { 236 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 237 .pre_gmdid_media_ip = &media_ip_xem, 238 PLATFORM(ALDERLAKE_P), 239 .dma_mask_size = 39, 240 .has_display = true, 241 .has_llc = true, 242 .require_force_probe = true, 243 .subplatforms = (const struct xe_subplatform_desc[]) { 244 { XE_SUBPLATFORM_ALDERLAKE_P_RPLU, "RPLU", adlp_rplu_ids }, 245 {}, 246 }, 247 }; 248 249 static const struct xe_device_desc adl_n_desc = { 250 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 251 .pre_gmdid_media_ip = &media_ip_xem, 252 PLATFORM(ALDERLAKE_N), 253 .dma_mask_size = 39, 254 .has_display = true, 255 .has_llc = true, 256 .require_force_probe = true, 257 }; 258 259 #define DGFX_FEATURES \ 260 .is_dgfx = 1 261 262 static const struct xe_device_desc dg1_desc = { 263 .pre_gmdid_graphics_ip = &graphics_ip_xelpp, 264 .pre_gmdid_media_ip = &media_ip_xem, 265 DGFX_FEATURES, 266 PLATFORM(DG1), 267 .dma_mask_size = 39, 268 .has_display = true, 269 .has_heci_gscfi = 1, 270 .require_force_probe = true, 271 }; 272 273 static const u16 dg2_g10_ids[] = { INTEL_DG2_G10_IDS(NOP), INTEL_ATS_M150_IDS(NOP), 0 }; 274 static const u16 dg2_g11_ids[] = { INTEL_DG2_G11_IDS(NOP), INTEL_ATS_M75_IDS(NOP), 0 }; 275 static const u16 dg2_g12_ids[] = { INTEL_DG2_G12_IDS(NOP), 0 }; 276 277 #define DG2_FEATURES \ 278 DGFX_FEATURES, \ 279 PLATFORM(DG2), \ 280 .has_heci_gscfi = 1, \ 281 .subplatforms = (const struct xe_subplatform_desc[]) { \ 282 { XE_SUBPLATFORM_DG2_G10, "G10", dg2_g10_ids }, \ 283 { XE_SUBPLATFORM_DG2_G11, "G11", dg2_g11_ids }, \ 284 { XE_SUBPLATFORM_DG2_G12, "G12", dg2_g12_ids }, \ 285 { } \ 286 } 287 288 static const struct xe_device_desc ats_m_desc = { 289 .pre_gmdid_graphics_ip = &graphics_ip_xehpg, 290 .pre_gmdid_media_ip = &media_ip_xehpm, 291 .dma_mask_size = 46, 292 .require_force_probe = true, 293 294 DG2_FEATURES, 295 .has_display = false, 296 }; 297 298 static const struct xe_device_desc dg2_desc = { 299 .pre_gmdid_graphics_ip = &graphics_ip_xehpg, 300 .pre_gmdid_media_ip = &media_ip_xehpm, 301 .dma_mask_size = 46, 302 .require_force_probe = true, 303 304 DG2_FEATURES, 305 .has_display = true, 306 }; 307 308 static const __maybe_unused struct xe_device_desc pvc_desc = { 309 .pre_gmdid_graphics_ip = &graphics_ip_xehpc, 310 DGFX_FEATURES, 311 PLATFORM(PVC), 312 .dma_mask_size = 52, 313 .has_display = false, 314 .has_heci_gscfi = 1, 315 .max_remote_tiles = 1, 316 .require_force_probe = true, 317 }; 318 319 static const struct xe_device_desc mtl_desc = { 320 /* .graphics and .media determined via GMD_ID */ 321 .require_force_probe = true, 322 PLATFORM(METEORLAKE), 323 .dma_mask_size = 46, 324 .has_display = true, 325 .has_pxp = true, 326 }; 327 328 static const struct xe_device_desc lnl_desc = { 329 PLATFORM(LUNARLAKE), 330 .dma_mask_size = 46, 331 .has_display = true, 332 .has_pxp = true, 333 }; 334 335 static const struct xe_device_desc bmg_desc = { 336 DGFX_FEATURES, 337 PLATFORM(BATTLEMAGE), 338 .dma_mask_size = 46, 339 .has_display = true, 340 .has_heci_cscfi = 1, 341 }; 342 343 static const struct xe_device_desc ptl_desc = { 344 PLATFORM(PANTHERLAKE), 345 .dma_mask_size = 46, 346 .has_display = true, 347 .has_sriov = true, 348 .require_force_probe = true, 349 }; 350 351 #undef PLATFORM 352 __diag_pop(); 353 354 /* 355 * Make sure any device matches here are from most specific to most 356 * general. For example, since the Quanta match is based on the subsystem 357 * and subvendor IDs, we need it to come before the more general IVB 358 * PCI ID matches, otherwise we'll use the wrong info struct above. 359 */ 360 static const struct pci_device_id pciidlist[] = { 361 INTEL_TGL_IDS(INTEL_VGA_DEVICE, &tgl_desc), 362 INTEL_RKL_IDS(INTEL_VGA_DEVICE, &rkl_desc), 363 INTEL_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc), 364 INTEL_ADLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 365 INTEL_ADLN_IDS(INTEL_VGA_DEVICE, &adl_n_desc), 366 INTEL_RPLU_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 367 INTEL_RPLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 368 INTEL_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc), 369 INTEL_DG1_IDS(INTEL_VGA_DEVICE, &dg1_desc), 370 INTEL_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_desc), 371 INTEL_ARL_IDS(INTEL_VGA_DEVICE, &mtl_desc), 372 INTEL_DG2_IDS(INTEL_VGA_DEVICE, &dg2_desc), 373 INTEL_MTL_IDS(INTEL_VGA_DEVICE, &mtl_desc), 374 INTEL_LNL_IDS(INTEL_VGA_DEVICE, &lnl_desc), 375 INTEL_BMG_IDS(INTEL_VGA_DEVICE, &bmg_desc), 376 INTEL_PTL_IDS(INTEL_VGA_DEVICE, &ptl_desc), 377 { } 378 }; 379 MODULE_DEVICE_TABLE(pci, pciidlist); 380 381 /* is device_id present in comma separated list of ids */ 382 static bool device_id_in_list(u16 device_id, const char *devices, bool negative) 383 { 384 char *s, *p, *tok; 385 bool ret; 386 387 if (!devices || !*devices) 388 return false; 389 390 /* match everything */ 391 if (negative && strcmp(devices, "!*") == 0) 392 return true; 393 if (!negative && strcmp(devices, "*") == 0) 394 return true; 395 396 s = kstrdup(devices, GFP_KERNEL); 397 if (!s) 398 return false; 399 400 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) { 401 u16 val; 402 403 if (negative && tok[0] == '!') 404 tok++; 405 else if ((negative && tok[0] != '!') || 406 (!negative && tok[0] == '!')) 407 continue; 408 409 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) { 410 ret = true; 411 break; 412 } 413 } 414 415 kfree(s); 416 417 return ret; 418 } 419 420 static bool id_forced(u16 device_id) 421 { 422 return device_id_in_list(device_id, xe_modparam.force_probe, false); 423 } 424 425 static bool id_blocked(u16 device_id) 426 { 427 return device_id_in_list(device_id, xe_modparam.force_probe, true); 428 } 429 430 static const struct xe_subplatform_desc * 431 find_subplatform(const struct xe_device *xe, const struct xe_device_desc *desc) 432 { 433 const struct xe_subplatform_desc *sp; 434 const u16 *id; 435 436 for (sp = desc->subplatforms; sp && sp->subplatform; sp++) 437 for (id = sp->pciidlist; *id; id++) 438 if (*id == xe->info.devid) 439 return sp; 440 441 return NULL; 442 } 443 444 enum xe_gmdid_type { 445 GMDID_GRAPHICS, 446 GMDID_MEDIA 447 }; 448 449 static void read_gmdid(struct xe_device *xe, enum xe_gmdid_type type, u32 *ver, u32 *revid) 450 { 451 struct xe_mmio *mmio = xe_root_tile_mmio(xe); 452 struct xe_reg gmdid_reg = GMD_ID; 453 u32 val; 454 455 KUNIT_STATIC_STUB_REDIRECT(read_gmdid, xe, type, ver, revid); 456 457 if (IS_SRIOV_VF(xe)) { 458 struct xe_gt *gt = xe_root_mmio_gt(xe); 459 460 /* 461 * To get the value of the GMDID register, VFs must obtain it 462 * from the GuC using MMIO communication. 463 * 464 * Note that at this point the xe_gt is not fully uninitialized 465 * and only basic access to MMIO registers is possible. To use 466 * our existing GuC communication functions we must perform at 467 * least basic xe_gt and xe_guc initialization. 468 * 469 * Since to obtain the value of GMDID_MEDIA we need to use the 470 * media GuC, temporarily tweak the gt type. 471 */ 472 xe_gt_assert(gt, gt->info.type == XE_GT_TYPE_UNINITIALIZED); 473 474 if (type == GMDID_MEDIA) { 475 gt->info.id = 1; 476 gt->info.type = XE_GT_TYPE_MEDIA; 477 } else { 478 gt->info.id = 0; 479 gt->info.type = XE_GT_TYPE_MAIN; 480 } 481 482 xe_gt_mmio_init(gt); 483 xe_guc_comm_init_early(>->uc.guc); 484 485 /* Don't bother with GMDID if failed to negotiate the GuC ABI */ 486 val = xe_gt_sriov_vf_bootstrap(gt) ? 0 : xe_gt_sriov_vf_gmdid(gt); 487 488 /* 489 * Only undo xe_gt.info here, the remaining changes made above 490 * will be overwritten as part of the regular initialization. 491 */ 492 gt->info.id = 0; 493 gt->info.type = XE_GT_TYPE_UNINITIALIZED; 494 } else { 495 /* 496 * GMD_ID is a GT register, but at this point in the driver 497 * init we haven't fully initialized the GT yet so we need to 498 * read the register with the tile's MMIO accessor. That means 499 * we need to apply the GSI offset manually since it won't get 500 * automatically added as it would if we were using a GT mmio 501 * accessor. 502 */ 503 if (type == GMDID_MEDIA) 504 gmdid_reg.addr += MEDIA_GT_GSI_OFFSET; 505 506 val = xe_mmio_read32(mmio, gmdid_reg); 507 } 508 509 *ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val) * 100 + REG_FIELD_GET(GMD_ID_RELEASE_MASK, val); 510 *revid = REG_FIELD_GET(GMD_ID_REVID, val); 511 } 512 513 /* 514 * Read IP version from hardware and select graphics/media IP descriptors 515 * based on the result. 516 */ 517 static void handle_gmdid(struct xe_device *xe, 518 const struct xe_ip **graphics_ip, 519 const struct xe_ip **media_ip, 520 u32 *graphics_revid, 521 u32 *media_revid) 522 { 523 u32 ver; 524 525 *graphics_ip = NULL; 526 *media_ip = NULL; 527 528 read_gmdid(xe, GMDID_GRAPHICS, &ver, graphics_revid); 529 530 for (int i = 0; i < ARRAY_SIZE(graphics_ips); i++) { 531 if (ver == graphics_ips[i].verx100) { 532 *graphics_ip = &graphics_ips[i]; 533 534 break; 535 } 536 } 537 538 if (!*graphics_ip) { 539 drm_err(&xe->drm, "Hardware reports unknown graphics version %u.%02u\n", 540 ver / 100, ver % 100); 541 } 542 543 read_gmdid(xe, GMDID_MEDIA, &ver, media_revid); 544 /* Media may legitimately be fused off / not present */ 545 if (ver == 0) 546 return; 547 548 for (int i = 0; i < ARRAY_SIZE(media_ips); i++) { 549 if (ver == media_ips[i].verx100) { 550 *media_ip = &media_ips[i]; 551 552 break; 553 } 554 } 555 556 if (!*media_ip) { 557 drm_err(&xe->drm, "Hardware reports unknown media version %u.%02u\n", 558 ver / 100, ver % 100); 559 } 560 } 561 562 /* 563 * Initialize device info content that only depends on static driver_data 564 * passed to the driver at probe time from PCI ID table. 565 */ 566 static int xe_info_init_early(struct xe_device *xe, 567 const struct xe_device_desc *desc, 568 const struct xe_subplatform_desc *subplatform_desc) 569 { 570 int err; 571 572 xe->info.platform_name = desc->platform_name; 573 xe->info.platform = desc->platform; 574 xe->info.subplatform = subplatform_desc ? 575 subplatform_desc->subplatform : XE_SUBPLATFORM_NONE; 576 577 xe->info.dma_mask_size = desc->dma_mask_size; 578 xe->info.is_dgfx = desc->is_dgfx; 579 xe->info.has_heci_gscfi = desc->has_heci_gscfi; 580 xe->info.has_heci_cscfi = desc->has_heci_cscfi; 581 xe->info.has_llc = desc->has_llc; 582 xe->info.has_pxp = desc->has_pxp; 583 xe->info.has_sriov = desc->has_sriov; 584 xe->info.skip_guc_pc = desc->skip_guc_pc; 585 xe->info.skip_mtcfg = desc->skip_mtcfg; 586 xe->info.skip_pcode = desc->skip_pcode; 587 588 xe->info.probe_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) && 589 xe_modparam.probe_display && 590 desc->has_display; 591 xe->info.tile_count = 1 + desc->max_remote_tiles; 592 593 err = xe_tile_init_early(xe_device_get_root_tile(xe), xe, 0); 594 if (err) 595 return err; 596 597 return 0; 598 } 599 600 /* 601 * Initialize device info content that does require knowledge about 602 * graphics / media IP version. 603 * Make sure that GT / tile structures allocated by the driver match the data 604 * present in device info. 605 */ 606 static int xe_info_init(struct xe_device *xe, 607 const struct xe_device_desc *desc) 608 { 609 u32 graphics_gmdid_revid = 0, media_gmdid_revid = 0; 610 const struct xe_ip *graphics_ip; 611 const struct xe_ip *media_ip; 612 const struct xe_graphics_desc *graphics_desc; 613 const struct xe_media_desc *media_desc; 614 struct xe_tile *tile; 615 struct xe_gt *gt; 616 u8 id; 617 618 /* 619 * If this platform supports GMD_ID, we'll detect the proper IP 620 * descriptor to use from hardware registers. 621 * desc->pre_gmdid_graphics_ip will only ever be set at this point for 622 * platforms before GMD_ID. In that case the IP descriptions and 623 * versions are simply derived from that. 624 */ 625 if (desc->pre_gmdid_graphics_ip) { 626 graphics_ip = desc->pre_gmdid_graphics_ip; 627 media_ip = desc->pre_gmdid_media_ip; 628 xe->info.step = xe_step_pre_gmdid_get(xe); 629 } else { 630 xe_assert(xe, !desc->pre_gmdid_media_ip); 631 handle_gmdid(xe, &graphics_ip, &media_ip, 632 &graphics_gmdid_revid, &media_gmdid_revid); 633 xe->info.step = xe_step_gmdid_get(xe, 634 graphics_gmdid_revid, 635 media_gmdid_revid); 636 } 637 638 /* 639 * If we couldn't detect the graphics IP, that's considered a fatal 640 * error and we should abort driver load. Failing to detect media 641 * IP is non-fatal; we'll just proceed without enabling media support. 642 */ 643 if (!graphics_ip) 644 return -ENODEV; 645 646 xe->info.graphics_verx100 = graphics_ip->verx100; 647 xe->info.graphics_name = graphics_ip->name; 648 graphics_desc = graphics_ip->desc; 649 650 if (media_ip) { 651 xe->info.media_verx100 = media_ip->verx100; 652 xe->info.media_name = media_ip->name; 653 media_desc = media_ip->desc; 654 } else { 655 xe->info.media_name = "none"; 656 media_desc = NULL; 657 } 658 659 xe->info.vram_flags = graphics_desc->vram_flags; 660 xe->info.va_bits = graphics_desc->va_bits; 661 xe->info.vm_max_level = graphics_desc->vm_max_level; 662 xe->info.has_asid = graphics_desc->has_asid; 663 xe->info.has_atomic_enable_pte_bit = graphics_desc->has_atomic_enable_pte_bit; 664 if (xe->info.platform != XE_PVC) 665 xe->info.has_device_atomics_on_smem = 1; 666 667 /* Runtime detection may change this later */ 668 xe->info.has_flat_ccs = graphics_desc->has_flat_ccs; 669 670 xe->info.has_range_tlb_invalidation = graphics_desc->has_range_tlb_invalidation; 671 xe->info.has_usm = graphics_desc->has_usm; 672 xe->info.has_64bit_timestamp = graphics_desc->has_64bit_timestamp; 673 674 for_each_remote_tile(tile, xe, id) { 675 int err; 676 677 err = xe_tile_init_early(tile, xe, id); 678 if (err) 679 return err; 680 } 681 682 /* 683 * All platforms have at least one primary GT. Any platform with media 684 * version 13 or higher has an additional dedicated media GT. And 685 * depending on the graphics IP there may be additional "remote tiles." 686 * All of these together determine the overall GT count. 687 */ 688 for_each_tile(tile, xe, id) { 689 gt = tile->primary_gt; 690 gt->info.id = xe->info.gt_count++; 691 gt->info.type = XE_GT_TYPE_MAIN; 692 gt->info.has_indirect_ring_state = graphics_desc->has_indirect_ring_state; 693 gt->info.engine_mask = graphics_desc->hw_engine_mask; 694 695 if (MEDIA_VER(xe) < 13 && media_desc) 696 gt->info.engine_mask |= media_desc->hw_engine_mask; 697 698 if (MEDIA_VER(xe) < 13 || !media_desc) 699 continue; 700 701 /* 702 * Allocate and setup media GT for platforms with standalone 703 * media. 704 */ 705 tile->media_gt = xe_gt_alloc(tile); 706 if (IS_ERR(tile->media_gt)) 707 return PTR_ERR(tile->media_gt); 708 709 gt = tile->media_gt; 710 gt->info.type = XE_GT_TYPE_MEDIA; 711 gt->info.has_indirect_ring_state = media_desc->has_indirect_ring_state; 712 gt->info.engine_mask = media_desc->hw_engine_mask; 713 714 /* 715 * FIXME: At the moment multi-tile and standalone media are 716 * mutually exclusive on current platforms. We'll need to 717 * come up with a better way to number GTs if we ever wind 718 * up with platforms that support both together. 719 */ 720 drm_WARN_ON(&xe->drm, id != 0); 721 gt->info.id = xe->info.gt_count++; 722 } 723 724 return 0; 725 } 726 727 static void xe_pci_remove(struct pci_dev *pdev) 728 { 729 struct xe_device *xe = pdev_to_xe_device(pdev); 730 731 if (IS_SRIOV_PF(xe)) 732 xe_pci_sriov_configure(pdev, 0); 733 734 if (xe_survivability_mode_is_enabled(xe)) 735 return; 736 737 xe_device_remove(xe); 738 xe_pm_runtime_fini(xe); 739 } 740 741 /* 742 * Probe the PCI device, initialize various parts of the driver. 743 * 744 * Fault injection is used to test the error paths of some initialization 745 * functions called either directly from xe_pci_probe() or indirectly for 746 * example through xe_device_probe(). Those functions use the kernel fault 747 * injection capabilities infrastructure, see 748 * Documentation/fault-injection/fault-injection.rst for details. The macro 749 * ALLOW_ERROR_INJECTION() is used to conditionally skip function execution 750 * at runtime and use a provided return value. The first requirement for 751 * error injectable functions is proper handling of the error code by the 752 * caller for recovery, which is always the case here. The second 753 * requirement is that no state is changed before the first error return. 754 * It is not strictly fulfilled for all initialization functions using the 755 * ALLOW_ERROR_INJECTION() macro but this is acceptable because for those 756 * error cases at probe time, the error code is simply propagated up by the 757 * caller. Therefore there is no consequence on those specific callers when 758 * function error injection skips the whole function. 759 */ 760 static int xe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 761 { 762 const struct xe_device_desc *desc = (const void *)ent->driver_data; 763 const struct xe_subplatform_desc *subplatform_desc; 764 struct xe_device *xe; 765 int err; 766 767 if (desc->require_force_probe && !id_forced(pdev->device)) { 768 dev_info(&pdev->dev, 769 "Your graphics device %04x is not officially supported\n" 770 "by xe driver in this kernel version. To force Xe probe,\n" 771 "use xe.force_probe='%04x' and i915.force_probe='!%04x'\n" 772 "module parameters or CONFIG_DRM_XE_FORCE_PROBE='%04x' and\n" 773 "CONFIG_DRM_I915_FORCE_PROBE='!%04x' configuration options.\n", 774 pdev->device, pdev->device, pdev->device, 775 pdev->device, pdev->device); 776 return -ENODEV; 777 } 778 779 if (id_blocked(pdev->device)) { 780 dev_info(&pdev->dev, "Probe blocked for device [%04x:%04x].\n", 781 pdev->vendor, pdev->device); 782 return -ENODEV; 783 } 784 785 if (xe_display_driver_probe_defer(pdev)) 786 return -EPROBE_DEFER; 787 788 err = pcim_enable_device(pdev); 789 if (err) 790 return err; 791 792 xe = xe_device_create(pdev, ent); 793 if (IS_ERR(xe)) 794 return PTR_ERR(xe); 795 796 pci_set_drvdata(pdev, &xe->drm); 797 798 xe_pm_assert_unbounded_bridge(xe); 799 subplatform_desc = find_subplatform(xe, desc); 800 801 pci_set_master(pdev); 802 803 err = xe_info_init_early(xe, desc, subplatform_desc); 804 if (err) 805 return err; 806 807 err = xe_device_probe_early(xe); 808 if (err) { 809 /* 810 * In Boot Survivability mode, no drm card is exposed and driver 811 * is loaded with bare minimum to allow for firmware to be 812 * flashed through mei. If early probe failed, but it managed to 813 * enable survivability mode, return success. 814 */ 815 if (xe_survivability_mode_is_enabled(xe)) 816 return 0; 817 818 return err; 819 } 820 821 err = xe_info_init(xe, desc); 822 if (err) 823 return err; 824 825 err = xe_display_probe(xe); 826 if (err) 827 return err; 828 829 drm_dbg(&xe->drm, "%s %s %04x:%04x dgfx:%d gfx:%s (%d.%02d) media:%s (%d.%02d) display:%s dma_m_s:%d tc:%d gscfi:%d cscfi:%d", 830 desc->platform_name, 831 subplatform_desc ? subplatform_desc->name : "", 832 xe->info.devid, xe->info.revid, 833 xe->info.is_dgfx, 834 xe->info.graphics_name, 835 xe->info.graphics_verx100 / 100, 836 xe->info.graphics_verx100 % 100, 837 xe->info.media_name, 838 xe->info.media_verx100 / 100, 839 xe->info.media_verx100 % 100, 840 str_yes_no(xe->info.probe_display), 841 xe->info.dma_mask_size, xe->info.tile_count, 842 xe->info.has_heci_gscfi, xe->info.has_heci_cscfi); 843 844 drm_dbg(&xe->drm, "Stepping = (G:%s, M:%s, B:%s)\n", 845 xe_step_name(xe->info.step.graphics), 846 xe_step_name(xe->info.step.media), 847 xe_step_name(xe->info.step.basedie)); 848 849 drm_dbg(&xe->drm, "SR-IOV support: %s (mode: %s)\n", 850 str_yes_no(xe_device_has_sriov(xe)), 851 xe_sriov_mode_to_string(xe_device_sriov_mode(xe))); 852 853 err = xe_pm_init_early(xe); 854 if (err) 855 return err; 856 857 err = xe_device_probe(xe); 858 if (err) 859 return err; 860 861 err = xe_pm_init(xe); 862 if (err) 863 goto err_driver_cleanup; 864 865 drm_dbg(&xe->drm, "d3cold: capable=%s\n", 866 str_yes_no(xe->d3cold.capable)); 867 868 return 0; 869 870 err_driver_cleanup: 871 xe_pci_remove(pdev); 872 return err; 873 } 874 875 static void xe_pci_shutdown(struct pci_dev *pdev) 876 { 877 xe_device_shutdown(pdev_to_xe_device(pdev)); 878 } 879 880 #ifdef CONFIG_PM_SLEEP 881 static void d3cold_toggle(struct pci_dev *pdev, enum toggle_d3cold toggle) 882 { 883 struct xe_device *xe = pdev_to_xe_device(pdev); 884 struct pci_dev *root_pdev; 885 886 if (!xe->d3cold.capable) 887 return; 888 889 root_pdev = pcie_find_root_port(pdev); 890 if (!root_pdev) 891 return; 892 893 switch (toggle) { 894 case D3COLD_DISABLE: 895 pci_d3cold_disable(root_pdev); 896 break; 897 case D3COLD_ENABLE: 898 pci_d3cold_enable(root_pdev); 899 break; 900 } 901 } 902 903 static int xe_pci_suspend(struct device *dev) 904 { 905 struct pci_dev *pdev = to_pci_dev(dev); 906 struct xe_device *xe = pdev_to_xe_device(pdev); 907 int err; 908 909 if (xe_survivability_mode_is_enabled(xe)) 910 return -EBUSY; 911 912 err = xe_pm_suspend(xe); 913 if (err) 914 return err; 915 916 /* 917 * Enabling D3Cold is needed for S2Idle/S0ix. 918 * It is save to allow here since xe_pm_suspend has evicted 919 * the local memory and the direct complete optimization is disabled. 920 */ 921 d3cold_toggle(pdev, D3COLD_ENABLE); 922 923 pci_save_state(pdev); 924 pci_disable_device(pdev); 925 926 return 0; 927 } 928 929 static int xe_pci_resume(struct device *dev) 930 { 931 struct pci_dev *pdev = to_pci_dev(dev); 932 int err; 933 934 /* Give back the D3Cold decision to the runtime P M*/ 935 d3cold_toggle(pdev, D3COLD_DISABLE); 936 937 err = pci_set_power_state(pdev, PCI_D0); 938 if (err) 939 return err; 940 941 pci_restore_state(pdev); 942 943 err = pci_enable_device(pdev); 944 if (err) 945 return err; 946 947 pci_set_master(pdev); 948 949 err = xe_pm_resume(pdev_to_xe_device(pdev)); 950 if (err) 951 return err; 952 953 return 0; 954 } 955 956 static int xe_pci_runtime_suspend(struct device *dev) 957 { 958 struct pci_dev *pdev = to_pci_dev(dev); 959 struct xe_device *xe = pdev_to_xe_device(pdev); 960 int err; 961 962 err = xe_pm_runtime_suspend(xe); 963 if (err) 964 return err; 965 966 pci_save_state(pdev); 967 968 if (xe->d3cold.allowed) { 969 d3cold_toggle(pdev, D3COLD_ENABLE); 970 pci_disable_device(pdev); 971 pci_ignore_hotplug(pdev); 972 pci_set_power_state(pdev, PCI_D3cold); 973 } else { 974 d3cold_toggle(pdev, D3COLD_DISABLE); 975 pci_set_power_state(pdev, PCI_D3hot); 976 } 977 978 return 0; 979 } 980 981 static int xe_pci_runtime_resume(struct device *dev) 982 { 983 struct pci_dev *pdev = to_pci_dev(dev); 984 struct xe_device *xe = pdev_to_xe_device(pdev); 985 int err; 986 987 err = pci_set_power_state(pdev, PCI_D0); 988 if (err) 989 return err; 990 991 pci_restore_state(pdev); 992 993 if (xe->d3cold.allowed) { 994 err = pci_enable_device(pdev); 995 if (err) 996 return err; 997 998 pci_set_master(pdev); 999 } 1000 1001 return xe_pm_runtime_resume(xe); 1002 } 1003 1004 static int xe_pci_runtime_idle(struct device *dev) 1005 { 1006 struct pci_dev *pdev = to_pci_dev(dev); 1007 struct xe_device *xe = pdev_to_xe_device(pdev); 1008 1009 xe_pm_d3cold_allowed_toggle(xe); 1010 1011 return 0; 1012 } 1013 1014 static const struct dev_pm_ops xe_pm_ops = { 1015 SET_SYSTEM_SLEEP_PM_OPS(xe_pci_suspend, xe_pci_resume) 1016 SET_RUNTIME_PM_OPS(xe_pci_runtime_suspend, xe_pci_runtime_resume, xe_pci_runtime_idle) 1017 }; 1018 #endif 1019 1020 static struct pci_driver xe_pci_driver = { 1021 .name = DRIVER_NAME, 1022 .id_table = pciidlist, 1023 .probe = xe_pci_probe, 1024 .remove = xe_pci_remove, 1025 .shutdown = xe_pci_shutdown, 1026 .sriov_configure = xe_pci_sriov_configure, 1027 #ifdef CONFIG_PM_SLEEP 1028 .driver.pm = &xe_pm_ops, 1029 #endif 1030 }; 1031 1032 int xe_register_pci_driver(void) 1033 { 1034 return pci_register_driver(&xe_pci_driver); 1035 } 1036 1037 void xe_unregister_pci_driver(void) 1038 { 1039 pci_unregister_driver(&xe_pci_driver); 1040 } 1041 1042 #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST) 1043 #include "tests/xe_pci.c" 1044 #endif 1045