1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #include "xe_pat.h" 7 8 #include <uapi/drm/xe_drm.h> 9 10 #include <generated/xe_wa_oob.h> 11 12 #include "regs/xe_reg_defs.h" 13 #include "xe_assert.h" 14 #include "xe_device.h" 15 #include "xe_force_wake.h" 16 #include "xe_gt.h" 17 #include "xe_gt_mcr.h" 18 #include "xe_mmio.h" 19 #include "xe_sriov.h" 20 #include "xe_wa.h" 21 22 #define _PAT_ATS 0x47fc 23 #define _PAT_INDEX(index) _PICK_EVEN_2RANGES(index, 8, \ 24 0x4800, 0x4804, \ 25 0x4848, 0x484c) 26 #define _PAT_PTA 0x4820 27 28 #define XE2_NO_PROMOTE REG_BIT(10) 29 #define XE2_COMP_EN REG_BIT(9) 30 #define XE2_L3_CLOS REG_GENMASK(7, 6) 31 #define XE2_L3_POLICY REG_GENMASK(5, 4) 32 #define XE2_L4_POLICY REG_GENMASK(3, 2) 33 #define XE2_COH_MODE REG_GENMASK(1, 0) 34 35 #define XELPG_L4_POLICY_MASK REG_GENMASK(3, 2) 36 #define XELPG_PAT_3_UC REG_FIELD_PREP(XELPG_L4_POLICY_MASK, 3) 37 #define XELPG_PAT_1_WT REG_FIELD_PREP(XELPG_L4_POLICY_MASK, 1) 38 #define XELPG_PAT_0_WB REG_FIELD_PREP(XELPG_L4_POLICY_MASK, 0) 39 #define XELPG_INDEX_COH_MODE_MASK REG_GENMASK(1, 0) 40 #define XELPG_3_COH_2W REG_FIELD_PREP(XELPG_INDEX_COH_MODE_MASK, 3) 41 #define XELPG_2_COH_1W REG_FIELD_PREP(XELPG_INDEX_COH_MODE_MASK, 2) 42 #define XELPG_0_COH_NON REG_FIELD_PREP(XELPG_INDEX_COH_MODE_MASK, 0) 43 44 #define XEHPC_CLOS_LEVEL_MASK REG_GENMASK(3, 2) 45 #define XEHPC_PAT_CLOS(x) REG_FIELD_PREP(XEHPC_CLOS_LEVEL_MASK, x) 46 47 #define XELP_MEM_TYPE_MASK REG_GENMASK(1, 0) 48 #define XELP_PAT_WB REG_FIELD_PREP(XELP_MEM_TYPE_MASK, 3) 49 #define XELP_PAT_WT REG_FIELD_PREP(XELP_MEM_TYPE_MASK, 2) 50 #define XELP_PAT_WC REG_FIELD_PREP(XELP_MEM_TYPE_MASK, 1) 51 #define XELP_PAT_UC REG_FIELD_PREP(XELP_MEM_TYPE_MASK, 0) 52 53 static const char *XELP_MEM_TYPE_STR_MAP[] = { "UC", "WC", "WT", "WB" }; 54 55 struct xe_pat_ops { 56 void (*program_graphics)(struct xe_gt *gt, const struct xe_pat_table_entry table[], 57 int n_entries); 58 void (*program_media)(struct xe_gt *gt, const struct xe_pat_table_entry table[], 59 int n_entries); 60 int (*dump)(struct xe_gt *gt, struct drm_printer *p); 61 }; 62 63 static const struct xe_pat_table_entry xelp_pat_table[] = { 64 [0] = { XELP_PAT_WB, XE_COH_AT_LEAST_1WAY }, 65 [1] = { XELP_PAT_WC, XE_COH_NONE }, 66 [2] = { XELP_PAT_WT, XE_COH_NONE }, 67 [3] = { XELP_PAT_UC, XE_COH_NONE }, 68 }; 69 70 static const struct xe_pat_table_entry xehpc_pat_table[] = { 71 [0] = { XELP_PAT_UC, XE_COH_NONE }, 72 [1] = { XELP_PAT_WC, XE_COH_NONE }, 73 [2] = { XELP_PAT_WT, XE_COH_NONE }, 74 [3] = { XELP_PAT_WB, XE_COH_AT_LEAST_1WAY }, 75 [4] = { XEHPC_PAT_CLOS(1) | XELP_PAT_WT, XE_COH_NONE }, 76 [5] = { XEHPC_PAT_CLOS(1) | XELP_PAT_WB, XE_COH_AT_LEAST_1WAY }, 77 [6] = { XEHPC_PAT_CLOS(2) | XELP_PAT_WT, XE_COH_NONE }, 78 [7] = { XEHPC_PAT_CLOS(2) | XELP_PAT_WB, XE_COH_AT_LEAST_1WAY }, 79 }; 80 81 static const struct xe_pat_table_entry xelpg_pat_table[] = { 82 [0] = { XELPG_PAT_0_WB, XE_COH_NONE }, 83 [1] = { XELPG_PAT_1_WT, XE_COH_NONE }, 84 [2] = { XELPG_PAT_3_UC, XE_COH_NONE }, 85 [3] = { XELPG_PAT_0_WB | XELPG_2_COH_1W, XE_COH_AT_LEAST_1WAY }, 86 [4] = { XELPG_PAT_0_WB | XELPG_3_COH_2W, XE_COH_AT_LEAST_1WAY }, 87 }; 88 89 /* 90 * The Xe2 table is getting large/complicated so it's easier to review if 91 * provided in a form that exactly matches the bspec's formatting. The meaning 92 * of the fields here are: 93 * - no_promote: 0=promotable, 1=no promote 94 * - comp_en: 0=disable, 1=enable 95 * - l3clos: L3 class of service (0-3) 96 * - l3_policy: 0=WB, 1=XD ("WB - Transient Display"), 3=UC 97 * - l4_policy: 0=WB, 1=WT, 3=UC 98 * - coh_mode: 0=no snoop, 2=1-way coherent, 3=2-way coherent 99 * 100 * Reserved entries should be programmed with the maximum caching, minimum 101 * coherency (which matches an all-0's encoding), so we can just omit them 102 * in the table. 103 * 104 * Note: There is an implicit assumption in the driver that compression and 105 * coh_1way+ are mutually exclusive. If this is ever not true then userptr 106 * and imported dma-buf from external device will have uncleared ccs state. See 107 * also xe_bo_needs_ccs_pages(). 108 */ 109 #define XE2_PAT(no_promote, comp_en, l3clos, l3_policy, l4_policy, __coh_mode) \ 110 { \ 111 .value = (no_promote ? XE2_NO_PROMOTE : 0) | \ 112 (comp_en ? XE2_COMP_EN : 0) | \ 113 REG_FIELD_PREP(XE2_L3_CLOS, l3clos) | \ 114 REG_FIELD_PREP(XE2_L3_POLICY, l3_policy) | \ 115 REG_FIELD_PREP(XE2_L4_POLICY, l4_policy) | \ 116 REG_FIELD_PREP(XE2_COH_MODE, __coh_mode), \ 117 .coh_mode = (BUILD_BUG_ON_ZERO(__coh_mode && comp_en) || __coh_mode) ? \ 118 XE_COH_AT_LEAST_1WAY : XE_COH_NONE \ 119 } 120 121 static const struct xe_pat_table_entry xe2_pat_table[] = { 122 [ 0] = XE2_PAT( 0, 0, 0, 0, 3, 0 ), 123 [ 1] = XE2_PAT( 0, 0, 0, 0, 3, 2 ), 124 [ 2] = XE2_PAT( 0, 0, 0, 0, 3, 3 ), 125 [ 3] = XE2_PAT( 0, 0, 0, 3, 3, 0 ), 126 [ 4] = XE2_PAT( 0, 0, 0, 3, 0, 2 ), 127 [ 5] = XE2_PAT( 0, 0, 0, 3, 3, 2 ), 128 [ 6] = XE2_PAT( 1, 0, 0, 1, 3, 0 ), 129 [ 7] = XE2_PAT( 0, 0, 0, 3, 0, 3 ), 130 [ 8] = XE2_PAT( 0, 0, 0, 3, 0, 0 ), 131 [ 9] = XE2_PAT( 0, 1, 0, 0, 3, 0 ), 132 [10] = XE2_PAT( 0, 1, 0, 3, 0, 0 ), 133 [11] = XE2_PAT( 1, 1, 0, 1, 3, 0 ), 134 [12] = XE2_PAT( 0, 1, 0, 3, 3, 0 ), 135 [13] = XE2_PAT( 0, 0, 0, 0, 0, 0 ), 136 [14] = XE2_PAT( 0, 1, 0, 0, 0, 0 ), 137 [15] = XE2_PAT( 1, 1, 0, 1, 1, 0 ), 138 /* 16..19 are reserved; leave set to all 0's */ 139 [20] = XE2_PAT( 0, 0, 1, 0, 3, 0 ), 140 [21] = XE2_PAT( 0, 1, 1, 0, 3, 0 ), 141 [22] = XE2_PAT( 0, 0, 1, 0, 3, 2 ), 142 [23] = XE2_PAT( 0, 0, 1, 0, 3, 3 ), 143 [24] = XE2_PAT( 0, 0, 2, 0, 3, 0 ), 144 [25] = XE2_PAT( 0, 1, 2, 0, 3, 0 ), 145 [26] = XE2_PAT( 0, 0, 2, 0, 3, 2 ), 146 [27] = XE2_PAT( 0, 0, 2, 0, 3, 3 ), 147 [28] = XE2_PAT( 0, 0, 3, 0, 3, 0 ), 148 [29] = XE2_PAT( 0, 1, 3, 0, 3, 0 ), 149 [30] = XE2_PAT( 0, 0, 3, 0, 3, 2 ), 150 [31] = XE2_PAT( 0, 0, 3, 0, 3, 3 ), 151 }; 152 153 /* Special PAT values programmed outside the main table */ 154 static const struct xe_pat_table_entry xe2_pat_ats = XE2_PAT( 0, 0, 0, 0, 3, 3 ); 155 static const struct xe_pat_table_entry xe2_pat_pta = XE2_PAT( 0, 0, 0, 0, 3, 0 ); 156 157 /* 158 * Xe3p_XPC PAT table uses the same layout as Xe2/Xe3, except that there's no 159 * option for compression. Also note that the "L3" and "L4" register fields 160 * actually control L2 and L3 cache respectively on this platform. 161 */ 162 #define XE3P_XPC_PAT(no_promote, l3clos, l3_policy, l4_policy, __coh_mode) \ 163 XE2_PAT(no_promote, 0, l3clos, l3_policy, l4_policy, __coh_mode) 164 165 static const struct xe_pat_table_entry xe3p_xpc_pat_ats = XE3P_XPC_PAT( 0, 0, 0, 0, 3 ); 166 static const struct xe_pat_table_entry xe3p_xpc_pat_pta = XE3P_XPC_PAT( 0, 0, 0, 0, 0 ); 167 168 static const struct xe_pat_table_entry xe3p_xpc_pat_table[] = { 169 [ 0] = XE3P_XPC_PAT( 0, 0, 0, 0, 0 ), 170 [ 1] = XE3P_XPC_PAT( 0, 0, 0, 0, 2 ), 171 [ 2] = XE3P_XPC_PAT( 0, 0, 0, 0, 3 ), 172 [ 3] = XE3P_XPC_PAT( 0, 0, 3, 3, 0 ), 173 [ 4] = XE3P_XPC_PAT( 0, 0, 3, 3, 2 ), 174 [ 5] = XE3P_XPC_PAT( 0, 0, 3, 0, 0 ), 175 [ 6] = XE3P_XPC_PAT( 0, 0, 3, 0, 2 ), 176 [ 7] = XE3P_XPC_PAT( 0, 0, 3, 0, 3 ), 177 [ 8] = XE3P_XPC_PAT( 0, 0, 0, 3, 0 ), 178 [ 9] = XE3P_XPC_PAT( 0, 0, 0, 3, 2 ), 179 [10] = XE3P_XPC_PAT( 0, 0, 0, 3, 3 ), 180 /* 11..22 are reserved; leave set to all 0's */ 181 [23] = XE3P_XPC_PAT( 0, 1, 0, 0, 0 ), 182 [24] = XE3P_XPC_PAT( 0, 1, 0, 0, 2 ), 183 [25] = XE3P_XPC_PAT( 0, 1, 0, 0, 3 ), 184 [26] = XE3P_XPC_PAT( 0, 2, 0, 0, 0 ), 185 [27] = XE3P_XPC_PAT( 0, 2, 0, 0, 2 ), 186 [28] = XE3P_XPC_PAT( 0, 2, 0, 0, 3 ), 187 [29] = XE3P_XPC_PAT( 0, 3, 0, 0, 0 ), 188 [30] = XE3P_XPC_PAT( 0, 3, 0, 0, 2 ), 189 [31] = XE3P_XPC_PAT( 0, 3, 0, 0, 3 ), 190 }; 191 192 u16 xe_pat_index_get_coh_mode(struct xe_device *xe, u16 pat_index) 193 { 194 WARN_ON(pat_index >= xe->pat.n_entries); 195 return xe->pat.table[pat_index].coh_mode; 196 } 197 198 static void program_pat(struct xe_gt *gt, const struct xe_pat_table_entry table[], 199 int n_entries) 200 { 201 struct xe_device *xe = gt_to_xe(gt); 202 203 for (int i = 0; i < n_entries; i++) { 204 struct xe_reg reg = XE_REG(_PAT_INDEX(i)); 205 206 xe_mmio_write32(>->mmio, reg, table[i].value); 207 } 208 209 if (xe->pat.pat_ats) 210 xe_mmio_write32(>->mmio, XE_REG(_PAT_ATS), xe->pat.pat_ats->value); 211 if (xe->pat.pat_pta) 212 xe_mmio_write32(>->mmio, XE_REG(_PAT_PTA), xe->pat.pat_pta->value); 213 } 214 215 static void program_pat_mcr(struct xe_gt *gt, const struct xe_pat_table_entry table[], 216 int n_entries) 217 { 218 struct xe_device *xe = gt_to_xe(gt); 219 220 for (int i = 0; i < n_entries; i++) { 221 struct xe_reg_mcr reg_mcr = XE_REG_MCR(_PAT_INDEX(i)); 222 223 xe_gt_mcr_multicast_write(gt, reg_mcr, table[i].value); 224 } 225 226 if (xe->pat.pat_ats) 227 xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_ATS), xe->pat.pat_ats->value); 228 if (xe->pat.pat_pta) 229 xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_PTA), xe->pat.pat_pta->value); 230 } 231 232 static int xelp_dump(struct xe_gt *gt, struct drm_printer *p) 233 { 234 struct xe_device *xe = gt_to_xe(gt); 235 unsigned int fw_ref; 236 int i; 237 238 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 239 if (!fw_ref) 240 return -ETIMEDOUT; 241 242 drm_printf(p, "PAT table:\n"); 243 244 for (i = 0; i < xe->pat.n_entries; i++) { 245 u32 pat = xe_mmio_read32(>->mmio, XE_REG(_PAT_INDEX(i))); 246 u8 mem_type = REG_FIELD_GET(XELP_MEM_TYPE_MASK, pat); 247 248 drm_printf(p, "PAT[%2d] = %s (%#8x)\n", i, 249 XELP_MEM_TYPE_STR_MAP[mem_type], pat); 250 } 251 252 xe_force_wake_put(gt_to_fw(gt), fw_ref); 253 return 0; 254 } 255 256 static const struct xe_pat_ops xelp_pat_ops = { 257 .program_graphics = program_pat, 258 .dump = xelp_dump, 259 }; 260 261 static int xehp_dump(struct xe_gt *gt, struct drm_printer *p) 262 { 263 struct xe_device *xe = gt_to_xe(gt); 264 unsigned int fw_ref; 265 int i; 266 267 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 268 if (!fw_ref) 269 return -ETIMEDOUT; 270 271 drm_printf(p, "PAT table:\n"); 272 273 for (i = 0; i < xe->pat.n_entries; i++) { 274 u32 pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i))); 275 u8 mem_type; 276 277 mem_type = REG_FIELD_GET(XELP_MEM_TYPE_MASK, pat); 278 279 drm_printf(p, "PAT[%2d] = %s (%#8x)\n", i, 280 XELP_MEM_TYPE_STR_MAP[mem_type], pat); 281 } 282 283 xe_force_wake_put(gt_to_fw(gt), fw_ref); 284 return 0; 285 } 286 287 static const struct xe_pat_ops xehp_pat_ops = { 288 .program_graphics = program_pat_mcr, 289 .dump = xehp_dump, 290 }; 291 292 static int xehpc_dump(struct xe_gt *gt, struct drm_printer *p) 293 { 294 struct xe_device *xe = gt_to_xe(gt); 295 unsigned int fw_ref; 296 int i; 297 298 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 299 if (!fw_ref) 300 return -ETIMEDOUT; 301 302 drm_printf(p, "PAT table:\n"); 303 304 for (i = 0; i < xe->pat.n_entries; i++) { 305 u32 pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i))); 306 307 drm_printf(p, "PAT[%2d] = [ %u, %u ] (%#8x)\n", i, 308 REG_FIELD_GET(XELP_MEM_TYPE_MASK, pat), 309 REG_FIELD_GET(XEHPC_CLOS_LEVEL_MASK, pat), pat); 310 } 311 312 xe_force_wake_put(gt_to_fw(gt), fw_ref); 313 return 0; 314 } 315 316 static const struct xe_pat_ops xehpc_pat_ops = { 317 .program_graphics = program_pat_mcr, 318 .dump = xehpc_dump, 319 }; 320 321 static int xelpg_dump(struct xe_gt *gt, struct drm_printer *p) 322 { 323 struct xe_device *xe = gt_to_xe(gt); 324 unsigned int fw_ref; 325 int i; 326 327 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 328 if (!fw_ref) 329 return -ETIMEDOUT; 330 331 drm_printf(p, "PAT table:\n"); 332 333 for (i = 0; i < xe->pat.n_entries; i++) { 334 u32 pat; 335 336 if (xe_gt_is_media_type(gt)) 337 pat = xe_mmio_read32(>->mmio, XE_REG(_PAT_INDEX(i))); 338 else 339 pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i))); 340 341 drm_printf(p, "PAT[%2d] = [ %u, %u ] (%#8x)\n", i, 342 REG_FIELD_GET(XELPG_L4_POLICY_MASK, pat), 343 REG_FIELD_GET(XELPG_INDEX_COH_MODE_MASK, pat), pat); 344 } 345 346 xe_force_wake_put(gt_to_fw(gt), fw_ref); 347 return 0; 348 } 349 350 /* 351 * SAMedia register offsets are adjusted by the write methods and they target 352 * registers that are not MCR, while for normal GT they are MCR 353 */ 354 static const struct xe_pat_ops xelpg_pat_ops = { 355 .program_graphics = program_pat, 356 .program_media = program_pat_mcr, 357 .dump = xelpg_dump, 358 }; 359 360 static int xe2_dump(struct xe_gt *gt, struct drm_printer *p) 361 { 362 struct xe_device *xe = gt_to_xe(gt); 363 unsigned int fw_ref; 364 u32 pat; 365 int i; 366 367 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 368 if (!fw_ref) 369 return -ETIMEDOUT; 370 371 drm_printf(p, "PAT table:\n"); 372 373 for (i = 0; i < xe->pat.n_entries; i++) { 374 if (xe_gt_is_media_type(gt)) 375 pat = xe_mmio_read32(>->mmio, XE_REG(_PAT_INDEX(i))); 376 else 377 pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i))); 378 379 drm_printf(p, "PAT[%2d] = [ %u, %u, %u, %u, %u, %u ] (%#8x)\n", i, 380 !!(pat & XE2_NO_PROMOTE), 381 !!(pat & XE2_COMP_EN), 382 REG_FIELD_GET(XE2_L3_CLOS, pat), 383 REG_FIELD_GET(XE2_L3_POLICY, pat), 384 REG_FIELD_GET(XE2_L4_POLICY, pat), 385 REG_FIELD_GET(XE2_COH_MODE, pat), 386 pat); 387 } 388 389 /* 390 * Also print PTA_MODE, which describes how the hardware accesses 391 * PPGTT entries. 392 */ 393 if (xe_gt_is_media_type(gt)) 394 pat = xe_mmio_read32(>->mmio, XE_REG(_PAT_PTA)); 395 else 396 pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_PTA)); 397 398 drm_printf(p, "Page Table Access:\n"); 399 drm_printf(p, "PTA_MODE= [ %u, %u, %u, %u, %u, %u ] (%#8x)\n", 400 !!(pat & XE2_NO_PROMOTE), 401 !!(pat & XE2_COMP_EN), 402 REG_FIELD_GET(XE2_L3_CLOS, pat), 403 REG_FIELD_GET(XE2_L3_POLICY, pat), 404 REG_FIELD_GET(XE2_L4_POLICY, pat), 405 REG_FIELD_GET(XE2_COH_MODE, pat), 406 pat); 407 408 xe_force_wake_put(gt_to_fw(gt), fw_ref); 409 return 0; 410 } 411 412 static const struct xe_pat_ops xe2_pat_ops = { 413 .program_graphics = program_pat_mcr, 414 .program_media = program_pat, 415 .dump = xe2_dump, 416 }; 417 418 static int xe3p_xpc_dump(struct xe_gt *gt, struct drm_printer *p) 419 { 420 struct xe_device *xe = gt_to_xe(gt); 421 unsigned int fw_ref; 422 u32 pat; 423 int i; 424 425 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 426 if (!fw_ref) 427 return -ETIMEDOUT; 428 429 drm_printf(p, "PAT table:\n"); 430 431 for (i = 0; i < xe->pat.n_entries; i++) { 432 pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i))); 433 434 drm_printf(p, "PAT[%2d] = [ %u, %u, %u, %u, %u ] (%#8x)\n", i, 435 !!(pat & XE2_NO_PROMOTE), 436 REG_FIELD_GET(XE2_L3_CLOS, pat), 437 REG_FIELD_GET(XE2_L3_POLICY, pat), 438 REG_FIELD_GET(XE2_L4_POLICY, pat), 439 REG_FIELD_GET(XE2_COH_MODE, pat), 440 pat); 441 } 442 443 /* 444 * Also print PTA_MODE, which describes how the hardware accesses 445 * PPGTT entries. 446 */ 447 pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_PTA)); 448 449 drm_printf(p, "Page Table Access:\n"); 450 drm_printf(p, "PTA_MODE= [ %u, %u, %u, %u, %u ] (%#8x)\n", 451 !!(pat & XE2_NO_PROMOTE), 452 REG_FIELD_GET(XE2_L3_CLOS, pat), 453 REG_FIELD_GET(XE2_L3_POLICY, pat), 454 REG_FIELD_GET(XE2_L4_POLICY, pat), 455 REG_FIELD_GET(XE2_COH_MODE, pat), 456 pat); 457 458 xe_force_wake_put(gt_to_fw(gt), fw_ref); 459 return 0; 460 } 461 462 static const struct xe_pat_ops xe3p_xpc_pat_ops = { 463 .program_graphics = program_pat_mcr, 464 .program_media = program_pat, 465 .dump = xe3p_xpc_dump, 466 }; 467 468 void xe_pat_init_early(struct xe_device *xe) 469 { 470 if (GRAPHICS_VERx100(xe) == 3511) { 471 xe->pat.ops = &xe3p_xpc_pat_ops; 472 xe->pat.table = xe3p_xpc_pat_table; 473 xe->pat.pat_ats = &xe3p_xpc_pat_ats; 474 xe->pat.pat_pta = &xe3p_xpc_pat_pta; 475 xe->pat.n_entries = ARRAY_SIZE(xe3p_xpc_pat_table); 476 xe->pat.idx[XE_CACHE_NONE] = 3; 477 xe->pat.idx[XE_CACHE_WT] = 3; /* N/A (no display); use UC */ 478 xe->pat.idx[XE_CACHE_WB] = 2; 479 } else if (GRAPHICS_VER(xe) == 30 || GRAPHICS_VER(xe) == 20) { 480 xe->pat.ops = &xe2_pat_ops; 481 xe->pat.table = xe2_pat_table; 482 xe->pat.pat_ats = &xe2_pat_ats; 483 if (IS_DGFX(xe)) 484 xe->pat.pat_pta = &xe2_pat_pta; 485 486 /* Wa_16023588340. XXX: Should use XE_WA */ 487 if (GRAPHICS_VERx100(xe) == 2001) 488 xe->pat.n_entries = 28; /* Disable CLOS3 */ 489 else 490 xe->pat.n_entries = ARRAY_SIZE(xe2_pat_table); 491 492 xe->pat.idx[XE_CACHE_NONE] = 3; 493 xe->pat.idx[XE_CACHE_WT] = 15; 494 xe->pat.idx[XE_CACHE_WB] = 2; 495 xe->pat.idx[XE_CACHE_NONE_COMPRESSION] = 12; /*Applicable on xe2 and beyond */ 496 } else if (xe->info.platform == XE_METEORLAKE) { 497 xe->pat.ops = &xelpg_pat_ops; 498 xe->pat.table = xelpg_pat_table; 499 xe->pat.n_entries = ARRAY_SIZE(xelpg_pat_table); 500 xe->pat.idx[XE_CACHE_NONE] = 2; 501 xe->pat.idx[XE_CACHE_WT] = 1; 502 xe->pat.idx[XE_CACHE_WB] = 3; 503 } else if (xe->info.platform == XE_PVC) { 504 xe->pat.ops = &xehpc_pat_ops; 505 xe->pat.table = xehpc_pat_table; 506 xe->pat.n_entries = ARRAY_SIZE(xehpc_pat_table); 507 xe->pat.idx[XE_CACHE_NONE] = 0; 508 xe->pat.idx[XE_CACHE_WT] = 2; 509 xe->pat.idx[XE_CACHE_WB] = 3; 510 } else if (xe->info.platform == XE_DG2) { 511 /* 512 * Table is the same as previous platforms, but programming 513 * method has changed. 514 */ 515 xe->pat.ops = &xehp_pat_ops; 516 xe->pat.table = xelp_pat_table; 517 xe->pat.n_entries = ARRAY_SIZE(xelp_pat_table); 518 xe->pat.idx[XE_CACHE_NONE] = 3; 519 xe->pat.idx[XE_CACHE_WT] = 2; 520 xe->pat.idx[XE_CACHE_WB] = 0; 521 } else if (GRAPHICS_VERx100(xe) <= 1210) { 522 WARN_ON_ONCE(!IS_DGFX(xe) && !xe->info.has_llc); 523 xe->pat.ops = &xelp_pat_ops; 524 xe->pat.table = xelp_pat_table; 525 xe->pat.n_entries = ARRAY_SIZE(xelp_pat_table); 526 xe->pat.idx[XE_CACHE_NONE] = 3; 527 xe->pat.idx[XE_CACHE_WT] = 2; 528 xe->pat.idx[XE_CACHE_WB] = 0; 529 } else { 530 /* 531 * Going forward we expect to need new PAT settings for most 532 * new platforms; failure to provide a new table can easily 533 * lead to subtle, hard-to-debug problems. If none of the 534 * conditions above match the platform we're running on we'll 535 * raise an error rather than trying to silently inherit the 536 * most recent platform's behavior. 537 */ 538 drm_err(&xe->drm, "Missing PAT table for platform with graphics version %d.%02d!\n", 539 GRAPHICS_VER(xe), GRAPHICS_VERx100(xe) % 100); 540 } 541 542 /* VFs can't program nor dump PAT settings */ 543 if (IS_SRIOV_VF(xe)) 544 xe->pat.ops = NULL; 545 546 xe_assert(xe, !xe->pat.ops || xe->pat.ops->dump); 547 xe_assert(xe, !xe->pat.ops || xe->pat.ops->program_graphics); 548 xe_assert(xe, !xe->pat.ops || MEDIA_VER(xe) < 13 || xe->pat.ops->program_media); 549 } 550 551 void xe_pat_init(struct xe_gt *gt) 552 { 553 struct xe_device *xe = gt_to_xe(gt); 554 555 if (!xe->pat.ops) 556 return; 557 558 if (xe_gt_is_media_type(gt)) 559 xe->pat.ops->program_media(gt, xe->pat.table, xe->pat.n_entries); 560 else 561 xe->pat.ops->program_graphics(gt, xe->pat.table, xe->pat.n_entries); 562 } 563 564 /** 565 * xe_pat_dump() - Dump GT PAT table into a drm printer. 566 * @gt: the &xe_gt 567 * @p: the &drm_printer 568 * 569 * Return: 0 on success or a negative error code on failure. 570 */ 571 int xe_pat_dump(struct xe_gt *gt, struct drm_printer *p) 572 { 573 struct xe_device *xe = gt_to_xe(gt); 574 575 if (!xe->pat.ops) 576 return -EOPNOTSUPP; 577 578 return xe->pat.ops->dump(gt, p); 579 } 580