1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #include "xe_pat.h" 7 8 #include <uapi/drm/xe_drm.h> 9 10 #include <generated/xe_wa_oob.h> 11 12 #include "regs/xe_reg_defs.h" 13 #include "xe_assert.h" 14 #include "xe_device.h" 15 #include "xe_force_wake.h" 16 #include "xe_gt.h" 17 #include "xe_gt_mcr.h" 18 #include "xe_mmio.h" 19 #include "xe_sriov.h" 20 #include "xe_wa.h" 21 22 #define _PAT_ATS 0x47fc 23 #define _PAT_INDEX(index) _PICK_EVEN_2RANGES(index, 8, \ 24 0x4800, 0x4804, \ 25 0x4848, 0x484c) 26 #define _PAT_PTA 0x4820 27 28 #define XE2_NO_PROMOTE REG_BIT(10) 29 #define XE2_COMP_EN REG_BIT(9) 30 #define XE2_L3_CLOS REG_GENMASK(7, 6) 31 #define XE2_L3_POLICY REG_GENMASK(5, 4) 32 #define XE2_L4_POLICY REG_GENMASK(3, 2) 33 #define XE2_COH_MODE REG_GENMASK(1, 0) 34 35 #define XELPG_L4_POLICY_MASK REG_GENMASK(3, 2) 36 #define XELPG_PAT_3_UC REG_FIELD_PREP(XELPG_L4_POLICY_MASK, 3) 37 #define XELPG_PAT_1_WT REG_FIELD_PREP(XELPG_L4_POLICY_MASK, 1) 38 #define XELPG_PAT_0_WB REG_FIELD_PREP(XELPG_L4_POLICY_MASK, 0) 39 #define XELPG_INDEX_COH_MODE_MASK REG_GENMASK(1, 0) 40 #define XELPG_3_COH_2W REG_FIELD_PREP(XELPG_INDEX_COH_MODE_MASK, 3) 41 #define XELPG_2_COH_1W REG_FIELD_PREP(XELPG_INDEX_COH_MODE_MASK, 2) 42 #define XELPG_0_COH_NON REG_FIELD_PREP(XELPG_INDEX_COH_MODE_MASK, 0) 43 44 #define XEHPC_CLOS_LEVEL_MASK REG_GENMASK(3, 2) 45 #define XEHPC_PAT_CLOS(x) REG_FIELD_PREP(XEHPC_CLOS_LEVEL_MASK, x) 46 47 #define XELP_MEM_TYPE_MASK REG_GENMASK(1, 0) 48 #define XELP_PAT_WB REG_FIELD_PREP(XELP_MEM_TYPE_MASK, 3) 49 #define XELP_PAT_WT REG_FIELD_PREP(XELP_MEM_TYPE_MASK, 2) 50 #define XELP_PAT_WC REG_FIELD_PREP(XELP_MEM_TYPE_MASK, 1) 51 #define XELP_PAT_UC REG_FIELD_PREP(XELP_MEM_TYPE_MASK, 0) 52 53 static const char *XELP_MEM_TYPE_STR_MAP[] = { "UC", "WC", "WT", "WB" }; 54 55 struct xe_pat_ops { 56 void (*program_graphics)(struct xe_gt *gt, const struct xe_pat_table_entry table[], 57 int n_entries); 58 void (*program_media)(struct xe_gt *gt, const struct xe_pat_table_entry table[], 59 int n_entries); 60 void (*dump)(struct xe_gt *gt, struct drm_printer *p); 61 }; 62 63 static const struct xe_pat_table_entry xelp_pat_table[] = { 64 [0] = { XELP_PAT_WB, XE_COH_AT_LEAST_1WAY }, 65 [1] = { XELP_PAT_WC, XE_COH_NONE }, 66 [2] = { XELP_PAT_WT, XE_COH_NONE }, 67 [3] = { XELP_PAT_UC, XE_COH_NONE }, 68 }; 69 70 static const struct xe_pat_table_entry xehpc_pat_table[] = { 71 [0] = { XELP_PAT_UC, XE_COH_NONE }, 72 [1] = { XELP_PAT_WC, XE_COH_NONE }, 73 [2] = { XELP_PAT_WT, XE_COH_NONE }, 74 [3] = { XELP_PAT_WB, XE_COH_AT_LEAST_1WAY }, 75 [4] = { XEHPC_PAT_CLOS(1) | XELP_PAT_WT, XE_COH_NONE }, 76 [5] = { XEHPC_PAT_CLOS(1) | XELP_PAT_WB, XE_COH_AT_LEAST_1WAY }, 77 [6] = { XEHPC_PAT_CLOS(2) | XELP_PAT_WT, XE_COH_NONE }, 78 [7] = { XEHPC_PAT_CLOS(2) | XELP_PAT_WB, XE_COH_AT_LEAST_1WAY }, 79 }; 80 81 static const struct xe_pat_table_entry xelpg_pat_table[] = { 82 [0] = { XELPG_PAT_0_WB, XE_COH_NONE }, 83 [1] = { XELPG_PAT_1_WT, XE_COH_NONE }, 84 [2] = { XELPG_PAT_3_UC, XE_COH_NONE }, 85 [3] = { XELPG_PAT_0_WB | XELPG_2_COH_1W, XE_COH_AT_LEAST_1WAY }, 86 [4] = { XELPG_PAT_0_WB | XELPG_3_COH_2W, XE_COH_AT_LEAST_1WAY }, 87 }; 88 89 /* 90 * The Xe2 table is getting large/complicated so it's easier to review if 91 * provided in a form that exactly matches the bspec's formatting. The meaning 92 * of the fields here are: 93 * - no_promote: 0=promotable, 1=no promote 94 * - comp_en: 0=disable, 1=enable 95 * - l3clos: L3 class of service (0-3) 96 * - l3_policy: 0=WB, 1=XD ("WB - Transient Display"), 3=UC 97 * - l4_policy: 0=WB, 1=WT, 3=UC 98 * - coh_mode: 0=no snoop, 2=1-way coherent, 3=2-way coherent 99 * 100 * Reserved entries should be programmed with the maximum caching, minimum 101 * coherency (which matches an all-0's encoding), so we can just omit them 102 * in the table. 103 * 104 * Note: There is an implicit assumption in the driver that compression and 105 * coh_1way+ are mutually exclusive. If this is ever not true then userptr 106 * and imported dma-buf from external device will have uncleared ccs state. See 107 * also xe_bo_needs_ccs_pages(). 108 */ 109 #define XE2_PAT(no_promote, comp_en, l3clos, l3_policy, l4_policy, __coh_mode) \ 110 { \ 111 .value = (no_promote ? XE2_NO_PROMOTE : 0) | \ 112 (comp_en ? XE2_COMP_EN : 0) | \ 113 REG_FIELD_PREP(XE2_L3_CLOS, l3clos) | \ 114 REG_FIELD_PREP(XE2_L3_POLICY, l3_policy) | \ 115 REG_FIELD_PREP(XE2_L4_POLICY, l4_policy) | \ 116 REG_FIELD_PREP(XE2_COH_MODE, __coh_mode), \ 117 .coh_mode = (BUILD_BUG_ON_ZERO(__coh_mode && comp_en) || __coh_mode) ? \ 118 XE_COH_AT_LEAST_1WAY : XE_COH_NONE \ 119 } 120 121 static const struct xe_pat_table_entry xe2_pat_table[] = { 122 [ 0] = XE2_PAT( 0, 0, 0, 0, 3, 0 ), 123 [ 1] = XE2_PAT( 0, 0, 0, 0, 3, 2 ), 124 [ 2] = XE2_PAT( 0, 0, 0, 0, 3, 3 ), 125 [ 3] = XE2_PAT( 0, 0, 0, 3, 3, 0 ), 126 [ 4] = XE2_PAT( 0, 0, 0, 3, 0, 2 ), 127 [ 5] = XE2_PAT( 0, 0, 0, 3, 3, 2 ), 128 [ 6] = XE2_PAT( 1, 0, 0, 1, 3, 0 ), 129 [ 7] = XE2_PAT( 0, 0, 0, 3, 0, 3 ), 130 [ 8] = XE2_PAT( 0, 0, 0, 3, 0, 0 ), 131 [ 9] = XE2_PAT( 0, 1, 0, 0, 3, 0 ), 132 [10] = XE2_PAT( 0, 1, 0, 3, 0, 0 ), 133 [11] = XE2_PAT( 1, 1, 0, 1, 3, 0 ), 134 [12] = XE2_PAT( 0, 1, 0, 3, 3, 0 ), 135 [13] = XE2_PAT( 0, 0, 0, 0, 0, 0 ), 136 [14] = XE2_PAT( 0, 1, 0, 0, 0, 0 ), 137 [15] = XE2_PAT( 1, 1, 0, 1, 1, 0 ), 138 /* 16..19 are reserved; leave set to all 0's */ 139 [20] = XE2_PAT( 0, 0, 1, 0, 3, 0 ), 140 [21] = XE2_PAT( 0, 1, 1, 0, 3, 0 ), 141 [22] = XE2_PAT( 0, 0, 1, 0, 3, 2 ), 142 [23] = XE2_PAT( 0, 0, 1, 0, 3, 3 ), 143 [24] = XE2_PAT( 0, 0, 2, 0, 3, 0 ), 144 [25] = XE2_PAT( 0, 1, 2, 0, 3, 0 ), 145 [26] = XE2_PAT( 0, 0, 2, 0, 3, 2 ), 146 [27] = XE2_PAT( 0, 0, 2, 0, 3, 3 ), 147 [28] = XE2_PAT( 0, 0, 3, 0, 3, 0 ), 148 [29] = XE2_PAT( 0, 1, 3, 0, 3, 0 ), 149 [30] = XE2_PAT( 0, 0, 3, 0, 3, 2 ), 150 [31] = XE2_PAT( 0, 0, 3, 0, 3, 3 ), 151 }; 152 153 /* Special PAT values programmed outside the main table */ 154 static const struct xe_pat_table_entry xe2_pat_ats = XE2_PAT( 0, 0, 0, 0, 3, 3 ); 155 static const struct xe_pat_table_entry xe2_pat_pta = XE2_PAT( 0, 0, 0, 0, 3, 0 ); 156 157 u16 xe_pat_index_get_coh_mode(struct xe_device *xe, u16 pat_index) 158 { 159 WARN_ON(pat_index >= xe->pat.n_entries); 160 return xe->pat.table[pat_index].coh_mode; 161 } 162 163 static void program_pat(struct xe_gt *gt, const struct xe_pat_table_entry table[], 164 int n_entries) 165 { 166 struct xe_device *xe = gt_to_xe(gt); 167 168 for (int i = 0; i < n_entries; i++) { 169 struct xe_reg reg = XE_REG(_PAT_INDEX(i)); 170 171 xe_mmio_write32(>->mmio, reg, table[i].value); 172 } 173 174 if (xe->pat.pat_ats) 175 xe_mmio_write32(>->mmio, XE_REG(_PAT_ATS), xe->pat.pat_ats->value); 176 if (xe->pat.pat_pta) 177 xe_mmio_write32(>->mmio, XE_REG(_PAT_PTA), xe->pat.pat_pta->value); 178 } 179 180 static void program_pat_mcr(struct xe_gt *gt, const struct xe_pat_table_entry table[], 181 int n_entries) 182 { 183 struct xe_device *xe = gt_to_xe(gt); 184 185 for (int i = 0; i < n_entries; i++) { 186 struct xe_reg_mcr reg_mcr = XE_REG_MCR(_PAT_INDEX(i)); 187 188 xe_gt_mcr_multicast_write(gt, reg_mcr, table[i].value); 189 } 190 191 if (xe->pat.pat_ats) 192 xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_ATS), xe->pat.pat_ats->value); 193 if (xe->pat.pat_pta) 194 xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_PTA), xe->pat.pat_pta->value); 195 } 196 197 static void xelp_dump(struct xe_gt *gt, struct drm_printer *p) 198 { 199 struct xe_device *xe = gt_to_xe(gt); 200 unsigned int fw_ref; 201 int i; 202 203 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 204 if (!fw_ref) 205 return; 206 207 drm_printf(p, "PAT table:\n"); 208 209 for (i = 0; i < xe->pat.n_entries; i++) { 210 u32 pat = xe_mmio_read32(>->mmio, XE_REG(_PAT_INDEX(i))); 211 u8 mem_type = REG_FIELD_GET(XELP_MEM_TYPE_MASK, pat); 212 213 drm_printf(p, "PAT[%2d] = %s (%#8x)\n", i, 214 XELP_MEM_TYPE_STR_MAP[mem_type], pat); 215 } 216 217 xe_force_wake_put(gt_to_fw(gt), fw_ref); 218 } 219 220 static const struct xe_pat_ops xelp_pat_ops = { 221 .program_graphics = program_pat, 222 .dump = xelp_dump, 223 }; 224 225 static void xehp_dump(struct xe_gt *gt, struct drm_printer *p) 226 { 227 struct xe_device *xe = gt_to_xe(gt); 228 unsigned int fw_ref; 229 int i; 230 231 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 232 if (!fw_ref) 233 return; 234 235 drm_printf(p, "PAT table:\n"); 236 237 for (i = 0; i < xe->pat.n_entries; i++) { 238 u32 pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i))); 239 u8 mem_type; 240 241 mem_type = REG_FIELD_GET(XELP_MEM_TYPE_MASK, pat); 242 243 drm_printf(p, "PAT[%2d] = %s (%#8x)\n", i, 244 XELP_MEM_TYPE_STR_MAP[mem_type], pat); 245 } 246 247 xe_force_wake_put(gt_to_fw(gt), fw_ref); 248 } 249 250 static const struct xe_pat_ops xehp_pat_ops = { 251 .program_graphics = program_pat_mcr, 252 .dump = xehp_dump, 253 }; 254 255 static void xehpc_dump(struct xe_gt *gt, struct drm_printer *p) 256 { 257 struct xe_device *xe = gt_to_xe(gt); 258 unsigned int fw_ref; 259 int i; 260 261 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 262 if (!fw_ref) 263 return; 264 265 drm_printf(p, "PAT table:\n"); 266 267 for (i = 0; i < xe->pat.n_entries; i++) { 268 u32 pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i))); 269 270 drm_printf(p, "PAT[%2d] = [ %u, %u ] (%#8x)\n", i, 271 REG_FIELD_GET(XELP_MEM_TYPE_MASK, pat), 272 REG_FIELD_GET(XEHPC_CLOS_LEVEL_MASK, pat), pat); 273 } 274 275 xe_force_wake_put(gt_to_fw(gt), fw_ref); 276 } 277 278 static const struct xe_pat_ops xehpc_pat_ops = { 279 .program_graphics = program_pat_mcr, 280 .dump = xehpc_dump, 281 }; 282 283 static void xelpg_dump(struct xe_gt *gt, struct drm_printer *p) 284 { 285 struct xe_device *xe = gt_to_xe(gt); 286 unsigned int fw_ref; 287 int i; 288 289 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 290 if (!fw_ref) 291 return; 292 293 drm_printf(p, "PAT table:\n"); 294 295 for (i = 0; i < xe->pat.n_entries; i++) { 296 u32 pat; 297 298 if (xe_gt_is_media_type(gt)) 299 pat = xe_mmio_read32(>->mmio, XE_REG(_PAT_INDEX(i))); 300 else 301 pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i))); 302 303 drm_printf(p, "PAT[%2d] = [ %u, %u ] (%#8x)\n", i, 304 REG_FIELD_GET(XELPG_L4_POLICY_MASK, pat), 305 REG_FIELD_GET(XELPG_INDEX_COH_MODE_MASK, pat), pat); 306 } 307 308 xe_force_wake_put(gt_to_fw(gt), fw_ref); 309 } 310 311 /* 312 * SAMedia register offsets are adjusted by the write methods and they target 313 * registers that are not MCR, while for normal GT they are MCR 314 */ 315 static const struct xe_pat_ops xelpg_pat_ops = { 316 .program_graphics = program_pat, 317 .program_media = program_pat_mcr, 318 .dump = xelpg_dump, 319 }; 320 321 static void xe2_dump(struct xe_gt *gt, struct drm_printer *p) 322 { 323 struct xe_device *xe = gt_to_xe(gt); 324 unsigned int fw_ref; 325 u32 pat; 326 int i; 327 328 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 329 if (!fw_ref) 330 return; 331 332 drm_printf(p, "PAT table:\n"); 333 334 for (i = 0; i < xe->pat.n_entries; i++) { 335 if (xe_gt_is_media_type(gt)) 336 pat = xe_mmio_read32(>->mmio, XE_REG(_PAT_INDEX(i))); 337 else 338 pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i))); 339 340 drm_printf(p, "PAT[%2d] = [ %u, %u, %u, %u, %u, %u ] (%#8x)\n", i, 341 !!(pat & XE2_NO_PROMOTE), 342 !!(pat & XE2_COMP_EN), 343 REG_FIELD_GET(XE2_L3_CLOS, pat), 344 REG_FIELD_GET(XE2_L3_POLICY, pat), 345 REG_FIELD_GET(XE2_L4_POLICY, pat), 346 REG_FIELD_GET(XE2_COH_MODE, pat), 347 pat); 348 } 349 350 /* 351 * Also print PTA_MODE, which describes how the hardware accesses 352 * PPGTT entries. 353 */ 354 if (xe_gt_is_media_type(gt)) 355 pat = xe_mmio_read32(>->mmio, XE_REG(_PAT_PTA)); 356 else 357 pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_PTA)); 358 359 drm_printf(p, "Page Table Access:\n"); 360 drm_printf(p, "PTA_MODE= [ %u, %u, %u, %u, %u, %u ] (%#8x)\n", 361 !!(pat & XE2_NO_PROMOTE), 362 !!(pat & XE2_COMP_EN), 363 REG_FIELD_GET(XE2_L3_CLOS, pat), 364 REG_FIELD_GET(XE2_L3_POLICY, pat), 365 REG_FIELD_GET(XE2_L4_POLICY, pat), 366 REG_FIELD_GET(XE2_COH_MODE, pat), 367 pat); 368 369 xe_force_wake_put(gt_to_fw(gt), fw_ref); 370 } 371 372 static const struct xe_pat_ops xe2_pat_ops = { 373 .program_graphics = program_pat_mcr, 374 .program_media = program_pat, 375 .dump = xe2_dump, 376 }; 377 378 void xe_pat_init_early(struct xe_device *xe) 379 { 380 if (GRAPHICS_VER(xe) == 30 || GRAPHICS_VER(xe) == 20) { 381 xe->pat.ops = &xe2_pat_ops; 382 xe->pat.table = xe2_pat_table; 383 xe->pat.pat_ats = &xe2_pat_ats; 384 if (IS_DGFX(xe)) 385 xe->pat.pat_pta = &xe2_pat_pta; 386 387 /* Wa_16023588340. XXX: Should use XE_WA */ 388 if (GRAPHICS_VERx100(xe) == 2001) 389 xe->pat.n_entries = 28; /* Disable CLOS3 */ 390 else 391 xe->pat.n_entries = ARRAY_SIZE(xe2_pat_table); 392 393 xe->pat.idx[XE_CACHE_NONE] = 3; 394 xe->pat.idx[XE_CACHE_WT] = 15; 395 xe->pat.idx[XE_CACHE_WB] = 2; 396 xe->pat.idx[XE_CACHE_NONE_COMPRESSION] = 12; /*Applicable on xe2 and beyond */ 397 } else if (xe->info.platform == XE_METEORLAKE) { 398 xe->pat.ops = &xelpg_pat_ops; 399 xe->pat.table = xelpg_pat_table; 400 xe->pat.n_entries = ARRAY_SIZE(xelpg_pat_table); 401 xe->pat.idx[XE_CACHE_NONE] = 2; 402 xe->pat.idx[XE_CACHE_WT] = 1; 403 xe->pat.idx[XE_CACHE_WB] = 3; 404 } else if (xe->info.platform == XE_PVC) { 405 xe->pat.ops = &xehpc_pat_ops; 406 xe->pat.table = xehpc_pat_table; 407 xe->pat.n_entries = ARRAY_SIZE(xehpc_pat_table); 408 xe->pat.idx[XE_CACHE_NONE] = 0; 409 xe->pat.idx[XE_CACHE_WT] = 2; 410 xe->pat.idx[XE_CACHE_WB] = 3; 411 } else if (xe->info.platform == XE_DG2) { 412 /* 413 * Table is the same as previous platforms, but programming 414 * method has changed. 415 */ 416 xe->pat.ops = &xehp_pat_ops; 417 xe->pat.table = xelp_pat_table; 418 xe->pat.n_entries = ARRAY_SIZE(xelp_pat_table); 419 xe->pat.idx[XE_CACHE_NONE] = 3; 420 xe->pat.idx[XE_CACHE_WT] = 2; 421 xe->pat.idx[XE_CACHE_WB] = 0; 422 } else if (GRAPHICS_VERx100(xe) <= 1210) { 423 WARN_ON_ONCE(!IS_DGFX(xe) && !xe->info.has_llc); 424 xe->pat.ops = &xelp_pat_ops; 425 xe->pat.table = xelp_pat_table; 426 xe->pat.n_entries = ARRAY_SIZE(xelp_pat_table); 427 xe->pat.idx[XE_CACHE_NONE] = 3; 428 xe->pat.idx[XE_CACHE_WT] = 2; 429 xe->pat.idx[XE_CACHE_WB] = 0; 430 } else { 431 /* 432 * Going forward we expect to need new PAT settings for most 433 * new platforms; failure to provide a new table can easily 434 * lead to subtle, hard-to-debug problems. If none of the 435 * conditions above match the platform we're running on we'll 436 * raise an error rather than trying to silently inherit the 437 * most recent platform's behavior. 438 */ 439 drm_err(&xe->drm, "Missing PAT table for platform with graphics version %d.%02d!\n", 440 GRAPHICS_VER(xe), GRAPHICS_VERx100(xe) % 100); 441 } 442 443 /* VFs can't program nor dump PAT settings */ 444 if (IS_SRIOV_VF(xe)) 445 xe->pat.ops = NULL; 446 447 xe_assert(xe, !xe->pat.ops || xe->pat.ops->dump); 448 xe_assert(xe, !xe->pat.ops || xe->pat.ops->program_graphics); 449 xe_assert(xe, !xe->pat.ops || MEDIA_VER(xe) < 13 || xe->pat.ops->program_media); 450 } 451 452 void xe_pat_init(struct xe_gt *gt) 453 { 454 struct xe_device *xe = gt_to_xe(gt); 455 456 if (!xe->pat.ops) 457 return; 458 459 if (xe_gt_is_media_type(gt)) 460 xe->pat.ops->program_media(gt, xe->pat.table, xe->pat.n_entries); 461 else 462 xe->pat.ops->program_graphics(gt, xe->pat.table, xe->pat.n_entries); 463 } 464 465 void xe_pat_dump(struct xe_gt *gt, struct drm_printer *p) 466 { 467 struct xe_device *xe = gt_to_xe(gt); 468 469 if (!xe->pat.ops) 470 return; 471 472 xe->pat.ops->dump(gt, p); 473 } 474