1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #include "xe_pat.h" 7 8 #include <uapi/drm/xe_drm.h> 9 10 #include <generated/xe_wa_oob.h> 11 12 #include "regs/xe_reg_defs.h" 13 #include "xe_assert.h" 14 #include "xe_device.h" 15 #include "xe_force_wake.h" 16 #include "xe_gt.h" 17 #include "xe_gt_mcr.h" 18 #include "xe_mmio.h" 19 #include "xe_sriov.h" 20 #include "xe_wa.h" 21 22 #define _PAT_ATS 0x47fc 23 #define _PAT_INDEX(index) _PICK_EVEN_2RANGES(index, 8, \ 24 0x4800, 0x4804, \ 25 0x4848, 0x484c) 26 #define _PAT_PTA 0x4820 27 28 #define XE2_NO_PROMOTE REG_BIT(10) 29 #define XE2_COMP_EN REG_BIT(9) 30 #define XE2_L3_CLOS REG_GENMASK(7, 6) 31 #define XE2_L3_POLICY REG_GENMASK(5, 4) 32 #define XE2_L4_POLICY REG_GENMASK(3, 2) 33 #define XE2_COH_MODE REG_GENMASK(1, 0) 34 35 #define XELPG_L4_POLICY_MASK REG_GENMASK(3, 2) 36 #define XELPG_PAT_3_UC REG_FIELD_PREP(XELPG_L4_POLICY_MASK, 3) 37 #define XELPG_PAT_1_WT REG_FIELD_PREP(XELPG_L4_POLICY_MASK, 1) 38 #define XELPG_PAT_0_WB REG_FIELD_PREP(XELPG_L4_POLICY_MASK, 0) 39 #define XELPG_INDEX_COH_MODE_MASK REG_GENMASK(1, 0) 40 #define XELPG_3_COH_2W REG_FIELD_PREP(XELPG_INDEX_COH_MODE_MASK, 3) 41 #define XELPG_2_COH_1W REG_FIELD_PREP(XELPG_INDEX_COH_MODE_MASK, 2) 42 #define XELPG_0_COH_NON REG_FIELD_PREP(XELPG_INDEX_COH_MODE_MASK, 0) 43 44 #define XEHPC_CLOS_LEVEL_MASK REG_GENMASK(3, 2) 45 #define XEHPC_PAT_CLOS(x) REG_FIELD_PREP(XEHPC_CLOS_LEVEL_MASK, x) 46 47 #define XELP_MEM_TYPE_MASK REG_GENMASK(1, 0) 48 #define XELP_PAT_WB REG_FIELD_PREP(XELP_MEM_TYPE_MASK, 3) 49 #define XELP_PAT_WT REG_FIELD_PREP(XELP_MEM_TYPE_MASK, 2) 50 #define XELP_PAT_WC REG_FIELD_PREP(XELP_MEM_TYPE_MASK, 1) 51 #define XELP_PAT_UC REG_FIELD_PREP(XELP_MEM_TYPE_MASK, 0) 52 53 static const char *XELP_MEM_TYPE_STR_MAP[] = { "UC", "WC", "WT", "WB" }; 54 55 struct xe_pat_ops { 56 void (*program_graphics)(struct xe_gt *gt, const struct xe_pat_table_entry table[], 57 int n_entries); 58 void (*program_media)(struct xe_gt *gt, const struct xe_pat_table_entry table[], 59 int n_entries); 60 int (*dump)(struct xe_gt *gt, struct drm_printer *p); 61 }; 62 63 static const struct xe_pat_table_entry xelp_pat_table[] = { 64 [0] = { XELP_PAT_WB, XE_COH_AT_LEAST_1WAY }, 65 [1] = { XELP_PAT_WC, XE_COH_NONE }, 66 [2] = { XELP_PAT_WT, XE_COH_NONE }, 67 [3] = { XELP_PAT_UC, XE_COH_NONE }, 68 }; 69 70 static const struct xe_pat_table_entry xehpc_pat_table[] = { 71 [0] = { XELP_PAT_UC, XE_COH_NONE }, 72 [1] = { XELP_PAT_WC, XE_COH_NONE }, 73 [2] = { XELP_PAT_WT, XE_COH_NONE }, 74 [3] = { XELP_PAT_WB, XE_COH_AT_LEAST_1WAY }, 75 [4] = { XEHPC_PAT_CLOS(1) | XELP_PAT_WT, XE_COH_NONE }, 76 [5] = { XEHPC_PAT_CLOS(1) | XELP_PAT_WB, XE_COH_AT_LEAST_1WAY }, 77 [6] = { XEHPC_PAT_CLOS(2) | XELP_PAT_WT, XE_COH_NONE }, 78 [7] = { XEHPC_PAT_CLOS(2) | XELP_PAT_WB, XE_COH_AT_LEAST_1WAY }, 79 }; 80 81 static const struct xe_pat_table_entry xelpg_pat_table[] = { 82 [0] = { XELPG_PAT_0_WB, XE_COH_NONE }, 83 [1] = { XELPG_PAT_1_WT, XE_COH_NONE }, 84 [2] = { XELPG_PAT_3_UC, XE_COH_NONE }, 85 [3] = { XELPG_PAT_0_WB | XELPG_2_COH_1W, XE_COH_AT_LEAST_1WAY }, 86 [4] = { XELPG_PAT_0_WB | XELPG_3_COH_2W, XE_COH_AT_LEAST_1WAY }, 87 }; 88 89 /* 90 * The Xe2 table is getting large/complicated so it's easier to review if 91 * provided in a form that exactly matches the bspec's formatting. The meaning 92 * of the fields here are: 93 * - no_promote: 0=promotable, 1=no promote 94 * - comp_en: 0=disable, 1=enable 95 * - l3clos: L3 class of service (0-3) 96 * - l3_policy: 0=WB, 1=XD ("WB - Transient Display"), 3=UC 97 * - l4_policy: 0=WB, 1=WT, 3=UC 98 * - coh_mode: 0=no snoop, 2=1-way coherent, 3=2-way coherent 99 * 100 * Reserved entries should be programmed with the maximum caching, minimum 101 * coherency (which matches an all-0's encoding), so we can just omit them 102 * in the table. 103 * 104 * Note: There is an implicit assumption in the driver that compression and 105 * coh_1way+ are mutually exclusive. If this is ever not true then userptr 106 * and imported dma-buf from external device will have uncleared ccs state. See 107 * also xe_bo_needs_ccs_pages(). 108 */ 109 #define XE2_PAT(no_promote, comp_en, l3clos, l3_policy, l4_policy, __coh_mode) \ 110 { \ 111 .value = (no_promote ? XE2_NO_PROMOTE : 0) | \ 112 (comp_en ? XE2_COMP_EN : 0) | \ 113 REG_FIELD_PREP(XE2_L3_CLOS, l3clos) | \ 114 REG_FIELD_PREP(XE2_L3_POLICY, l3_policy) | \ 115 REG_FIELD_PREP(XE2_L4_POLICY, l4_policy) | \ 116 REG_FIELD_PREP(XE2_COH_MODE, __coh_mode), \ 117 .coh_mode = (BUILD_BUG_ON_ZERO(__coh_mode && comp_en) || __coh_mode) ? \ 118 XE_COH_AT_LEAST_1WAY : XE_COH_NONE \ 119 } 120 121 static const struct xe_pat_table_entry xe2_pat_table[] = { 122 [ 0] = XE2_PAT( 0, 0, 0, 0, 3, 0 ), 123 [ 1] = XE2_PAT( 0, 0, 0, 0, 3, 2 ), 124 [ 2] = XE2_PAT( 0, 0, 0, 0, 3, 3 ), 125 [ 3] = XE2_PAT( 0, 0, 0, 3, 3, 0 ), 126 [ 4] = XE2_PAT( 0, 0, 0, 3, 0, 2 ), 127 [ 5] = XE2_PAT( 0, 0, 0, 3, 3, 2 ), 128 [ 6] = XE2_PAT( 1, 0, 0, 1, 3, 0 ), 129 [ 7] = XE2_PAT( 0, 0, 0, 3, 0, 3 ), 130 [ 8] = XE2_PAT( 0, 0, 0, 3, 0, 0 ), 131 [ 9] = XE2_PAT( 0, 1, 0, 0, 3, 0 ), 132 [10] = XE2_PAT( 0, 1, 0, 3, 0, 0 ), 133 [11] = XE2_PAT( 1, 1, 0, 1, 3, 0 ), 134 [12] = XE2_PAT( 0, 1, 0, 3, 3, 0 ), 135 [13] = XE2_PAT( 0, 0, 0, 0, 0, 0 ), 136 [14] = XE2_PAT( 0, 1, 0, 0, 0, 0 ), 137 [15] = XE2_PAT( 1, 1, 0, 1, 1, 0 ), 138 /* 16..19 are reserved; leave set to all 0's */ 139 [20] = XE2_PAT( 0, 0, 1, 0, 3, 0 ), 140 [21] = XE2_PAT( 0, 1, 1, 0, 3, 0 ), 141 [22] = XE2_PAT( 0, 0, 1, 0, 3, 2 ), 142 [23] = XE2_PAT( 0, 0, 1, 0, 3, 3 ), 143 [24] = XE2_PAT( 0, 0, 2, 0, 3, 0 ), 144 [25] = XE2_PAT( 0, 1, 2, 0, 3, 0 ), 145 [26] = XE2_PAT( 0, 0, 2, 0, 3, 2 ), 146 [27] = XE2_PAT( 0, 0, 2, 0, 3, 3 ), 147 [28] = XE2_PAT( 0, 0, 3, 0, 3, 0 ), 148 [29] = XE2_PAT( 0, 1, 3, 0, 3, 0 ), 149 [30] = XE2_PAT( 0, 0, 3, 0, 3, 2 ), 150 [31] = XE2_PAT( 0, 0, 3, 0, 3, 3 ), 151 }; 152 153 /* Special PAT values programmed outside the main table */ 154 static const struct xe_pat_table_entry xe2_pat_ats = XE2_PAT( 0, 0, 0, 0, 3, 3 ); 155 static const struct xe_pat_table_entry xe2_pat_pta = XE2_PAT( 0, 0, 0, 0, 3, 0 ); 156 157 u16 xe_pat_index_get_coh_mode(struct xe_device *xe, u16 pat_index) 158 { 159 WARN_ON(pat_index >= xe->pat.n_entries); 160 return xe->pat.table[pat_index].coh_mode; 161 } 162 163 static void program_pat(struct xe_gt *gt, const struct xe_pat_table_entry table[], 164 int n_entries) 165 { 166 struct xe_device *xe = gt_to_xe(gt); 167 168 for (int i = 0; i < n_entries; i++) { 169 struct xe_reg reg = XE_REG(_PAT_INDEX(i)); 170 171 xe_mmio_write32(>->mmio, reg, table[i].value); 172 } 173 174 if (xe->pat.pat_ats) 175 xe_mmio_write32(>->mmio, XE_REG(_PAT_ATS), xe->pat.pat_ats->value); 176 if (xe->pat.pat_pta) 177 xe_mmio_write32(>->mmio, XE_REG(_PAT_PTA), xe->pat.pat_pta->value); 178 } 179 180 static void program_pat_mcr(struct xe_gt *gt, const struct xe_pat_table_entry table[], 181 int n_entries) 182 { 183 struct xe_device *xe = gt_to_xe(gt); 184 185 for (int i = 0; i < n_entries; i++) { 186 struct xe_reg_mcr reg_mcr = XE_REG_MCR(_PAT_INDEX(i)); 187 188 xe_gt_mcr_multicast_write(gt, reg_mcr, table[i].value); 189 } 190 191 if (xe->pat.pat_ats) 192 xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_ATS), xe->pat.pat_ats->value); 193 if (xe->pat.pat_pta) 194 xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_PTA), xe->pat.pat_pta->value); 195 } 196 197 static int xelp_dump(struct xe_gt *gt, struct drm_printer *p) 198 { 199 struct xe_device *xe = gt_to_xe(gt); 200 unsigned int fw_ref; 201 int i; 202 203 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 204 if (!fw_ref) 205 return -ETIMEDOUT; 206 207 drm_printf(p, "PAT table:\n"); 208 209 for (i = 0; i < xe->pat.n_entries; i++) { 210 u32 pat = xe_mmio_read32(>->mmio, XE_REG(_PAT_INDEX(i))); 211 u8 mem_type = REG_FIELD_GET(XELP_MEM_TYPE_MASK, pat); 212 213 drm_printf(p, "PAT[%2d] = %s (%#8x)\n", i, 214 XELP_MEM_TYPE_STR_MAP[mem_type], pat); 215 } 216 217 xe_force_wake_put(gt_to_fw(gt), fw_ref); 218 return 0; 219 } 220 221 static const struct xe_pat_ops xelp_pat_ops = { 222 .program_graphics = program_pat, 223 .dump = xelp_dump, 224 }; 225 226 static int xehp_dump(struct xe_gt *gt, struct drm_printer *p) 227 { 228 struct xe_device *xe = gt_to_xe(gt); 229 unsigned int fw_ref; 230 int i; 231 232 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 233 if (!fw_ref) 234 return -ETIMEDOUT; 235 236 drm_printf(p, "PAT table:\n"); 237 238 for (i = 0; i < xe->pat.n_entries; i++) { 239 u32 pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i))); 240 u8 mem_type; 241 242 mem_type = REG_FIELD_GET(XELP_MEM_TYPE_MASK, pat); 243 244 drm_printf(p, "PAT[%2d] = %s (%#8x)\n", i, 245 XELP_MEM_TYPE_STR_MAP[mem_type], pat); 246 } 247 248 xe_force_wake_put(gt_to_fw(gt), fw_ref); 249 return 0; 250 } 251 252 static const struct xe_pat_ops xehp_pat_ops = { 253 .program_graphics = program_pat_mcr, 254 .dump = xehp_dump, 255 }; 256 257 static int xehpc_dump(struct xe_gt *gt, struct drm_printer *p) 258 { 259 struct xe_device *xe = gt_to_xe(gt); 260 unsigned int fw_ref; 261 int i; 262 263 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 264 if (!fw_ref) 265 return -ETIMEDOUT; 266 267 drm_printf(p, "PAT table:\n"); 268 269 for (i = 0; i < xe->pat.n_entries; i++) { 270 u32 pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i))); 271 272 drm_printf(p, "PAT[%2d] = [ %u, %u ] (%#8x)\n", i, 273 REG_FIELD_GET(XELP_MEM_TYPE_MASK, pat), 274 REG_FIELD_GET(XEHPC_CLOS_LEVEL_MASK, pat), pat); 275 } 276 277 xe_force_wake_put(gt_to_fw(gt), fw_ref); 278 return 0; 279 } 280 281 static const struct xe_pat_ops xehpc_pat_ops = { 282 .program_graphics = program_pat_mcr, 283 .dump = xehpc_dump, 284 }; 285 286 static int xelpg_dump(struct xe_gt *gt, struct drm_printer *p) 287 { 288 struct xe_device *xe = gt_to_xe(gt); 289 unsigned int fw_ref; 290 int i; 291 292 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 293 if (!fw_ref) 294 return -ETIMEDOUT; 295 296 drm_printf(p, "PAT table:\n"); 297 298 for (i = 0; i < xe->pat.n_entries; i++) { 299 u32 pat; 300 301 if (xe_gt_is_media_type(gt)) 302 pat = xe_mmio_read32(>->mmio, XE_REG(_PAT_INDEX(i))); 303 else 304 pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i))); 305 306 drm_printf(p, "PAT[%2d] = [ %u, %u ] (%#8x)\n", i, 307 REG_FIELD_GET(XELPG_L4_POLICY_MASK, pat), 308 REG_FIELD_GET(XELPG_INDEX_COH_MODE_MASK, pat), pat); 309 } 310 311 xe_force_wake_put(gt_to_fw(gt), fw_ref); 312 return 0; 313 } 314 315 /* 316 * SAMedia register offsets are adjusted by the write methods and they target 317 * registers that are not MCR, while for normal GT they are MCR 318 */ 319 static const struct xe_pat_ops xelpg_pat_ops = { 320 .program_graphics = program_pat, 321 .program_media = program_pat_mcr, 322 .dump = xelpg_dump, 323 }; 324 325 static int xe2_dump(struct xe_gt *gt, struct drm_printer *p) 326 { 327 struct xe_device *xe = gt_to_xe(gt); 328 unsigned int fw_ref; 329 u32 pat; 330 int i; 331 332 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 333 if (!fw_ref) 334 return -ETIMEDOUT; 335 336 drm_printf(p, "PAT table:\n"); 337 338 for (i = 0; i < xe->pat.n_entries; i++) { 339 if (xe_gt_is_media_type(gt)) 340 pat = xe_mmio_read32(>->mmio, XE_REG(_PAT_INDEX(i))); 341 else 342 pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i))); 343 344 drm_printf(p, "PAT[%2d] = [ %u, %u, %u, %u, %u, %u ] (%#8x)\n", i, 345 !!(pat & XE2_NO_PROMOTE), 346 !!(pat & XE2_COMP_EN), 347 REG_FIELD_GET(XE2_L3_CLOS, pat), 348 REG_FIELD_GET(XE2_L3_POLICY, pat), 349 REG_FIELD_GET(XE2_L4_POLICY, pat), 350 REG_FIELD_GET(XE2_COH_MODE, pat), 351 pat); 352 } 353 354 /* 355 * Also print PTA_MODE, which describes how the hardware accesses 356 * PPGTT entries. 357 */ 358 if (xe_gt_is_media_type(gt)) 359 pat = xe_mmio_read32(>->mmio, XE_REG(_PAT_PTA)); 360 else 361 pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_PTA)); 362 363 drm_printf(p, "Page Table Access:\n"); 364 drm_printf(p, "PTA_MODE= [ %u, %u, %u, %u, %u, %u ] (%#8x)\n", 365 !!(pat & XE2_NO_PROMOTE), 366 !!(pat & XE2_COMP_EN), 367 REG_FIELD_GET(XE2_L3_CLOS, pat), 368 REG_FIELD_GET(XE2_L3_POLICY, pat), 369 REG_FIELD_GET(XE2_L4_POLICY, pat), 370 REG_FIELD_GET(XE2_COH_MODE, pat), 371 pat); 372 373 xe_force_wake_put(gt_to_fw(gt), fw_ref); 374 return 0; 375 } 376 377 static const struct xe_pat_ops xe2_pat_ops = { 378 .program_graphics = program_pat_mcr, 379 .program_media = program_pat, 380 .dump = xe2_dump, 381 }; 382 383 void xe_pat_init_early(struct xe_device *xe) 384 { 385 if (GRAPHICS_VER(xe) == 30 || GRAPHICS_VER(xe) == 20) { 386 xe->pat.ops = &xe2_pat_ops; 387 xe->pat.table = xe2_pat_table; 388 xe->pat.pat_ats = &xe2_pat_ats; 389 if (IS_DGFX(xe)) 390 xe->pat.pat_pta = &xe2_pat_pta; 391 392 /* Wa_16023588340. XXX: Should use XE_WA */ 393 if (GRAPHICS_VERx100(xe) == 2001) 394 xe->pat.n_entries = 28; /* Disable CLOS3 */ 395 else 396 xe->pat.n_entries = ARRAY_SIZE(xe2_pat_table); 397 398 xe->pat.idx[XE_CACHE_NONE] = 3; 399 xe->pat.idx[XE_CACHE_WT] = 15; 400 xe->pat.idx[XE_CACHE_WB] = 2; 401 xe->pat.idx[XE_CACHE_NONE_COMPRESSION] = 12; /*Applicable on xe2 and beyond */ 402 } else if (xe->info.platform == XE_METEORLAKE) { 403 xe->pat.ops = &xelpg_pat_ops; 404 xe->pat.table = xelpg_pat_table; 405 xe->pat.n_entries = ARRAY_SIZE(xelpg_pat_table); 406 xe->pat.idx[XE_CACHE_NONE] = 2; 407 xe->pat.idx[XE_CACHE_WT] = 1; 408 xe->pat.idx[XE_CACHE_WB] = 3; 409 } else if (xe->info.platform == XE_PVC) { 410 xe->pat.ops = &xehpc_pat_ops; 411 xe->pat.table = xehpc_pat_table; 412 xe->pat.n_entries = ARRAY_SIZE(xehpc_pat_table); 413 xe->pat.idx[XE_CACHE_NONE] = 0; 414 xe->pat.idx[XE_CACHE_WT] = 2; 415 xe->pat.idx[XE_CACHE_WB] = 3; 416 } else if (xe->info.platform == XE_DG2) { 417 /* 418 * Table is the same as previous platforms, but programming 419 * method has changed. 420 */ 421 xe->pat.ops = &xehp_pat_ops; 422 xe->pat.table = xelp_pat_table; 423 xe->pat.n_entries = ARRAY_SIZE(xelp_pat_table); 424 xe->pat.idx[XE_CACHE_NONE] = 3; 425 xe->pat.idx[XE_CACHE_WT] = 2; 426 xe->pat.idx[XE_CACHE_WB] = 0; 427 } else if (GRAPHICS_VERx100(xe) <= 1210) { 428 WARN_ON_ONCE(!IS_DGFX(xe) && !xe->info.has_llc); 429 xe->pat.ops = &xelp_pat_ops; 430 xe->pat.table = xelp_pat_table; 431 xe->pat.n_entries = ARRAY_SIZE(xelp_pat_table); 432 xe->pat.idx[XE_CACHE_NONE] = 3; 433 xe->pat.idx[XE_CACHE_WT] = 2; 434 xe->pat.idx[XE_CACHE_WB] = 0; 435 } else { 436 /* 437 * Going forward we expect to need new PAT settings for most 438 * new platforms; failure to provide a new table can easily 439 * lead to subtle, hard-to-debug problems. If none of the 440 * conditions above match the platform we're running on we'll 441 * raise an error rather than trying to silently inherit the 442 * most recent platform's behavior. 443 */ 444 drm_err(&xe->drm, "Missing PAT table for platform with graphics version %d.%02d!\n", 445 GRAPHICS_VER(xe), GRAPHICS_VERx100(xe) % 100); 446 } 447 448 /* VFs can't program nor dump PAT settings */ 449 if (IS_SRIOV_VF(xe)) 450 xe->pat.ops = NULL; 451 452 xe_assert(xe, !xe->pat.ops || xe->pat.ops->dump); 453 xe_assert(xe, !xe->pat.ops || xe->pat.ops->program_graphics); 454 xe_assert(xe, !xe->pat.ops || MEDIA_VER(xe) < 13 || xe->pat.ops->program_media); 455 } 456 457 void xe_pat_init(struct xe_gt *gt) 458 { 459 struct xe_device *xe = gt_to_xe(gt); 460 461 if (!xe->pat.ops) 462 return; 463 464 if (xe_gt_is_media_type(gt)) 465 xe->pat.ops->program_media(gt, xe->pat.table, xe->pat.n_entries); 466 else 467 xe->pat.ops->program_graphics(gt, xe->pat.table, xe->pat.n_entries); 468 } 469 470 /** 471 * xe_pat_dump() - Dump GT PAT table into a drm printer. 472 * @gt: the &xe_gt 473 * @p: the &drm_printer 474 * 475 * Return: 0 on success or a negative error code on failure. 476 */ 477 int xe_pat_dump(struct xe_gt *gt, struct drm_printer *p) 478 { 479 struct xe_device *xe = gt_to_xe(gt); 480 481 if (!xe->pat.ops) 482 return -EOPNOTSUPP; 483 484 return xe->pat.ops->dump(gt, p); 485 } 486