1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 #include "xe_lrc.h" 7 8 #include <generated/xe_wa_oob.h> 9 10 #include <linux/ascii85.h> 11 12 #include "instructions/xe_mi_commands.h" 13 #include "instructions/xe_gfxpipe_commands.h" 14 #include "instructions/xe_gfx_state_commands.h" 15 #include "regs/xe_engine_regs.h" 16 #include "regs/xe_lrc_layout.h" 17 #include "xe_bb.h" 18 #include "xe_bo.h" 19 #include "xe_device.h" 20 #include "xe_drm_client.h" 21 #include "xe_exec_queue_types.h" 22 #include "xe_gt.h" 23 #include "xe_gt_printk.h" 24 #include "xe_hw_fence.h" 25 #include "xe_map.h" 26 #include "xe_memirq.h" 27 #include "xe_mmio.h" 28 #include "xe_sriov.h" 29 #include "xe_trace_lrc.h" 30 #include "xe_vm.h" 31 #include "xe_wa.h" 32 33 #define LRC_VALID BIT_ULL(0) 34 #define LRC_PRIVILEGE BIT_ULL(8) 35 #define LRC_ADDRESSING_MODE GENMASK_ULL(4, 3) 36 #define LRC_LEGACY_64B_CONTEXT 3 37 38 #define LRC_ENGINE_CLASS GENMASK_ULL(63, 61) 39 #define LRC_ENGINE_INSTANCE GENMASK_ULL(53, 48) 40 41 #define LRC_PPHWSP_SIZE SZ_4K 42 #define LRC_INDIRECT_RING_STATE_SIZE SZ_4K 43 44 static struct xe_device * 45 lrc_to_xe(struct xe_lrc *lrc) 46 { 47 return gt_to_xe(lrc->fence_ctx.gt); 48 } 49 50 size_t xe_gt_lrc_size(struct xe_gt *gt, enum xe_engine_class class) 51 { 52 struct xe_device *xe = gt_to_xe(gt); 53 size_t size; 54 55 /* Per-process HW status page (PPHWSP) */ 56 size = LRC_PPHWSP_SIZE; 57 58 /* Engine context image */ 59 switch (class) { 60 case XE_ENGINE_CLASS_RENDER: 61 if (GRAPHICS_VER(xe) >= 20) 62 size += 3 * SZ_4K; 63 else 64 size += 13 * SZ_4K; 65 break; 66 case XE_ENGINE_CLASS_COMPUTE: 67 if (GRAPHICS_VER(xe) >= 20) 68 size += 2 * SZ_4K; 69 else 70 size += 13 * SZ_4K; 71 break; 72 default: 73 WARN(1, "Unknown engine class: %d", class); 74 fallthrough; 75 case XE_ENGINE_CLASS_COPY: 76 case XE_ENGINE_CLASS_VIDEO_DECODE: 77 case XE_ENGINE_CLASS_VIDEO_ENHANCE: 78 case XE_ENGINE_CLASS_OTHER: 79 size += 1 * SZ_4K; 80 } 81 82 /* Add indirect ring state page */ 83 if (xe_gt_has_indirect_ring_state(gt)) 84 size += LRC_INDIRECT_RING_STATE_SIZE; 85 86 return size; 87 } 88 89 /* 90 * The per-platform tables are u8-encoded in @data. Decode @data and set the 91 * addresses' offset and commands in @regs. The following encoding is used 92 * for each byte. There are 2 steps: decoding commands and decoding addresses. 93 * 94 * Commands: 95 * [7]: create NOPs - number of NOPs are set in lower bits 96 * [6]: When creating MI_LOAD_REGISTER_IMM command, allow to set 97 * MI_LRI_FORCE_POSTED 98 * [5:0]: Number of NOPs or registers to set values to in case of 99 * MI_LOAD_REGISTER_IMM 100 * 101 * Addresses: these are decoded after a MI_LOAD_REGISTER_IMM command by "count" 102 * number of registers. They are set by using the REG/REG16 macros: the former 103 * is used for offsets smaller than 0x200 while the latter is for values bigger 104 * than that. Those macros already set all the bits documented below correctly: 105 * 106 * [7]: When a register offset needs more than 6 bits, use additional bytes, to 107 * follow, for the lower bits 108 * [6:0]: Register offset, without considering the engine base. 109 * 110 * This function only tweaks the commands and register offsets. Values are not 111 * filled out. 112 */ 113 static void set_offsets(u32 *regs, 114 const u8 *data, 115 const struct xe_hw_engine *hwe) 116 #define NOP(x) (BIT(7) | (x)) 117 #define LRI(count, flags) ((flags) << 6 | (count) | \ 118 BUILD_BUG_ON_ZERO(count >= BIT(6))) 119 #define POSTED BIT(0) 120 #define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200)) 121 #define REG16(x) \ 122 (((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x10000)), \ 123 (((x) >> 2) & 0x7f) 124 { 125 const u32 base = hwe->mmio_base; 126 127 while (*data) { 128 u8 count, flags; 129 130 if (*data & BIT(7)) { /* skip */ 131 count = *data++ & ~BIT(7); 132 regs += count; 133 continue; 134 } 135 136 count = *data & 0x3f; 137 flags = *data >> 6; 138 data++; 139 140 *regs = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(count); 141 if (flags & POSTED) 142 *regs |= MI_LRI_FORCE_POSTED; 143 *regs |= MI_LRI_LRM_CS_MMIO; 144 regs++; 145 146 xe_gt_assert(hwe->gt, count); 147 do { 148 u32 offset = 0; 149 u8 v; 150 151 do { 152 v = *data++; 153 offset <<= 7; 154 offset |= v & ~BIT(7); 155 } while (v & BIT(7)); 156 157 regs[0] = base + (offset << 2); 158 regs += 2; 159 } while (--count); 160 } 161 162 *regs = MI_BATCH_BUFFER_END | BIT(0); 163 } 164 165 static const u8 gen12_xcs_offsets[] = { 166 NOP(1), 167 LRI(13, POSTED), 168 REG16(0x244), 169 REG(0x034), 170 REG(0x030), 171 REG(0x038), 172 REG(0x03c), 173 REG(0x168), 174 REG(0x140), 175 REG(0x110), 176 REG(0x1c0), 177 REG(0x1c4), 178 REG(0x1c8), 179 REG(0x180), 180 REG16(0x2b4), 181 182 NOP(5), 183 LRI(9, POSTED), 184 REG16(0x3a8), 185 REG16(0x28c), 186 REG16(0x288), 187 REG16(0x284), 188 REG16(0x280), 189 REG16(0x27c), 190 REG16(0x278), 191 REG16(0x274), 192 REG16(0x270), 193 194 0 195 }; 196 197 static const u8 dg2_xcs_offsets[] = { 198 NOP(1), 199 LRI(15, POSTED), 200 REG16(0x244), 201 REG(0x034), 202 REG(0x030), 203 REG(0x038), 204 REG(0x03c), 205 REG(0x168), 206 REG(0x140), 207 REG(0x110), 208 REG(0x1c0), 209 REG(0x1c4), 210 REG(0x1c8), 211 REG(0x180), 212 REG16(0x2b4), 213 REG(0x120), 214 REG(0x124), 215 216 NOP(1), 217 LRI(9, POSTED), 218 REG16(0x3a8), 219 REG16(0x28c), 220 REG16(0x288), 221 REG16(0x284), 222 REG16(0x280), 223 REG16(0x27c), 224 REG16(0x278), 225 REG16(0x274), 226 REG16(0x270), 227 228 0 229 }; 230 231 static const u8 gen12_rcs_offsets[] = { 232 NOP(1), 233 LRI(13, POSTED), 234 REG16(0x244), 235 REG(0x034), 236 REG(0x030), 237 REG(0x038), 238 REG(0x03c), 239 REG(0x168), 240 REG(0x140), 241 REG(0x110), 242 REG(0x1c0), 243 REG(0x1c4), 244 REG(0x1c8), 245 REG(0x180), 246 REG16(0x2b4), 247 248 NOP(5), 249 LRI(9, POSTED), 250 REG16(0x3a8), 251 REG16(0x28c), 252 REG16(0x288), 253 REG16(0x284), 254 REG16(0x280), 255 REG16(0x27c), 256 REG16(0x278), 257 REG16(0x274), 258 REG16(0x270), 259 260 LRI(3, POSTED), 261 REG(0x1b0), 262 REG16(0x5a8), 263 REG16(0x5ac), 264 265 NOP(6), 266 LRI(1, 0), 267 REG(0x0c8), 268 NOP(3 + 9 + 1), 269 270 LRI(51, POSTED), 271 REG16(0x588), 272 REG16(0x588), 273 REG16(0x588), 274 REG16(0x588), 275 REG16(0x588), 276 REG16(0x588), 277 REG(0x028), 278 REG(0x09c), 279 REG(0x0c0), 280 REG(0x178), 281 REG(0x17c), 282 REG16(0x358), 283 REG(0x170), 284 REG(0x150), 285 REG(0x154), 286 REG(0x158), 287 REG16(0x41c), 288 REG16(0x600), 289 REG16(0x604), 290 REG16(0x608), 291 REG16(0x60c), 292 REG16(0x610), 293 REG16(0x614), 294 REG16(0x618), 295 REG16(0x61c), 296 REG16(0x620), 297 REG16(0x624), 298 REG16(0x628), 299 REG16(0x62c), 300 REG16(0x630), 301 REG16(0x634), 302 REG16(0x638), 303 REG16(0x63c), 304 REG16(0x640), 305 REG16(0x644), 306 REG16(0x648), 307 REG16(0x64c), 308 REG16(0x650), 309 REG16(0x654), 310 REG16(0x658), 311 REG16(0x65c), 312 REG16(0x660), 313 REG16(0x664), 314 REG16(0x668), 315 REG16(0x66c), 316 REG16(0x670), 317 REG16(0x674), 318 REG16(0x678), 319 REG16(0x67c), 320 REG(0x068), 321 REG(0x084), 322 NOP(1), 323 324 0 325 }; 326 327 static const u8 xehp_rcs_offsets[] = { 328 NOP(1), 329 LRI(13, POSTED), 330 REG16(0x244), 331 REG(0x034), 332 REG(0x030), 333 REG(0x038), 334 REG(0x03c), 335 REG(0x168), 336 REG(0x140), 337 REG(0x110), 338 REG(0x1c0), 339 REG(0x1c4), 340 REG(0x1c8), 341 REG(0x180), 342 REG16(0x2b4), 343 344 NOP(5), 345 LRI(9, POSTED), 346 REG16(0x3a8), 347 REG16(0x28c), 348 REG16(0x288), 349 REG16(0x284), 350 REG16(0x280), 351 REG16(0x27c), 352 REG16(0x278), 353 REG16(0x274), 354 REG16(0x270), 355 356 LRI(3, POSTED), 357 REG(0x1b0), 358 REG16(0x5a8), 359 REG16(0x5ac), 360 361 NOP(6), 362 LRI(1, 0), 363 REG(0x0c8), 364 365 0 366 }; 367 368 static const u8 dg2_rcs_offsets[] = { 369 NOP(1), 370 LRI(15, POSTED), 371 REG16(0x244), 372 REG(0x034), 373 REG(0x030), 374 REG(0x038), 375 REG(0x03c), 376 REG(0x168), 377 REG(0x140), 378 REG(0x110), 379 REG(0x1c0), 380 REG(0x1c4), 381 REG(0x1c8), 382 REG(0x180), 383 REG16(0x2b4), 384 REG(0x120), 385 REG(0x124), 386 387 NOP(1), 388 LRI(9, POSTED), 389 REG16(0x3a8), 390 REG16(0x28c), 391 REG16(0x288), 392 REG16(0x284), 393 REG16(0x280), 394 REG16(0x27c), 395 REG16(0x278), 396 REG16(0x274), 397 REG16(0x270), 398 399 LRI(3, POSTED), 400 REG(0x1b0), 401 REG16(0x5a8), 402 REG16(0x5ac), 403 404 NOP(6), 405 LRI(1, 0), 406 REG(0x0c8), 407 408 0 409 }; 410 411 static const u8 mtl_rcs_offsets[] = { 412 NOP(1), 413 LRI(15, POSTED), 414 REG16(0x244), 415 REG(0x034), 416 REG(0x030), 417 REG(0x038), 418 REG(0x03c), 419 REG(0x168), 420 REG(0x140), 421 REG(0x110), 422 REG(0x1c0), 423 REG(0x1c4), 424 REG(0x1c8), 425 REG(0x180), 426 REG16(0x2b4), 427 REG(0x120), 428 REG(0x124), 429 430 NOP(1), 431 LRI(9, POSTED), 432 REG16(0x3a8), 433 REG16(0x28c), 434 REG16(0x288), 435 REG16(0x284), 436 REG16(0x280), 437 REG16(0x27c), 438 REG16(0x278), 439 REG16(0x274), 440 REG16(0x270), 441 442 NOP(2), 443 LRI(2, POSTED), 444 REG16(0x5a8), 445 REG16(0x5ac), 446 447 NOP(6), 448 LRI(1, 0), 449 REG(0x0c8), 450 451 0 452 }; 453 454 #define XE2_CTX_COMMON \ 455 NOP(1), /* [0x00] */ \ 456 LRI(15, POSTED), /* [0x01] */ \ 457 REG16(0x244), /* [0x02] CTXT_SR_CTL */ \ 458 REG(0x034), /* [0x04] RING_BUFFER_HEAD */ \ 459 REG(0x030), /* [0x06] RING_BUFFER_TAIL */ \ 460 REG(0x038), /* [0x08] RING_BUFFER_START */ \ 461 REG(0x03c), /* [0x0a] RING_BUFFER_CONTROL */ \ 462 REG(0x168), /* [0x0c] BB_ADDR_UDW */ \ 463 REG(0x140), /* [0x0e] BB_ADDR */ \ 464 REG(0x110), /* [0x10] BB_STATE */ \ 465 REG(0x1c0), /* [0x12] BB_PER_CTX_PTR */ \ 466 REG(0x1c4), /* [0x14] RCS_INDIRECT_CTX */ \ 467 REG(0x1c8), /* [0x16] RCS_INDIRECT_CTX_OFFSET */ \ 468 REG(0x180), /* [0x18] CCID */ \ 469 REG16(0x2b4), /* [0x1a] SEMAPHORE_TOKEN */ \ 470 REG(0x120), /* [0x1c] PRT_BB_STATE */ \ 471 REG(0x124), /* [0x1e] PRT_BB_STATE_UDW */ \ 472 \ 473 NOP(1), /* [0x20] */ \ 474 LRI(9, POSTED), /* [0x21] */ \ 475 REG16(0x3a8), /* [0x22] CTX_TIMESTAMP */ \ 476 REG16(0x3ac), /* [0x24] CTX_TIMESTAMP_UDW */ \ 477 REG(0x108), /* [0x26] INDIRECT_RING_STATE */ \ 478 REG16(0x284), /* [0x28] dummy reg */ \ 479 REG16(0x280), /* [0x2a] CS_ACC_CTR_THOLD */ \ 480 REG16(0x27c), /* [0x2c] CS_CTX_SYS_PASID */ \ 481 REG16(0x278), /* [0x2e] CS_CTX_ASID */ \ 482 REG16(0x274), /* [0x30] PTBP_UDW */ \ 483 REG16(0x270) /* [0x32] PTBP_LDW */ 484 485 static const u8 xe2_rcs_offsets[] = { 486 XE2_CTX_COMMON, 487 488 NOP(2), /* [0x34] */ 489 LRI(2, POSTED), /* [0x36] */ 490 REG16(0x5a8), /* [0x37] CONTEXT_SCHEDULING_ATTRIBUTES */ 491 REG16(0x5ac), /* [0x39] PREEMPTION_STATUS */ 492 493 NOP(6), /* [0x41] */ 494 LRI(1, 0), /* [0x47] */ 495 REG(0x0c8), /* [0x48] R_PWR_CLK_STATE */ 496 497 0 498 }; 499 500 static const u8 xe2_bcs_offsets[] = { 501 XE2_CTX_COMMON, 502 503 NOP(4 + 8 + 1), /* [0x34] */ 504 LRI(2, POSTED), /* [0x41] */ 505 REG16(0x200), /* [0x42] BCS_SWCTRL */ 506 REG16(0x204), /* [0x44] BLIT_CCTL */ 507 508 0 509 }; 510 511 static const u8 xe2_xcs_offsets[] = { 512 XE2_CTX_COMMON, 513 514 0 515 }; 516 517 static const u8 xe2_indirect_ring_state_offsets[] = { 518 NOP(1), /* [0x00] */ 519 LRI(5, POSTED), /* [0x01] */ 520 REG(0x034), /* [0x02] RING_BUFFER_HEAD */ 521 REG(0x030), /* [0x04] RING_BUFFER_TAIL */ 522 REG(0x038), /* [0x06] RING_BUFFER_START */ 523 REG(0x048), /* [0x08] RING_BUFFER_START_UDW */ 524 REG(0x03c), /* [0x0a] RING_BUFFER_CONTROL */ 525 526 NOP(5), /* [0x0c] */ 527 LRI(9, POSTED), /* [0x11] */ 528 REG(0x168), /* [0x12] BB_ADDR_UDW */ 529 REG(0x140), /* [0x14] BB_ADDR */ 530 REG(0x110), /* [0x16] BB_STATE */ 531 REG16(0x588), /* [0x18] BB_STACK_WRITE_PORT */ 532 REG16(0x588), /* [0x20] BB_STACK_WRITE_PORT */ 533 REG16(0x588), /* [0x22] BB_STACK_WRITE_PORT */ 534 REG16(0x588), /* [0x24] BB_STACK_WRITE_PORT */ 535 REG16(0x588), /* [0x26] BB_STACK_WRITE_PORT */ 536 REG16(0x588), /* [0x28] BB_STACK_WRITE_PORT */ 537 538 NOP(12), /* [0x00] */ 539 540 0 541 }; 542 543 #undef REG16 544 #undef REG 545 #undef LRI 546 #undef NOP 547 548 static const u8 *reg_offsets(struct xe_device *xe, enum xe_engine_class class) 549 { 550 if (class == XE_ENGINE_CLASS_RENDER) { 551 if (GRAPHICS_VER(xe) >= 20) 552 return xe2_rcs_offsets; 553 else if (GRAPHICS_VERx100(xe) >= 1270) 554 return mtl_rcs_offsets; 555 else if (GRAPHICS_VERx100(xe) >= 1255) 556 return dg2_rcs_offsets; 557 else if (GRAPHICS_VERx100(xe) >= 1250) 558 return xehp_rcs_offsets; 559 else 560 return gen12_rcs_offsets; 561 } else if (class == XE_ENGINE_CLASS_COPY) { 562 if (GRAPHICS_VER(xe) >= 20) 563 return xe2_bcs_offsets; 564 else 565 return gen12_xcs_offsets; 566 } else { 567 if (GRAPHICS_VER(xe) >= 20) 568 return xe2_xcs_offsets; 569 else if (GRAPHICS_VERx100(xe) >= 1255) 570 return dg2_xcs_offsets; 571 else 572 return gen12_xcs_offsets; 573 } 574 } 575 576 static void set_context_control(u32 *regs, struct xe_hw_engine *hwe) 577 { 578 regs[CTX_CONTEXT_CONTROL] = _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH | 579 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); 580 581 if (xe_gt_has_indirect_ring_state(hwe->gt)) 582 regs[CTX_CONTEXT_CONTROL] |= 583 _MASKED_BIT_ENABLE(CTX_CTRL_INDIRECT_RING_STATE_ENABLE); 584 585 /* TODO: Timestamp */ 586 } 587 588 static void set_memory_based_intr(u32 *regs, struct xe_hw_engine *hwe) 589 { 590 struct xe_memirq *memirq = >_to_tile(hwe->gt)->memirq; 591 struct xe_device *xe = gt_to_xe(hwe->gt); 592 u8 num_regs; 593 594 if (!xe_device_uses_memirq(xe)) 595 return; 596 597 regs[CTX_LRM_INT_MASK_ENABLE] = MI_LOAD_REGISTER_MEM | 598 MI_LRI_LRM_CS_MMIO | MI_LRM_USE_GGTT; 599 regs[CTX_INT_MASK_ENABLE_REG] = RING_IMR(0).addr; 600 regs[CTX_INT_MASK_ENABLE_PTR] = xe_memirq_enable_ptr(memirq); 601 602 num_regs = xe_device_has_msix(xe) ? 3 : 2; 603 regs[CTX_LRI_INT_REPORT_PTR] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(num_regs) | 604 MI_LRI_LRM_CS_MMIO | MI_LRI_FORCE_POSTED; 605 regs[CTX_INT_STATUS_REPORT_REG] = RING_INT_STATUS_RPT_PTR(0).addr; 606 regs[CTX_INT_STATUS_REPORT_PTR] = xe_memirq_status_ptr(memirq, hwe); 607 regs[CTX_INT_SRC_REPORT_REG] = RING_INT_SRC_RPT_PTR(0).addr; 608 regs[CTX_INT_SRC_REPORT_PTR] = xe_memirq_source_ptr(memirq, hwe); 609 610 if (xe_device_has_msix(xe)) { 611 regs[CTX_CS_INT_VEC_REG] = CS_INT_VEC(0).addr; 612 /* CTX_CS_INT_VEC_DATA will be set in xe_lrc_init */ 613 } 614 } 615 616 static int lrc_ring_mi_mode(struct xe_hw_engine *hwe) 617 { 618 struct xe_device *xe = gt_to_xe(hwe->gt); 619 620 if (GRAPHICS_VERx100(xe) >= 1250) 621 return 0x70; 622 else 623 return 0x60; 624 } 625 626 static void reset_stop_ring(u32 *regs, struct xe_hw_engine *hwe) 627 { 628 int x; 629 630 x = lrc_ring_mi_mode(hwe); 631 regs[x + 1] &= ~STOP_RING; 632 regs[x + 1] |= STOP_RING << 16; 633 } 634 635 static inline bool xe_lrc_has_indirect_ring_state(struct xe_lrc *lrc) 636 { 637 return lrc->flags & XE_LRC_FLAG_INDIRECT_RING_STATE; 638 } 639 640 static inline u32 __xe_lrc_ring_offset(struct xe_lrc *lrc) 641 { 642 return 0; 643 } 644 645 u32 xe_lrc_pphwsp_offset(struct xe_lrc *lrc) 646 { 647 return lrc->ring.size; 648 } 649 650 /* Make the magic macros work */ 651 #define __xe_lrc_pphwsp_offset xe_lrc_pphwsp_offset 652 #define __xe_lrc_regs_offset xe_lrc_regs_offset 653 654 #define LRC_SEQNO_PPHWSP_OFFSET 512 655 #define LRC_START_SEQNO_PPHWSP_OFFSET (LRC_SEQNO_PPHWSP_OFFSET + 8) 656 #define LRC_CTX_JOB_TIMESTAMP_OFFSET (LRC_START_SEQNO_PPHWSP_OFFSET + 8) 657 #define LRC_PARALLEL_PPHWSP_OFFSET 2048 658 #define LRC_ENGINE_ID_PPHWSP_OFFSET 2096 659 660 u32 xe_lrc_regs_offset(struct xe_lrc *lrc) 661 { 662 return xe_lrc_pphwsp_offset(lrc) + LRC_PPHWSP_SIZE; 663 } 664 665 static size_t lrc_reg_size(struct xe_device *xe) 666 { 667 if (GRAPHICS_VERx100(xe) >= 1250) 668 return 96 * sizeof(u32); 669 else 670 return 80 * sizeof(u32); 671 } 672 673 size_t xe_lrc_skip_size(struct xe_device *xe) 674 { 675 return LRC_PPHWSP_SIZE + lrc_reg_size(xe); 676 } 677 678 static inline u32 __xe_lrc_seqno_offset(struct xe_lrc *lrc) 679 { 680 /* The seqno is stored in the driver-defined portion of PPHWSP */ 681 return xe_lrc_pphwsp_offset(lrc) + LRC_SEQNO_PPHWSP_OFFSET; 682 } 683 684 static inline u32 __xe_lrc_start_seqno_offset(struct xe_lrc *lrc) 685 { 686 /* The start seqno is stored in the driver-defined portion of PPHWSP */ 687 return xe_lrc_pphwsp_offset(lrc) + LRC_START_SEQNO_PPHWSP_OFFSET; 688 } 689 690 static u32 __xe_lrc_ctx_job_timestamp_offset(struct xe_lrc *lrc) 691 { 692 /* This is stored in the driver-defined portion of PPHWSP */ 693 return xe_lrc_pphwsp_offset(lrc) + LRC_CTX_JOB_TIMESTAMP_OFFSET; 694 } 695 696 static inline u32 __xe_lrc_parallel_offset(struct xe_lrc *lrc) 697 { 698 /* The parallel is stored in the driver-defined portion of PPHWSP */ 699 return xe_lrc_pphwsp_offset(lrc) + LRC_PARALLEL_PPHWSP_OFFSET; 700 } 701 702 static inline u32 __xe_lrc_engine_id_offset(struct xe_lrc *lrc) 703 { 704 return xe_lrc_pphwsp_offset(lrc) + LRC_ENGINE_ID_PPHWSP_OFFSET; 705 } 706 707 static u32 __xe_lrc_ctx_timestamp_offset(struct xe_lrc *lrc) 708 { 709 return __xe_lrc_regs_offset(lrc) + CTX_TIMESTAMP * sizeof(u32); 710 } 711 712 static u32 __xe_lrc_ctx_timestamp_udw_offset(struct xe_lrc *lrc) 713 { 714 return __xe_lrc_regs_offset(lrc) + CTX_TIMESTAMP_UDW * sizeof(u32); 715 } 716 717 static inline u32 __xe_lrc_indirect_ring_offset(struct xe_lrc *lrc) 718 { 719 /* Indirect ring state page is at the very end of LRC */ 720 return lrc->size - LRC_INDIRECT_RING_STATE_SIZE; 721 } 722 723 #define DECL_MAP_ADDR_HELPERS(elem) \ 724 static inline struct iosys_map __xe_lrc_##elem##_map(struct xe_lrc *lrc) \ 725 { \ 726 struct iosys_map map = lrc->bo->vmap; \ 727 \ 728 xe_assert(lrc_to_xe(lrc), !iosys_map_is_null(&map)); \ 729 iosys_map_incr(&map, __xe_lrc_##elem##_offset(lrc)); \ 730 return map; \ 731 } \ 732 static inline u32 __maybe_unused __xe_lrc_##elem##_ggtt_addr(struct xe_lrc *lrc) \ 733 { \ 734 return xe_bo_ggtt_addr(lrc->bo) + __xe_lrc_##elem##_offset(lrc); \ 735 } \ 736 737 DECL_MAP_ADDR_HELPERS(ring) 738 DECL_MAP_ADDR_HELPERS(pphwsp) 739 DECL_MAP_ADDR_HELPERS(seqno) 740 DECL_MAP_ADDR_HELPERS(regs) 741 DECL_MAP_ADDR_HELPERS(start_seqno) 742 DECL_MAP_ADDR_HELPERS(ctx_job_timestamp) 743 DECL_MAP_ADDR_HELPERS(ctx_timestamp) 744 DECL_MAP_ADDR_HELPERS(ctx_timestamp_udw) 745 DECL_MAP_ADDR_HELPERS(parallel) 746 DECL_MAP_ADDR_HELPERS(indirect_ring) 747 DECL_MAP_ADDR_HELPERS(engine_id) 748 749 #undef DECL_MAP_ADDR_HELPERS 750 751 /** 752 * xe_lrc_ctx_timestamp_ggtt_addr() - Get ctx timestamp GGTT address 753 * @lrc: Pointer to the lrc. 754 * 755 * Returns: ctx timestamp GGTT address 756 */ 757 u32 xe_lrc_ctx_timestamp_ggtt_addr(struct xe_lrc *lrc) 758 { 759 return __xe_lrc_ctx_timestamp_ggtt_addr(lrc); 760 } 761 762 /** 763 * xe_lrc_ctx_timestamp_udw_ggtt_addr() - Get ctx timestamp udw GGTT address 764 * @lrc: Pointer to the lrc. 765 * 766 * Returns: ctx timestamp udw GGTT address 767 */ 768 u32 xe_lrc_ctx_timestamp_udw_ggtt_addr(struct xe_lrc *lrc) 769 { 770 return __xe_lrc_ctx_timestamp_udw_ggtt_addr(lrc); 771 } 772 773 /** 774 * xe_lrc_ctx_timestamp() - Read ctx timestamp value 775 * @lrc: Pointer to the lrc. 776 * 777 * Returns: ctx timestamp value 778 */ 779 u64 xe_lrc_ctx_timestamp(struct xe_lrc *lrc) 780 { 781 struct xe_device *xe = lrc_to_xe(lrc); 782 struct iosys_map map; 783 u32 ldw, udw = 0; 784 785 map = __xe_lrc_ctx_timestamp_map(lrc); 786 ldw = xe_map_read32(xe, &map); 787 788 if (xe->info.has_64bit_timestamp) { 789 map = __xe_lrc_ctx_timestamp_udw_map(lrc); 790 udw = xe_map_read32(xe, &map); 791 } 792 793 return (u64)udw << 32 | ldw; 794 } 795 796 /** 797 * xe_lrc_ctx_job_timestamp_ggtt_addr() - Get ctx job timestamp GGTT address 798 * @lrc: Pointer to the lrc. 799 * 800 * Returns: ctx timestamp job GGTT address 801 */ 802 u32 xe_lrc_ctx_job_timestamp_ggtt_addr(struct xe_lrc *lrc) 803 { 804 return __xe_lrc_ctx_job_timestamp_ggtt_addr(lrc); 805 } 806 807 /** 808 * xe_lrc_ctx_job_timestamp() - Read ctx job timestamp value 809 * @lrc: Pointer to the lrc. 810 * 811 * Returns: ctx timestamp job value 812 */ 813 u32 xe_lrc_ctx_job_timestamp(struct xe_lrc *lrc) 814 { 815 struct xe_device *xe = lrc_to_xe(lrc); 816 struct iosys_map map; 817 818 map = __xe_lrc_ctx_job_timestamp_map(lrc); 819 return xe_map_read32(xe, &map); 820 } 821 822 u32 xe_lrc_ggtt_addr(struct xe_lrc *lrc) 823 { 824 return __xe_lrc_pphwsp_ggtt_addr(lrc); 825 } 826 827 u32 xe_lrc_indirect_ring_ggtt_addr(struct xe_lrc *lrc) 828 { 829 if (!xe_lrc_has_indirect_ring_state(lrc)) 830 return 0; 831 832 return __xe_lrc_indirect_ring_ggtt_addr(lrc); 833 } 834 835 static u32 xe_lrc_read_indirect_ctx_reg(struct xe_lrc *lrc, int reg_nr) 836 { 837 struct xe_device *xe = lrc_to_xe(lrc); 838 struct iosys_map map; 839 840 map = __xe_lrc_indirect_ring_map(lrc); 841 iosys_map_incr(&map, reg_nr * sizeof(u32)); 842 return xe_map_read32(xe, &map); 843 } 844 845 static void xe_lrc_write_indirect_ctx_reg(struct xe_lrc *lrc, 846 int reg_nr, u32 val) 847 { 848 struct xe_device *xe = lrc_to_xe(lrc); 849 struct iosys_map map; 850 851 map = __xe_lrc_indirect_ring_map(lrc); 852 iosys_map_incr(&map, reg_nr * sizeof(u32)); 853 xe_map_write32(xe, &map, val); 854 } 855 856 u32 xe_lrc_read_ctx_reg(struct xe_lrc *lrc, int reg_nr) 857 { 858 struct xe_device *xe = lrc_to_xe(lrc); 859 struct iosys_map map; 860 861 map = __xe_lrc_regs_map(lrc); 862 iosys_map_incr(&map, reg_nr * sizeof(u32)); 863 return xe_map_read32(xe, &map); 864 } 865 866 void xe_lrc_write_ctx_reg(struct xe_lrc *lrc, int reg_nr, u32 val) 867 { 868 struct xe_device *xe = lrc_to_xe(lrc); 869 struct iosys_map map; 870 871 map = __xe_lrc_regs_map(lrc); 872 iosys_map_incr(&map, reg_nr * sizeof(u32)); 873 xe_map_write32(xe, &map, val); 874 } 875 876 static void *empty_lrc_data(struct xe_hw_engine *hwe) 877 { 878 struct xe_gt *gt = hwe->gt; 879 void *data; 880 u32 *regs; 881 882 data = kzalloc(xe_gt_lrc_size(gt, hwe->class), GFP_KERNEL); 883 if (!data) 884 return NULL; 885 886 /* 1st page: Per-Process of HW status Page */ 887 regs = data + LRC_PPHWSP_SIZE; 888 set_offsets(regs, reg_offsets(gt_to_xe(gt), hwe->class), hwe); 889 set_context_control(regs, hwe); 890 set_memory_based_intr(regs, hwe); 891 reset_stop_ring(regs, hwe); 892 if (xe_gt_has_indirect_ring_state(gt)) { 893 regs = data + xe_gt_lrc_size(gt, hwe->class) - 894 LRC_INDIRECT_RING_STATE_SIZE; 895 set_offsets(regs, xe2_indirect_ring_state_offsets, hwe); 896 } 897 898 return data; 899 } 900 901 static void xe_lrc_set_ppgtt(struct xe_lrc *lrc, struct xe_vm *vm) 902 { 903 u64 desc = xe_vm_pdp4_descriptor(vm, gt_to_tile(lrc->gt)); 904 905 xe_lrc_write_ctx_reg(lrc, CTX_PDP0_UDW, upper_32_bits(desc)); 906 xe_lrc_write_ctx_reg(lrc, CTX_PDP0_LDW, lower_32_bits(desc)); 907 } 908 909 static void xe_lrc_finish(struct xe_lrc *lrc) 910 { 911 xe_hw_fence_ctx_finish(&lrc->fence_ctx); 912 xe_bo_unpin_map_no_vm(lrc->bo); 913 xe_bo_unpin_map_no_vm(lrc->bb_per_ctx_bo); 914 } 915 916 /* 917 * xe_lrc_setup_utilization() - Setup wa bb to assist in calculating active 918 * context run ticks. 919 * @lrc: Pointer to the lrc. 920 * 921 * Context Timestamp (CTX_TIMESTAMP) in the LRC accumulates the run ticks of the 922 * context, but only gets updated when the context switches out. In order to 923 * check how long a context has been active before it switches out, two things 924 * are required: 925 * 926 * (1) Determine if the context is running: 927 * To do so, we program the WA BB to set an initial value for CTX_TIMESTAMP in 928 * the LRC. The value chosen is 1 since 0 is the initial value when the LRC is 929 * initialized. During a query, we just check for this value to determine if the 930 * context is active. If the context switched out, it would overwrite this 931 * location with the actual CTX_TIMESTAMP MMIO value. Note that WA BB runs as 932 * the last part of context restore, so reusing this LRC location will not 933 * clobber anything. 934 * 935 * (2) Calculate the time that the context has been active for: 936 * The CTX_TIMESTAMP ticks only when the context is active. If a context is 937 * active, we just use the CTX_TIMESTAMP MMIO as the new value of utilization. 938 * While doing so, we need to read the CTX_TIMESTAMP MMIO for the specific 939 * engine instance. Since we do not know which instance the context is running 940 * on until it is scheduled, we also read the ENGINE_ID MMIO in the WA BB and 941 * store it in the PPHSWP. 942 */ 943 #define CONTEXT_ACTIVE 1ULL 944 static void xe_lrc_setup_utilization(struct xe_lrc *lrc) 945 { 946 u32 *cmd; 947 948 cmd = lrc->bb_per_ctx_bo->vmap.vaddr; 949 950 *cmd++ = MI_STORE_REGISTER_MEM | MI_SRM_USE_GGTT | MI_SRM_ADD_CS_OFFSET; 951 *cmd++ = ENGINE_ID(0).addr; 952 *cmd++ = __xe_lrc_engine_id_ggtt_addr(lrc); 953 *cmd++ = 0; 954 955 *cmd++ = MI_STORE_DATA_IMM | MI_SDI_GGTT | MI_SDI_NUM_DW(1); 956 *cmd++ = __xe_lrc_ctx_timestamp_ggtt_addr(lrc); 957 *cmd++ = 0; 958 *cmd++ = lower_32_bits(CONTEXT_ACTIVE); 959 960 if (lrc_to_xe(lrc)->info.has_64bit_timestamp) { 961 *cmd++ = MI_STORE_DATA_IMM | MI_SDI_GGTT | MI_SDI_NUM_DW(1); 962 *cmd++ = __xe_lrc_ctx_timestamp_udw_ggtt_addr(lrc); 963 *cmd++ = 0; 964 *cmd++ = upper_32_bits(CONTEXT_ACTIVE); 965 } 966 967 *cmd++ = MI_BATCH_BUFFER_END; 968 969 xe_lrc_write_ctx_reg(lrc, CTX_BB_PER_CTX_PTR, 970 xe_bo_ggtt_addr(lrc->bb_per_ctx_bo) | 1); 971 972 } 973 974 #define PVC_CTX_ASID (0x2e + 1) 975 #define PVC_CTX_ACC_CTR_THOLD (0x2a + 1) 976 977 static int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe, 978 struct xe_vm *vm, u32 ring_size, u16 msix_vec, 979 u32 init_flags) 980 { 981 struct xe_gt *gt = hwe->gt; 982 struct xe_tile *tile = gt_to_tile(gt); 983 struct xe_device *xe = gt_to_xe(gt); 984 struct iosys_map map; 985 void *init_data = NULL; 986 u32 arb_enable; 987 u32 lrc_size; 988 u32 bo_flags; 989 int err; 990 991 kref_init(&lrc->refcount); 992 lrc->gt = gt; 993 lrc->flags = 0; 994 lrc_size = ring_size + xe_gt_lrc_size(gt, hwe->class); 995 if (xe_gt_has_indirect_ring_state(gt)) 996 lrc->flags |= XE_LRC_FLAG_INDIRECT_RING_STATE; 997 998 bo_flags = XE_BO_FLAG_VRAM_IF_DGFX(tile) | XE_BO_FLAG_GGTT | 999 XE_BO_FLAG_GGTT_INVALIDATE; 1000 if (vm && vm->xef) /* userspace */ 1001 bo_flags |= XE_BO_FLAG_PINNED_LATE_RESTORE; 1002 1003 /* 1004 * FIXME: Perma-pinning LRC as we don't yet support moving GGTT address 1005 * via VM bind calls. 1006 */ 1007 lrc->bo = xe_bo_create_pin_map(xe, tile, NULL, lrc_size, 1008 ttm_bo_type_kernel, 1009 bo_flags); 1010 if (IS_ERR(lrc->bo)) 1011 return PTR_ERR(lrc->bo); 1012 1013 lrc->bb_per_ctx_bo = xe_bo_create_pin_map(xe, tile, NULL, SZ_4K, 1014 ttm_bo_type_kernel, 1015 bo_flags); 1016 if (IS_ERR(lrc->bb_per_ctx_bo)) { 1017 err = PTR_ERR(lrc->bb_per_ctx_bo); 1018 goto err_lrc_finish; 1019 } 1020 1021 lrc->size = lrc_size; 1022 lrc->ring.size = ring_size; 1023 lrc->ring.tail = 0; 1024 1025 xe_hw_fence_ctx_init(&lrc->fence_ctx, hwe->gt, 1026 hwe->fence_irq, hwe->name); 1027 1028 if (!gt->default_lrc[hwe->class]) { 1029 init_data = empty_lrc_data(hwe); 1030 if (!init_data) { 1031 err = -ENOMEM; 1032 goto err_lrc_finish; 1033 } 1034 } 1035 1036 /* 1037 * Init Per-Process of HW status Page, LRC / context state to known 1038 * values 1039 */ 1040 map = __xe_lrc_pphwsp_map(lrc); 1041 if (!init_data) { 1042 xe_map_memset(xe, &map, 0, 0, LRC_PPHWSP_SIZE); /* PPHWSP */ 1043 xe_map_memcpy_to(xe, &map, LRC_PPHWSP_SIZE, 1044 gt->default_lrc[hwe->class] + LRC_PPHWSP_SIZE, 1045 xe_gt_lrc_size(gt, hwe->class) - LRC_PPHWSP_SIZE); 1046 } else { 1047 xe_map_memcpy_to(xe, &map, 0, init_data, 1048 xe_gt_lrc_size(gt, hwe->class)); 1049 kfree(init_data); 1050 } 1051 1052 if (vm) { 1053 xe_lrc_set_ppgtt(lrc, vm); 1054 1055 if (vm->xef) 1056 xe_drm_client_add_bo(vm->xef->client, lrc->bo); 1057 } 1058 1059 if (xe_device_has_msix(xe)) { 1060 xe_lrc_write_ctx_reg(lrc, CTX_INT_STATUS_REPORT_PTR, 1061 xe_memirq_status_ptr(&tile->memirq, hwe)); 1062 xe_lrc_write_ctx_reg(lrc, CTX_INT_SRC_REPORT_PTR, 1063 xe_memirq_source_ptr(&tile->memirq, hwe)); 1064 xe_lrc_write_ctx_reg(lrc, CTX_CS_INT_VEC_DATA, msix_vec << 16 | msix_vec); 1065 } 1066 1067 if (xe_gt_has_indirect_ring_state(gt)) { 1068 xe_lrc_write_ctx_reg(lrc, CTX_INDIRECT_RING_STATE, 1069 __xe_lrc_indirect_ring_ggtt_addr(lrc)); 1070 1071 xe_lrc_write_indirect_ctx_reg(lrc, INDIRECT_CTX_RING_START, 1072 __xe_lrc_ring_ggtt_addr(lrc)); 1073 xe_lrc_write_indirect_ctx_reg(lrc, INDIRECT_CTX_RING_START_UDW, 0); 1074 xe_lrc_write_indirect_ctx_reg(lrc, INDIRECT_CTX_RING_HEAD, 0); 1075 xe_lrc_write_indirect_ctx_reg(lrc, INDIRECT_CTX_RING_TAIL, lrc->ring.tail); 1076 xe_lrc_write_indirect_ctx_reg(lrc, INDIRECT_CTX_RING_CTL, 1077 RING_CTL_SIZE(lrc->ring.size) | RING_VALID); 1078 } else { 1079 xe_lrc_write_ctx_reg(lrc, CTX_RING_START, __xe_lrc_ring_ggtt_addr(lrc)); 1080 xe_lrc_write_ctx_reg(lrc, CTX_RING_HEAD, 0); 1081 xe_lrc_write_ctx_reg(lrc, CTX_RING_TAIL, lrc->ring.tail); 1082 xe_lrc_write_ctx_reg(lrc, CTX_RING_CTL, 1083 RING_CTL_SIZE(lrc->ring.size) | RING_VALID); 1084 } 1085 1086 if (init_flags & XE_LRC_CREATE_RUNALONE) 1087 xe_lrc_write_ctx_reg(lrc, CTX_CONTEXT_CONTROL, 1088 xe_lrc_read_ctx_reg(lrc, CTX_CONTEXT_CONTROL) | 1089 _MASKED_BIT_ENABLE(CTX_CTRL_RUN_ALONE)); 1090 1091 if (init_flags & XE_LRC_CREATE_PXP) 1092 xe_lrc_write_ctx_reg(lrc, CTX_CONTEXT_CONTROL, 1093 xe_lrc_read_ctx_reg(lrc, CTX_CONTEXT_CONTROL) | 1094 _MASKED_BIT_ENABLE(CTX_CTRL_PXP_ENABLE)); 1095 1096 lrc->ctx_timestamp = 0; 1097 xe_lrc_write_ctx_reg(lrc, CTX_TIMESTAMP, 0); 1098 if (lrc_to_xe(lrc)->info.has_64bit_timestamp) 1099 xe_lrc_write_ctx_reg(lrc, CTX_TIMESTAMP_UDW, 0); 1100 1101 if (xe->info.has_asid && vm) 1102 xe_lrc_write_ctx_reg(lrc, PVC_CTX_ASID, vm->usm.asid); 1103 1104 lrc->desc = LRC_VALID; 1105 lrc->desc |= FIELD_PREP(LRC_ADDRESSING_MODE, LRC_LEGACY_64B_CONTEXT); 1106 /* TODO: Priority */ 1107 1108 /* While this appears to have something about privileged batches or 1109 * some such, it really just means PPGTT mode. 1110 */ 1111 if (vm) 1112 lrc->desc |= LRC_PRIVILEGE; 1113 1114 if (GRAPHICS_VERx100(xe) < 1250) { 1115 lrc->desc |= FIELD_PREP(LRC_ENGINE_INSTANCE, hwe->instance); 1116 lrc->desc |= FIELD_PREP(LRC_ENGINE_CLASS, hwe->class); 1117 } 1118 1119 arb_enable = MI_ARB_ON_OFF | MI_ARB_ENABLE; 1120 xe_lrc_write_ring(lrc, &arb_enable, sizeof(arb_enable)); 1121 1122 map = __xe_lrc_seqno_map(lrc); 1123 xe_map_write32(lrc_to_xe(lrc), &map, lrc->fence_ctx.next_seqno - 1); 1124 1125 map = __xe_lrc_start_seqno_map(lrc); 1126 xe_map_write32(lrc_to_xe(lrc), &map, lrc->fence_ctx.next_seqno - 1); 1127 1128 xe_lrc_setup_utilization(lrc); 1129 1130 return 0; 1131 1132 err_lrc_finish: 1133 xe_lrc_finish(lrc); 1134 return err; 1135 } 1136 1137 /** 1138 * xe_lrc_create - Create a LRC 1139 * @hwe: Hardware Engine 1140 * @vm: The VM (address space) 1141 * @ring_size: LRC ring size 1142 * @msix_vec: MSI-X interrupt vector (for platforms that support it) 1143 * @flags: LRC initialization flags 1144 * 1145 * Allocate and initialize the Logical Ring Context (LRC). 1146 * 1147 * Return pointer to created LRC upon success and an error pointer 1148 * upon failure. 1149 */ 1150 struct xe_lrc *xe_lrc_create(struct xe_hw_engine *hwe, struct xe_vm *vm, 1151 u32 ring_size, u16 msix_vec, u32 flags) 1152 { 1153 struct xe_lrc *lrc; 1154 int err; 1155 1156 lrc = kzalloc(sizeof(*lrc), GFP_KERNEL); 1157 if (!lrc) 1158 return ERR_PTR(-ENOMEM); 1159 1160 err = xe_lrc_init(lrc, hwe, vm, ring_size, msix_vec, flags); 1161 if (err) { 1162 kfree(lrc); 1163 return ERR_PTR(err); 1164 } 1165 1166 return lrc; 1167 } 1168 1169 /** 1170 * xe_lrc_destroy - Destroy the LRC 1171 * @ref: reference to LRC 1172 * 1173 * Called when ref == 0, release resources held by the Logical Ring Context 1174 * (LRC) and free the LRC memory. 1175 */ 1176 void xe_lrc_destroy(struct kref *ref) 1177 { 1178 struct xe_lrc *lrc = container_of(ref, struct xe_lrc, refcount); 1179 1180 xe_lrc_finish(lrc); 1181 kfree(lrc); 1182 } 1183 1184 void xe_lrc_set_ring_tail(struct xe_lrc *lrc, u32 tail) 1185 { 1186 if (xe_lrc_has_indirect_ring_state(lrc)) 1187 xe_lrc_write_indirect_ctx_reg(lrc, INDIRECT_CTX_RING_TAIL, tail); 1188 else 1189 xe_lrc_write_ctx_reg(lrc, CTX_RING_TAIL, tail); 1190 } 1191 1192 u32 xe_lrc_ring_tail(struct xe_lrc *lrc) 1193 { 1194 if (xe_lrc_has_indirect_ring_state(lrc)) 1195 return xe_lrc_read_indirect_ctx_reg(lrc, INDIRECT_CTX_RING_TAIL) & TAIL_ADDR; 1196 else 1197 return xe_lrc_read_ctx_reg(lrc, CTX_RING_TAIL) & TAIL_ADDR; 1198 } 1199 1200 static u32 xe_lrc_ring_start(struct xe_lrc *lrc) 1201 { 1202 if (xe_lrc_has_indirect_ring_state(lrc)) 1203 return xe_lrc_read_indirect_ctx_reg(lrc, INDIRECT_CTX_RING_START); 1204 else 1205 return xe_lrc_read_ctx_reg(lrc, CTX_RING_START); 1206 } 1207 1208 void xe_lrc_set_ring_head(struct xe_lrc *lrc, u32 head) 1209 { 1210 if (xe_lrc_has_indirect_ring_state(lrc)) 1211 xe_lrc_write_indirect_ctx_reg(lrc, INDIRECT_CTX_RING_HEAD, head); 1212 else 1213 xe_lrc_write_ctx_reg(lrc, CTX_RING_HEAD, head); 1214 } 1215 1216 u32 xe_lrc_ring_head(struct xe_lrc *lrc) 1217 { 1218 if (xe_lrc_has_indirect_ring_state(lrc)) 1219 return xe_lrc_read_indirect_ctx_reg(lrc, INDIRECT_CTX_RING_HEAD) & HEAD_ADDR; 1220 else 1221 return xe_lrc_read_ctx_reg(lrc, CTX_RING_HEAD) & HEAD_ADDR; 1222 } 1223 1224 u32 xe_lrc_ring_space(struct xe_lrc *lrc) 1225 { 1226 const u32 head = xe_lrc_ring_head(lrc); 1227 const u32 tail = lrc->ring.tail; 1228 const u32 size = lrc->ring.size; 1229 1230 return ((head - tail - 1) & (size - 1)) + 1; 1231 } 1232 1233 static void __xe_lrc_write_ring(struct xe_lrc *lrc, struct iosys_map ring, 1234 const void *data, size_t size) 1235 { 1236 struct xe_device *xe = lrc_to_xe(lrc); 1237 1238 iosys_map_incr(&ring, lrc->ring.tail); 1239 xe_map_memcpy_to(xe, &ring, 0, data, size); 1240 lrc->ring.tail = (lrc->ring.tail + size) & (lrc->ring.size - 1); 1241 } 1242 1243 void xe_lrc_write_ring(struct xe_lrc *lrc, const void *data, size_t size) 1244 { 1245 struct xe_device *xe = lrc_to_xe(lrc); 1246 struct iosys_map ring; 1247 u32 rhs; 1248 size_t aligned_size; 1249 1250 xe_assert(xe, IS_ALIGNED(size, 4)); 1251 aligned_size = ALIGN(size, 8); 1252 1253 ring = __xe_lrc_ring_map(lrc); 1254 1255 xe_assert(xe, lrc->ring.tail < lrc->ring.size); 1256 rhs = lrc->ring.size - lrc->ring.tail; 1257 if (size > rhs) { 1258 __xe_lrc_write_ring(lrc, ring, data, rhs); 1259 __xe_lrc_write_ring(lrc, ring, data + rhs, size - rhs); 1260 } else { 1261 __xe_lrc_write_ring(lrc, ring, data, size); 1262 } 1263 1264 if (aligned_size > size) { 1265 u32 noop = MI_NOOP; 1266 1267 __xe_lrc_write_ring(lrc, ring, &noop, sizeof(noop)); 1268 } 1269 } 1270 1271 u64 xe_lrc_descriptor(struct xe_lrc *lrc) 1272 { 1273 return lrc->desc | xe_lrc_ggtt_addr(lrc); 1274 } 1275 1276 u32 xe_lrc_seqno_ggtt_addr(struct xe_lrc *lrc) 1277 { 1278 return __xe_lrc_seqno_ggtt_addr(lrc); 1279 } 1280 1281 /** 1282 * xe_lrc_alloc_seqno_fence() - Allocate an lrc seqno fence. 1283 * 1284 * Allocate but don't initialize an lrc seqno fence. 1285 * 1286 * Return: Pointer to the allocated fence or 1287 * negative error pointer on error. 1288 */ 1289 struct dma_fence *xe_lrc_alloc_seqno_fence(void) 1290 { 1291 return xe_hw_fence_alloc(); 1292 } 1293 1294 /** 1295 * xe_lrc_free_seqno_fence() - Free an lrc seqno fence. 1296 * @fence: Pointer to the fence to free. 1297 * 1298 * Frees an lrc seqno fence that hasn't yet been 1299 * initialized. 1300 */ 1301 void xe_lrc_free_seqno_fence(struct dma_fence *fence) 1302 { 1303 xe_hw_fence_free(fence); 1304 } 1305 1306 /** 1307 * xe_lrc_init_seqno_fence() - Initialize an lrc seqno fence. 1308 * @lrc: Pointer to the lrc. 1309 * @fence: Pointer to the fence to initialize. 1310 * 1311 * Initializes a pre-allocated lrc seqno fence. 1312 * After initialization, the fence is subject to normal 1313 * dma-fence refcounting. 1314 */ 1315 void xe_lrc_init_seqno_fence(struct xe_lrc *lrc, struct dma_fence *fence) 1316 { 1317 xe_hw_fence_init(fence, &lrc->fence_ctx, __xe_lrc_seqno_map(lrc)); 1318 } 1319 1320 s32 xe_lrc_seqno(struct xe_lrc *lrc) 1321 { 1322 struct iosys_map map = __xe_lrc_seqno_map(lrc); 1323 1324 return xe_map_read32(lrc_to_xe(lrc), &map); 1325 } 1326 1327 s32 xe_lrc_start_seqno(struct xe_lrc *lrc) 1328 { 1329 struct iosys_map map = __xe_lrc_start_seqno_map(lrc); 1330 1331 return xe_map_read32(lrc_to_xe(lrc), &map); 1332 } 1333 1334 u32 xe_lrc_start_seqno_ggtt_addr(struct xe_lrc *lrc) 1335 { 1336 return __xe_lrc_start_seqno_ggtt_addr(lrc); 1337 } 1338 1339 u32 xe_lrc_parallel_ggtt_addr(struct xe_lrc *lrc) 1340 { 1341 return __xe_lrc_parallel_ggtt_addr(lrc); 1342 } 1343 1344 struct iosys_map xe_lrc_parallel_map(struct xe_lrc *lrc) 1345 { 1346 return __xe_lrc_parallel_map(lrc); 1347 } 1348 1349 /** 1350 * xe_lrc_engine_id() - Read engine id value 1351 * @lrc: Pointer to the lrc. 1352 * 1353 * Returns: context id value 1354 */ 1355 static u32 xe_lrc_engine_id(struct xe_lrc *lrc) 1356 { 1357 struct xe_device *xe = lrc_to_xe(lrc); 1358 struct iosys_map map; 1359 1360 map = __xe_lrc_engine_id_map(lrc); 1361 return xe_map_read32(xe, &map); 1362 } 1363 1364 static int instr_dw(u32 cmd_header) 1365 { 1366 /* GFXPIPE "SINGLE_DW" opcodes are a single dword */ 1367 if ((cmd_header & (XE_INSTR_CMD_TYPE | GFXPIPE_PIPELINE)) == 1368 GFXPIPE_SINGLE_DW_CMD(0, 0)) 1369 return 1; 1370 1371 /* 3DSTATE_SO_DECL_LIST has a 9-bit dword length rather than 8 */ 1372 if ((cmd_header & GFXPIPE_MATCH_MASK) == CMD_3DSTATE_SO_DECL_LIST) 1373 return REG_FIELD_GET(CMD_3DSTATE_SO_DECL_LIST_DW_LEN, cmd_header) + 2; 1374 1375 /* Most instructions have the # of dwords (minus 2) in 7:0 */ 1376 return REG_FIELD_GET(XE_INSTR_LEN_MASK, cmd_header) + 2; 1377 } 1378 1379 static int dump_mi_command(struct drm_printer *p, 1380 struct xe_gt *gt, 1381 u32 *dw, 1382 int remaining_dw) 1383 { 1384 u32 inst_header = *dw; 1385 u32 numdw = instr_dw(inst_header); 1386 u32 opcode = REG_FIELD_GET(MI_OPCODE, inst_header); 1387 int num_noop; 1388 1389 /* First check for commands that don't have/use a '# DW' field */ 1390 switch (inst_header & MI_OPCODE) { 1391 case MI_NOOP: 1392 num_noop = 1; 1393 while (num_noop < remaining_dw && 1394 (*(++dw) & REG_GENMASK(31, 23)) == MI_NOOP) 1395 num_noop++; 1396 drm_printf(p, "[%#010x] MI_NOOP (%d dwords)\n", inst_header, num_noop); 1397 return num_noop; 1398 1399 case MI_TOPOLOGY_FILTER: 1400 drm_printf(p, "[%#010x] MI_TOPOLOGY_FILTER\n", inst_header); 1401 return 1; 1402 1403 case MI_BATCH_BUFFER_END: 1404 drm_printf(p, "[%#010x] MI_BATCH_BUFFER_END\n", inst_header); 1405 /* Return 'remaining_dw' to consume the rest of the LRC */ 1406 return remaining_dw; 1407 } 1408 1409 /* 1410 * Any remaining commands include a # of dwords. We should make sure 1411 * it doesn't exceed the remaining size of the LRC. 1412 */ 1413 if (xe_gt_WARN_ON(gt, numdw > remaining_dw)) 1414 numdw = remaining_dw; 1415 1416 switch (inst_header & MI_OPCODE) { 1417 case MI_LOAD_REGISTER_IMM: 1418 drm_printf(p, "[%#010x] MI_LOAD_REGISTER_IMM: %d regs\n", 1419 inst_header, (numdw - 1) / 2); 1420 for (int i = 1; i < numdw; i += 2) 1421 drm_printf(p, " - %#6x = %#010x\n", dw[i], dw[i + 1]); 1422 return numdw; 1423 1424 case MI_LOAD_REGISTER_MEM & MI_OPCODE: 1425 drm_printf(p, "[%#010x] MI_LOAD_REGISTER_MEM: %s%s\n", 1426 inst_header, 1427 dw[0] & MI_LRI_LRM_CS_MMIO ? "CS_MMIO " : "", 1428 dw[0] & MI_LRM_USE_GGTT ? "USE_GGTT " : ""); 1429 if (numdw == 4) 1430 drm_printf(p, " - %#6x = %#010llx\n", 1431 dw[1], ((u64)(dw[3]) << 32 | (u64)(dw[2]))); 1432 else 1433 drm_printf(p, " - %*ph (%s)\n", 1434 (int)sizeof(u32) * (numdw - 1), dw + 1, 1435 numdw < 4 ? "truncated" : "malformed"); 1436 return numdw; 1437 1438 case MI_FORCE_WAKEUP: 1439 drm_printf(p, "[%#010x] MI_FORCE_WAKEUP\n", inst_header); 1440 return numdw; 1441 1442 default: 1443 drm_printf(p, "[%#010x] unknown MI opcode %#x, likely %d dwords\n", 1444 inst_header, opcode, numdw); 1445 return numdw; 1446 } 1447 } 1448 1449 static int dump_gfxpipe_command(struct drm_printer *p, 1450 struct xe_gt *gt, 1451 u32 *dw, 1452 int remaining_dw) 1453 { 1454 u32 numdw = instr_dw(*dw); 1455 u32 pipeline = REG_FIELD_GET(GFXPIPE_PIPELINE, *dw); 1456 u32 opcode = REG_FIELD_GET(GFXPIPE_OPCODE, *dw); 1457 u32 subopcode = REG_FIELD_GET(GFXPIPE_SUBOPCODE, *dw); 1458 1459 /* 1460 * Make sure we haven't mis-parsed a number of dwords that exceeds the 1461 * remaining size of the LRC. 1462 */ 1463 if (xe_gt_WARN_ON(gt, numdw > remaining_dw)) 1464 numdw = remaining_dw; 1465 1466 switch (*dw & GFXPIPE_MATCH_MASK) { 1467 #define MATCH(cmd) \ 1468 case cmd: \ 1469 drm_printf(p, "[%#010x] " #cmd " (%d dwords)\n", *dw, numdw); \ 1470 return numdw 1471 #define MATCH3D(cmd) \ 1472 case CMD_##cmd: \ 1473 drm_printf(p, "[%#010x] " #cmd " (%d dwords)\n", *dw, numdw); \ 1474 return numdw 1475 1476 MATCH(STATE_BASE_ADDRESS); 1477 MATCH(STATE_SIP); 1478 MATCH(GPGPU_CSR_BASE_ADDRESS); 1479 MATCH(STATE_COMPUTE_MODE); 1480 MATCH3D(3DSTATE_BTD); 1481 MATCH(STATE_SYSTEM_MEM_FENCE_ADDRESS); 1482 MATCH(STATE_CONTEXT_DATA_BASE_ADDRESS); 1483 1484 MATCH3D(3DSTATE_VF_STATISTICS); 1485 1486 MATCH(PIPELINE_SELECT); 1487 1488 MATCH3D(3DSTATE_DRAWING_RECTANGLE_FAST); 1489 MATCH3D(3DSTATE_CLEAR_PARAMS); 1490 MATCH3D(3DSTATE_DEPTH_BUFFER); 1491 MATCH3D(3DSTATE_STENCIL_BUFFER); 1492 MATCH3D(3DSTATE_HIER_DEPTH_BUFFER); 1493 MATCH3D(3DSTATE_VERTEX_BUFFERS); 1494 MATCH3D(3DSTATE_VERTEX_ELEMENTS); 1495 MATCH3D(3DSTATE_INDEX_BUFFER); 1496 MATCH3D(3DSTATE_VF); 1497 MATCH3D(3DSTATE_MULTISAMPLE); 1498 MATCH3D(3DSTATE_CC_STATE_POINTERS); 1499 MATCH3D(3DSTATE_SCISSOR_STATE_POINTERS); 1500 MATCH3D(3DSTATE_VS); 1501 MATCH3D(3DSTATE_GS); 1502 MATCH3D(3DSTATE_CLIP); 1503 MATCH3D(3DSTATE_SF); 1504 MATCH3D(3DSTATE_WM); 1505 MATCH3D(3DSTATE_CONSTANT_VS); 1506 MATCH3D(3DSTATE_CONSTANT_GS); 1507 MATCH3D(3DSTATE_CONSTANT_PS); 1508 MATCH3D(3DSTATE_SAMPLE_MASK); 1509 MATCH3D(3DSTATE_CONSTANT_HS); 1510 MATCH3D(3DSTATE_CONSTANT_DS); 1511 MATCH3D(3DSTATE_HS); 1512 MATCH3D(3DSTATE_TE); 1513 MATCH3D(3DSTATE_DS); 1514 MATCH3D(3DSTATE_STREAMOUT); 1515 MATCH3D(3DSTATE_SBE); 1516 MATCH3D(3DSTATE_PS); 1517 MATCH3D(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP); 1518 MATCH3D(3DSTATE_CPS_POINTERS); 1519 MATCH3D(3DSTATE_VIEWPORT_STATE_POINTERS_CC); 1520 MATCH3D(3DSTATE_BLEND_STATE_POINTERS); 1521 MATCH3D(3DSTATE_BINDING_TABLE_POINTERS_VS); 1522 MATCH3D(3DSTATE_BINDING_TABLE_POINTERS_HS); 1523 MATCH3D(3DSTATE_BINDING_TABLE_POINTERS_DS); 1524 MATCH3D(3DSTATE_BINDING_TABLE_POINTERS_GS); 1525 MATCH3D(3DSTATE_BINDING_TABLE_POINTERS_PS); 1526 MATCH3D(3DSTATE_SAMPLER_STATE_POINTERS_VS); 1527 MATCH3D(3DSTATE_SAMPLER_STATE_POINTERS_HS); 1528 MATCH3D(3DSTATE_SAMPLER_STATE_POINTERS_DS); 1529 MATCH3D(3DSTATE_SAMPLER_STATE_POINTERS_GS); 1530 MATCH3D(3DSTATE_SAMPLER_STATE_POINTERS_PS); 1531 MATCH3D(3DSTATE_VF_INSTANCING); 1532 MATCH3D(3DSTATE_VF_SGVS); 1533 MATCH3D(3DSTATE_VF_TOPOLOGY); 1534 MATCH3D(3DSTATE_WM_CHROMAKEY); 1535 MATCH3D(3DSTATE_PS_BLEND); 1536 MATCH3D(3DSTATE_WM_DEPTH_STENCIL); 1537 MATCH3D(3DSTATE_PS_EXTRA); 1538 MATCH3D(3DSTATE_RASTER); 1539 MATCH3D(3DSTATE_SBE_SWIZ); 1540 MATCH3D(3DSTATE_WM_HZ_OP); 1541 MATCH3D(3DSTATE_VF_COMPONENT_PACKING); 1542 MATCH3D(3DSTATE_VF_SGVS_2); 1543 MATCH3D(3DSTATE_VFG); 1544 MATCH3D(3DSTATE_URB_ALLOC_VS); 1545 MATCH3D(3DSTATE_URB_ALLOC_HS); 1546 MATCH3D(3DSTATE_URB_ALLOC_DS); 1547 MATCH3D(3DSTATE_URB_ALLOC_GS); 1548 MATCH3D(3DSTATE_SO_BUFFER_INDEX_0); 1549 MATCH3D(3DSTATE_SO_BUFFER_INDEX_1); 1550 MATCH3D(3DSTATE_SO_BUFFER_INDEX_2); 1551 MATCH3D(3DSTATE_SO_BUFFER_INDEX_3); 1552 MATCH3D(3DSTATE_PRIMITIVE_REPLICATION); 1553 MATCH3D(3DSTATE_TBIMR_TILE_PASS_INFO); 1554 MATCH3D(3DSTATE_AMFS); 1555 MATCH3D(3DSTATE_DEPTH_BOUNDS); 1556 MATCH3D(3DSTATE_AMFS_TEXTURE_POINTERS); 1557 MATCH3D(3DSTATE_CONSTANT_TS_POINTER); 1558 MATCH3D(3DSTATE_MESH_CONTROL); 1559 MATCH3D(3DSTATE_MESH_DISTRIB); 1560 MATCH3D(3DSTATE_TASK_REDISTRIB); 1561 MATCH3D(3DSTATE_MESH_SHADER); 1562 MATCH3D(3DSTATE_MESH_SHADER_DATA); 1563 MATCH3D(3DSTATE_TASK_CONTROL); 1564 MATCH3D(3DSTATE_TASK_SHADER); 1565 MATCH3D(3DSTATE_TASK_SHADER_DATA); 1566 MATCH3D(3DSTATE_URB_ALLOC_MESH); 1567 MATCH3D(3DSTATE_URB_ALLOC_TASK); 1568 MATCH3D(3DSTATE_CLIP_MESH); 1569 MATCH3D(3DSTATE_SBE_MESH); 1570 MATCH3D(3DSTATE_CPSIZE_CONTROL_BUFFER); 1571 MATCH3D(3DSTATE_COARSE_PIXEL); 1572 1573 MATCH3D(3DSTATE_DRAWING_RECTANGLE); 1574 MATCH3D(3DSTATE_CHROMA_KEY); 1575 MATCH3D(3DSTATE_POLY_STIPPLE_OFFSET); 1576 MATCH3D(3DSTATE_POLY_STIPPLE_PATTERN); 1577 MATCH3D(3DSTATE_LINE_STIPPLE); 1578 MATCH3D(3DSTATE_AA_LINE_PARAMETERS); 1579 MATCH3D(3DSTATE_MONOFILTER_SIZE); 1580 MATCH3D(3DSTATE_PUSH_CONSTANT_ALLOC_VS); 1581 MATCH3D(3DSTATE_PUSH_CONSTANT_ALLOC_HS); 1582 MATCH3D(3DSTATE_PUSH_CONSTANT_ALLOC_DS); 1583 MATCH3D(3DSTATE_PUSH_CONSTANT_ALLOC_GS); 1584 MATCH3D(3DSTATE_PUSH_CONSTANT_ALLOC_PS); 1585 MATCH3D(3DSTATE_SO_DECL_LIST); 1586 MATCH3D(3DSTATE_SO_BUFFER); 1587 MATCH3D(3DSTATE_BINDING_TABLE_POOL_ALLOC); 1588 MATCH3D(3DSTATE_SAMPLE_PATTERN); 1589 MATCH3D(3DSTATE_3D_MODE); 1590 MATCH3D(3DSTATE_SUBSLICE_HASH_TABLE); 1591 MATCH3D(3DSTATE_SLICE_TABLE_STATE_POINTERS); 1592 MATCH3D(3DSTATE_PTBR_TILE_PASS_INFO); 1593 1594 default: 1595 drm_printf(p, "[%#010x] unknown GFXPIPE command (pipeline=%#x, opcode=%#x, subopcode=%#x), likely %d dwords\n", 1596 *dw, pipeline, opcode, subopcode, numdw); 1597 return numdw; 1598 } 1599 } 1600 1601 static int dump_gfx_state_command(struct drm_printer *p, 1602 struct xe_gt *gt, 1603 u32 *dw, 1604 int remaining_dw) 1605 { 1606 u32 numdw = instr_dw(*dw); 1607 u32 opcode = REG_FIELD_GET(GFX_STATE_OPCODE, *dw); 1608 1609 /* 1610 * Make sure we haven't mis-parsed a number of dwords that exceeds the 1611 * remaining size of the LRC. 1612 */ 1613 if (xe_gt_WARN_ON(gt, numdw > remaining_dw)) 1614 numdw = remaining_dw; 1615 1616 switch (*dw & (XE_INSTR_GFX_STATE | GFX_STATE_OPCODE)) { 1617 MATCH(STATE_WRITE_INLINE); 1618 1619 default: 1620 drm_printf(p, "[%#010x] unknown GFX_STATE command (opcode=%#x), likely %d dwords\n", 1621 *dw, opcode, numdw); 1622 return numdw; 1623 } 1624 } 1625 1626 void xe_lrc_dump_default(struct drm_printer *p, 1627 struct xe_gt *gt, 1628 enum xe_engine_class hwe_class) 1629 { 1630 u32 *dw; 1631 int remaining_dw, num_dw; 1632 1633 if (!gt->default_lrc[hwe_class]) { 1634 drm_printf(p, "No default LRC for class %d\n", hwe_class); 1635 return; 1636 } 1637 1638 /* 1639 * Skip the beginning of the LRC since it contains the per-process 1640 * hardware status page. 1641 */ 1642 dw = gt->default_lrc[hwe_class] + LRC_PPHWSP_SIZE; 1643 remaining_dw = (xe_gt_lrc_size(gt, hwe_class) - LRC_PPHWSP_SIZE) / 4; 1644 1645 while (remaining_dw > 0) { 1646 if ((*dw & XE_INSTR_CMD_TYPE) == XE_INSTR_MI) { 1647 num_dw = dump_mi_command(p, gt, dw, remaining_dw); 1648 } else if ((*dw & XE_INSTR_CMD_TYPE) == XE_INSTR_GFXPIPE) { 1649 num_dw = dump_gfxpipe_command(p, gt, dw, remaining_dw); 1650 } else if ((*dw & XE_INSTR_CMD_TYPE) == XE_INSTR_GFX_STATE) { 1651 num_dw = dump_gfx_state_command(p, gt, dw, remaining_dw); 1652 } else { 1653 num_dw = min(instr_dw(*dw), remaining_dw); 1654 drm_printf(p, "[%#10x] Unknown instruction of type %#x, likely %d dwords\n", 1655 *dw, REG_FIELD_GET(XE_INSTR_CMD_TYPE, *dw), 1656 num_dw); 1657 } 1658 1659 dw += num_dw; 1660 remaining_dw -= num_dw; 1661 } 1662 } 1663 1664 struct instr_state { 1665 u32 instr; 1666 u16 num_dw; 1667 }; 1668 1669 static const struct instr_state xe_hpg_svg_state[] = { 1670 { .instr = CMD_3DSTATE_CONSTANT_VS, .num_dw = 11 }, 1671 { .instr = CMD_3DSTATE_CONSTANT_HS, .num_dw = 11 }, 1672 { .instr = CMD_3DSTATE_CONSTANT_DS, .num_dw = 11 }, 1673 { .instr = CMD_3DSTATE_CONSTANT_GS, .num_dw = 11 }, 1674 { .instr = CMD_3DSTATE_VERTEX_ELEMENTS, .num_dw = 69 }, 1675 { .instr = CMD_3DSTATE_VF_COMPONENT_PACKING, .num_dw = 5 }, 1676 { .instr = CMD_3DSTATE_VF_SGVS, .num_dw = 2 }, 1677 { .instr = CMD_3DSTATE_VF_SGVS_2, .num_dw = 3 }, 1678 { .instr = CMD_3DSTATE_VS, .num_dw = 9 }, 1679 { .instr = CMD_3DSTATE_BINDING_TABLE_POINTERS_VS, .num_dw = 2 }, 1680 { .instr = CMD_3DSTATE_SAMPLER_STATE_POINTERS_VS, .num_dw = 2 }, 1681 { .instr = CMD_3DSTATE_URB_ALLOC_VS, .num_dw = 3 }, 1682 { .instr = CMD_3DSTATE_STREAMOUT, .num_dw = 5 }, 1683 { .instr = CMD_3DSTATE_SO_BUFFER_INDEX_0, .num_dw = 8 }, 1684 { .instr = CMD_3DSTATE_SO_BUFFER_INDEX_1, .num_dw = 8 }, 1685 { .instr = CMD_3DSTATE_SO_BUFFER_INDEX_2, .num_dw = 8 }, 1686 { .instr = CMD_3DSTATE_SO_BUFFER_INDEX_3, .num_dw = 8 }, 1687 { .instr = CMD_3DSTATE_CLIP, .num_dw = 4 }, 1688 { .instr = CMD_3DSTATE_PRIMITIVE_REPLICATION, .num_dw = 6 }, 1689 { .instr = CMD_3DSTATE_CLIP_MESH, .num_dw = 2 }, 1690 { .instr = CMD_3DSTATE_SF, .num_dw = 4 }, 1691 { .instr = CMD_3DSTATE_SCISSOR_STATE_POINTERS, .num_dw = 2 }, 1692 { .instr = CMD_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP, .num_dw = 2 }, 1693 { .instr = CMD_3DSTATE_RASTER, .num_dw = 5 }, 1694 { .instr = CMD_3DSTATE_TBIMR_TILE_PASS_INFO, .num_dw = 4 }, 1695 { .instr = CMD_3DSTATE_WM_HZ_OP, .num_dw = 6 }, 1696 { .instr = CMD_3DSTATE_MULTISAMPLE, .num_dw = 2 }, 1697 { .instr = CMD_3DSTATE_HS, .num_dw = 9 }, 1698 { .instr = CMD_3DSTATE_BINDING_TABLE_POINTERS_HS, .num_dw = 2 }, 1699 { .instr = CMD_3DSTATE_SAMPLER_STATE_POINTERS_HS, .num_dw = 2 }, 1700 { .instr = CMD_3DSTATE_URB_ALLOC_HS, .num_dw = 3 }, 1701 { .instr = CMD_3DSTATE_TASK_CONTROL, .num_dw = 3 }, 1702 { .instr = CMD_3DSTATE_TASK_SHADER, .num_dw = 7 }, 1703 { .instr = CMD_3DSTATE_TASK_SHADER_DATA, .num_dw = 10 }, 1704 { .instr = CMD_3DSTATE_URB_ALLOC_TASK, .num_dw = 3 }, 1705 { .instr = CMD_3DSTATE_TE, .num_dw = 5 }, 1706 { .instr = CMD_3DSTATE_TASK_REDISTRIB, .num_dw = 2 }, 1707 { .instr = CMD_3DSTATE_DS, .num_dw = 11 }, 1708 { .instr = CMD_3DSTATE_BINDING_TABLE_POINTERS_DS, .num_dw = 2 }, 1709 { .instr = CMD_3DSTATE_SAMPLER_STATE_POINTERS_DS, .num_dw = 2 }, 1710 { .instr = CMD_3DSTATE_URB_ALLOC_DS, .num_dw = 3 }, 1711 { .instr = CMD_3DSTATE_GS, .num_dw = 10 }, 1712 { .instr = CMD_3DSTATE_BINDING_TABLE_POINTERS_GS, .num_dw = 2 }, 1713 { .instr = CMD_3DSTATE_SAMPLER_STATE_POINTERS_GS, .num_dw = 2 }, 1714 { .instr = CMD_3DSTATE_URB_ALLOC_GS, .num_dw = 3 }, 1715 { .instr = CMD_3DSTATE_MESH_CONTROL, .num_dw = 3 }, 1716 { .instr = CMD_3DSTATE_MESH_SHADER_DATA, .num_dw = 10 }, 1717 { .instr = CMD_3DSTATE_URB_ALLOC_MESH, .num_dw = 3 }, 1718 { .instr = CMD_3DSTATE_MESH_SHADER, .num_dw = 8 }, 1719 { .instr = CMD_3DSTATE_DRAWING_RECTANGLE, .num_dw = 4 }, 1720 }; 1721 1722 void xe_lrc_emit_hwe_state_instructions(struct xe_exec_queue *q, struct xe_bb *bb) 1723 { 1724 struct xe_gt *gt = q->hwe->gt; 1725 struct xe_device *xe = gt_to_xe(gt); 1726 const struct instr_state *state_table = NULL; 1727 int state_table_size = 0; 1728 1729 /* 1730 * Wa_14019789679 1731 * 1732 * If the driver doesn't explicitly emit the SVG instructions while 1733 * setting up the default LRC, the context switch will write 0's 1734 * (noops) into the LRC memory rather than the expected instruction 1735 * headers. Application contexts start out as a copy of the default 1736 * LRC, and if they also do not emit specific settings for some SVG 1737 * state, then on context restore they'll unintentionally inherit 1738 * whatever state setting the previous context had programmed into the 1739 * hardware (i.e., the lack of a 3DSTATE_* instruction in the LRC will 1740 * prevent the hardware from resetting that state back to any specific 1741 * value). 1742 * 1743 * The official workaround only requires emitting 3DSTATE_MESH_CONTROL 1744 * since that's a specific state setting that can easily cause GPU 1745 * hangs if unintentionally inherited. However to be safe we'll 1746 * continue to emit all of the SVG state since it's best not to leak 1747 * any of the state between contexts, even if that leakage is harmless. 1748 */ 1749 if (XE_WA(gt, 14019789679) && q->hwe->class == XE_ENGINE_CLASS_RENDER) { 1750 state_table = xe_hpg_svg_state; 1751 state_table_size = ARRAY_SIZE(xe_hpg_svg_state); 1752 } 1753 1754 if (!state_table) { 1755 xe_gt_dbg(gt, "No non-register state to emit on graphics ver %d.%02d\n", 1756 GRAPHICS_VER(xe), GRAPHICS_VERx100(xe) % 100); 1757 return; 1758 } 1759 1760 for (int i = 0; i < state_table_size; i++) { 1761 u32 instr = state_table[i].instr; 1762 u16 num_dw = state_table[i].num_dw; 1763 bool is_single_dw = ((instr & GFXPIPE_PIPELINE) == PIPELINE_SINGLE_DW); 1764 1765 xe_gt_assert(gt, (instr & XE_INSTR_CMD_TYPE) == XE_INSTR_GFXPIPE); 1766 xe_gt_assert(gt, num_dw != 0); 1767 xe_gt_assert(gt, is_single_dw ^ (num_dw > 1)); 1768 1769 /* 1770 * Xe2's SVG context is the same as the one on DG2 / MTL 1771 * except that 3DSTATE_DRAWING_RECTANGLE (non-pipelined) has 1772 * been replaced by 3DSTATE_DRAWING_RECTANGLE_FAST (pipelined). 1773 * Just make the replacement here rather than defining a 1774 * whole separate table for the single trivial change. 1775 */ 1776 if (GRAPHICS_VER(xe) >= 20 && 1777 instr == CMD_3DSTATE_DRAWING_RECTANGLE) 1778 instr = CMD_3DSTATE_DRAWING_RECTANGLE_FAST; 1779 1780 bb->cs[bb->len] = instr; 1781 if (!is_single_dw) 1782 bb->cs[bb->len] |= (num_dw - 2); 1783 1784 bb->len += num_dw; 1785 } 1786 } 1787 1788 struct xe_lrc_snapshot *xe_lrc_snapshot_capture(struct xe_lrc *lrc) 1789 { 1790 struct xe_lrc_snapshot *snapshot = kmalloc(sizeof(*snapshot), GFP_NOWAIT); 1791 1792 if (!snapshot) 1793 return NULL; 1794 1795 snapshot->context_desc = xe_lrc_ggtt_addr(lrc); 1796 snapshot->ring_addr = __xe_lrc_ring_ggtt_addr(lrc); 1797 snapshot->indirect_context_desc = xe_lrc_indirect_ring_ggtt_addr(lrc); 1798 snapshot->head = xe_lrc_ring_head(lrc); 1799 snapshot->tail.internal = lrc->ring.tail; 1800 snapshot->tail.memory = xe_lrc_ring_tail(lrc); 1801 snapshot->start = xe_lrc_ring_start(lrc); 1802 snapshot->start_seqno = xe_lrc_start_seqno(lrc); 1803 snapshot->seqno = xe_lrc_seqno(lrc); 1804 snapshot->lrc_bo = xe_bo_get(lrc->bo); 1805 snapshot->lrc_offset = xe_lrc_pphwsp_offset(lrc); 1806 snapshot->lrc_size = lrc->bo->size - snapshot->lrc_offset; 1807 snapshot->lrc_snapshot = NULL; 1808 snapshot->ctx_timestamp = lower_32_bits(xe_lrc_ctx_timestamp(lrc)); 1809 snapshot->ctx_job_timestamp = xe_lrc_ctx_job_timestamp(lrc); 1810 return snapshot; 1811 } 1812 1813 void xe_lrc_snapshot_capture_delayed(struct xe_lrc_snapshot *snapshot) 1814 { 1815 struct xe_bo *bo; 1816 struct iosys_map src; 1817 1818 if (!snapshot) 1819 return; 1820 1821 bo = snapshot->lrc_bo; 1822 snapshot->lrc_bo = NULL; 1823 1824 snapshot->lrc_snapshot = kvmalloc(snapshot->lrc_size, GFP_KERNEL); 1825 if (!snapshot->lrc_snapshot) 1826 goto put_bo; 1827 1828 xe_bo_lock(bo, false); 1829 if (!ttm_bo_vmap(&bo->ttm, &src)) { 1830 xe_map_memcpy_from(xe_bo_device(bo), 1831 snapshot->lrc_snapshot, &src, snapshot->lrc_offset, 1832 snapshot->lrc_size); 1833 ttm_bo_vunmap(&bo->ttm, &src); 1834 } else { 1835 kvfree(snapshot->lrc_snapshot); 1836 snapshot->lrc_snapshot = NULL; 1837 } 1838 xe_bo_unlock(bo); 1839 put_bo: 1840 xe_bo_put(bo); 1841 } 1842 1843 void xe_lrc_snapshot_print(struct xe_lrc_snapshot *snapshot, struct drm_printer *p) 1844 { 1845 unsigned long i; 1846 1847 if (!snapshot) 1848 return; 1849 1850 drm_printf(p, "\tHW Context Desc: 0x%08x\n", snapshot->context_desc); 1851 drm_printf(p, "\tHW Ring address: 0x%08x\n", 1852 snapshot->ring_addr); 1853 drm_printf(p, "\tHW Indirect Ring State: 0x%08x\n", 1854 snapshot->indirect_context_desc); 1855 drm_printf(p, "\tLRC Head: (memory) %u\n", snapshot->head); 1856 drm_printf(p, "\tLRC Tail: (internal) %u, (memory) %u\n", 1857 snapshot->tail.internal, snapshot->tail.memory); 1858 drm_printf(p, "\tRing start: (memory) 0x%08x\n", snapshot->start); 1859 drm_printf(p, "\tStart seqno: (memory) %d\n", snapshot->start_seqno); 1860 drm_printf(p, "\tSeqno: (memory) %d\n", snapshot->seqno); 1861 drm_printf(p, "\tTimestamp: 0x%08x\n", snapshot->ctx_timestamp); 1862 drm_printf(p, "\tJob Timestamp: 0x%08x\n", snapshot->ctx_job_timestamp); 1863 1864 if (!snapshot->lrc_snapshot) 1865 return; 1866 1867 drm_printf(p, "\t[HWSP].length: 0x%x\n", LRC_PPHWSP_SIZE); 1868 drm_puts(p, "\t[HWSP].data: "); 1869 for (i = 0; i < LRC_PPHWSP_SIZE; i += sizeof(u32)) { 1870 u32 *val = snapshot->lrc_snapshot + i; 1871 char dumped[ASCII85_BUFSZ]; 1872 1873 drm_puts(p, ascii85_encode(*val, dumped)); 1874 } 1875 1876 drm_printf(p, "\n\t[HWCTX].length: 0x%lx\n", snapshot->lrc_size - LRC_PPHWSP_SIZE); 1877 drm_puts(p, "\t[HWCTX].data: "); 1878 for (; i < snapshot->lrc_size; i += sizeof(u32)) { 1879 u32 *val = snapshot->lrc_snapshot + i; 1880 char dumped[ASCII85_BUFSZ]; 1881 1882 drm_puts(p, ascii85_encode(*val, dumped)); 1883 } 1884 drm_puts(p, "\n"); 1885 } 1886 1887 void xe_lrc_snapshot_free(struct xe_lrc_snapshot *snapshot) 1888 { 1889 if (!snapshot) 1890 return; 1891 1892 kvfree(snapshot->lrc_snapshot); 1893 if (snapshot->lrc_bo) 1894 xe_bo_put(snapshot->lrc_bo); 1895 1896 kfree(snapshot); 1897 } 1898 1899 static int get_ctx_timestamp(struct xe_lrc *lrc, u32 engine_id, u64 *reg_ctx_ts) 1900 { 1901 u16 class = REG_FIELD_GET(ENGINE_CLASS_ID, engine_id); 1902 u16 instance = REG_FIELD_GET(ENGINE_INSTANCE_ID, engine_id); 1903 struct xe_hw_engine *hwe; 1904 u64 val; 1905 1906 hwe = xe_gt_hw_engine(lrc->gt, class, instance, false); 1907 if (xe_gt_WARN_ONCE(lrc->gt, !hwe || xe_hw_engine_is_reserved(hwe), 1908 "Unexpected engine class:instance %d:%d for context utilization\n", 1909 class, instance)) 1910 return -1; 1911 1912 if (lrc_to_xe(lrc)->info.has_64bit_timestamp) 1913 val = xe_mmio_read64_2x32(&hwe->gt->mmio, 1914 RING_CTX_TIMESTAMP(hwe->mmio_base)); 1915 else 1916 val = xe_mmio_read32(&hwe->gt->mmio, 1917 RING_CTX_TIMESTAMP(hwe->mmio_base)); 1918 1919 *reg_ctx_ts = val; 1920 1921 return 0; 1922 } 1923 1924 /** 1925 * xe_lrc_update_timestamp() - Update ctx timestamp 1926 * @lrc: Pointer to the lrc. 1927 * @old_ts: Old timestamp value 1928 * 1929 * Populate @old_ts current saved ctx timestamp, read new ctx timestamp and 1930 * update saved value. With support for active contexts, the calculation may be 1931 * slightly racy, so follow a read-again logic to ensure that the context is 1932 * still active before returning the right timestamp. 1933 * 1934 * Returns: New ctx timestamp value 1935 */ 1936 u64 xe_lrc_update_timestamp(struct xe_lrc *lrc, u64 *old_ts) 1937 { 1938 u64 lrc_ts, reg_ts; 1939 u32 engine_id; 1940 1941 *old_ts = lrc->ctx_timestamp; 1942 1943 lrc_ts = xe_lrc_ctx_timestamp(lrc); 1944 /* CTX_TIMESTAMP mmio read is invalid on VF, so return the LRC value */ 1945 if (IS_SRIOV_VF(lrc_to_xe(lrc))) { 1946 lrc->ctx_timestamp = lrc_ts; 1947 goto done; 1948 } 1949 1950 if (lrc_ts == CONTEXT_ACTIVE) { 1951 engine_id = xe_lrc_engine_id(lrc); 1952 if (!get_ctx_timestamp(lrc, engine_id, ®_ts)) 1953 lrc->ctx_timestamp = reg_ts; 1954 1955 /* read lrc again to ensure context is still active */ 1956 lrc_ts = xe_lrc_ctx_timestamp(lrc); 1957 } 1958 1959 /* 1960 * If context switched out, just use the lrc_ts. Note that this needs to 1961 * be a separate if condition. 1962 */ 1963 if (lrc_ts != CONTEXT_ACTIVE) 1964 lrc->ctx_timestamp = lrc_ts; 1965 1966 done: 1967 trace_xe_lrc_update_timestamp(lrc, *old_ts); 1968 1969 return lrc->ctx_timestamp; 1970 } 1971 1972 /** 1973 * xe_lrc_ring_is_idle() - LRC is idle 1974 * @lrc: Pointer to the lrc. 1975 * 1976 * Compare LRC ring head and tail to determine if idle. 1977 * 1978 * Return: True is ring is idle, False otherwise 1979 */ 1980 bool xe_lrc_ring_is_idle(struct xe_lrc *lrc) 1981 { 1982 return xe_lrc_ring_head(lrc) == xe_lrc_ring_tail(lrc); 1983 } 1984