1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Intel Xe I2C attached Microcontroller Units (MCU) 4 * 5 * Copyright (C) 2025 Intel Corporation. 6 */ 7 8 #include <drm/drm_print.h> 9 #include <linux/array_size.h> 10 #include <linux/container_of.h> 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/err.h> 14 #include <linux/i2c.h> 15 #include <linux/ioport.h> 16 #include <linux/notifier.h> 17 #include <linux/pci.h> 18 #include <linux/platform_device.h> 19 #include <linux/property.h> 20 #include <linux/regmap.h> 21 #include <linux/sprintf.h> 22 #include <linux/string.h> 23 #include <linux/types.h> 24 #include <linux/workqueue.h> 25 26 #include <linux/designware_i2c.h> 27 28 #include "regs/xe_i2c_regs.h" 29 #include "regs/xe_irq_regs.h" 30 31 #include "xe_amc.h" 32 #include "xe_device.h" 33 #include "xe_i2c.h" 34 #include "xe_mmio.h" 35 #include "xe_sriov.h" 36 #include "xe_survivability_mode.h" 37 38 /** 39 * DOC: Xe I2C devices 40 * 41 * Register a platform device for the I2C host controller (Synpsys DesignWare 42 * I2C) if the registers of that controller are mapped to the MMIO, and also the 43 * I2C client device for the Add-In Management Controller (the MCU) attached to 44 * the host controller. 45 * 46 * See drivers/i2c/busses/i2c-designware-* for more information on the I2C host 47 * controller. 48 */ 49 50 static const char adapter_name[] = "i2c_designware"; 51 52 static const struct property_entry xe_i2c_adapter_properties[] = { 53 PROPERTY_ENTRY_STRING("compatible", "intel,xe-i2c"), 54 PROPERTY_ENTRY_U32("clock-frequency", I2C_MAX_FAST_MODE_PLUS_FREQ), 55 { } 56 }; 57 58 static inline void xe_i2c_read_endpoint(struct xe_mmio *mmio, void *ep) 59 { 60 u32 *val = ep; 61 62 val[0] = xe_mmio_read32(mmio, REG_SG_REMAP_ADDR_PREFIX); 63 val[1] = xe_mmio_read32(mmio, REG_SG_REMAP_ADDR_POSTFIX); 64 } 65 66 static void xe_i2c_handle_smbus_alert(struct xe_i2c *i2c) 67 { 68 u32 stat; 69 70 stat = xe_mmio_read32(i2c->mmio, I2C_REG(DW_IC_SMBUS_INTR_STAT)); 71 if (!stat) 72 return; 73 74 xe_mmio_write32(i2c->mmio, I2C_REG(DW_IC_CLR_SMBUS_INTR), stat); 75 76 if (stat & DW_IC_SMBUS_INTR_ALERT && i2c->amc) 77 xe_amc_handle_alert(i2c); 78 else 79 xe_mmio_rmw32(i2c->mmio, I2C_CONFIG_CMD, PCI_COMMAND_INTX_DISABLE, 0); 80 } 81 82 static void xe_i2c_client_work(struct work_struct *work) 83 { 84 struct xe_i2c *i2c = container_of(work, struct xe_i2c, work); 85 struct i2c_board_info info = { 86 .type = "amc", 87 .flags = I2C_CLIENT_HOST_NOTIFY, 88 .addr = i2c->ep.addr[XE_I2C_CLIENT_AMC], 89 }; 90 91 i2c->client[XE_I2C_CLIENT_AMC] = i2c_new_client_device(i2c->adapter, &info); 92 } 93 94 static int xe_i2c_notifier(struct notifier_block *nb, unsigned long action, void *data) 95 { 96 struct xe_i2c *i2c = container_of(nb, struct xe_i2c, bus_notifier); 97 struct i2c_adapter *adapter = i2c_verify_adapter(data); 98 struct device *dev = data; 99 100 if (action == BUS_NOTIFY_ADD_DEVICE && 101 adapter && dev->parent == &i2c->pdev->dev) { 102 i2c->adapter = adapter; 103 schedule_work(&i2c->work); 104 return NOTIFY_OK; 105 } 106 107 return NOTIFY_DONE; 108 } 109 110 static int xe_i2c_register_adapter(struct xe_i2c *i2c) 111 { 112 struct pci_dev *pci = to_pci_dev(i2c->drm_dev); 113 struct platform_device *pdev; 114 int ret; 115 u32 id; 116 117 id = (pci_domain_nr(pci->bus) << 16) | pci_dev_id(pci); 118 119 /* 120 * Not using platform_device_register_full() here because we don't have 121 * a handle to the platform_device before it returns. xe_i2c_notifier() 122 * uses that handle, but it may be called before 123 * platform_device_register_full() is done. 124 */ 125 pdev = platform_device_alloc(adapter_name, id); 126 if (!pdev) 127 return -ENOMEM; 128 129 ret = device_create_managed_software_node(&pdev->dev, 130 xe_i2c_adapter_properties, 131 NULL); 132 if (ret) 133 goto err_pdev_put; 134 135 pdev->dev.parent = i2c->drm_dev; 136 i2c->pdev = pdev; 137 138 ret = platform_device_add(pdev); 139 if (ret) 140 goto err_pdev_put; 141 142 return 0; 143 144 err_pdev_put: 145 platform_device_put(pdev); 146 147 return ret; 148 } 149 150 static void xe_i2c_unregister_adapter(struct xe_i2c *i2c) 151 { 152 platform_device_unregister(i2c->pdev); 153 } 154 155 /** 156 * xe_i2c_present - I2C controller is present and functional 157 * @xe: xe device instance 158 * 159 * Check whether the I2C controller is present and functioning with valid 160 * endpoint cookie. 161 * 162 * Return: %true if present, %false otherwise. 163 */ 164 bool xe_i2c_present(struct xe_device *xe) 165 { 166 return xe->i2c && xe->i2c->ep.cookie == XE_I2C_EP_COOKIE_DEVICE; 167 } 168 169 static bool xe_i2c_irq_present(struct xe_device *xe) 170 { 171 return xe->i2c && xe->i2c->ep.capabilities & XE_I2C_EP_CAP_IRQ && 172 !xe_survivability_mode_is_boot_enabled(xe); 173 } 174 175 /** 176 * xe_i2c_irq_handler: Handler for I2C interrupts 177 * @xe: xe device instance 178 * @master_ctl: interrupt register 179 * 180 * Forward interrupts generated by the I2C host adapter to the I2C host adapter 181 * driver. 182 */ 183 void xe_i2c_irq_handler(struct xe_device *xe, u32 master_ctl) 184 { 185 if (!(master_ctl & I2C_IRQ) || !xe_i2c_irq_present(xe)) 186 return; 187 188 xe_i2c_handle_smbus_alert(xe->i2c); 189 } 190 191 void xe_i2c_irq_reset(struct xe_device *xe) 192 { 193 struct xe_mmio *mmio = xe_root_tile_mmio(xe); 194 195 if (!xe_i2c_irq_present(xe)) 196 return; 197 198 xe_mmio_rmw32(mmio, I2C_CONFIG_CMD, 0, PCI_COMMAND_INTX_DISABLE); 199 xe_mmio_rmw32(mmio, I2C_BRIDGE_PCICFGCTL, ACPI_INTR_EN, 0); 200 } 201 202 void xe_i2c_irq_postinstall(struct xe_device *xe) 203 { 204 struct xe_mmio *mmio = xe_root_tile_mmio(xe); 205 206 if (!xe_i2c_irq_present(xe)) 207 return; 208 209 xe_mmio_rmw32(mmio, I2C_BRIDGE_PCICFGCTL, 0, ACPI_INTR_EN); 210 xe_mmio_rmw32(mmio, I2C_CONFIG_CMD, PCI_COMMAND_INTX_DISABLE, 0); 211 } 212 213 /* See "Disabling DW_apb_i2c" in the DesignWare DW_abp_i2c databook. */ 214 static void xe_i2c_disable(struct xe_i2c *i2c) 215 { 216 int timeout = 100; 217 u32 status; 218 219 xe_mmio_rmw32(i2c->mmio, I2C_REG(DW_IC_ENABLE), DW_IC_ENABLE_ENABLE, 0); 220 221 do { 222 status = xe_mmio_read32(i2c->mmio, I2C_REG(DW_IC_ENABLE_STATUS)); 223 if (!(status & DW_IC_ENABLE_ENABLE)) 224 return; 225 /* Can't sleep here. */ 226 udelay(25); 227 } while (timeout--); 228 229 dev_warn(i2c->drm_dev, "timeout in disabling i2c adapter\n"); 230 } 231 232 static int xe_i2c_read(void *context, unsigned int reg, unsigned int *val) 233 { 234 struct xe_i2c *i2c = context; 235 236 *val = xe_mmio_read32(i2c->mmio, I2C_REG(reg)); 237 238 switch (reg) { 239 case DW_IC_ENABLE: 240 case DW_IC_ENABLE_STATUS: 241 FIELD_MODIFY(DW_IC_ENABLE_ENABLE, val, 242 i2c->ic_enable & DW_IC_ENABLE_ENABLE); 243 break; 244 default: 245 break; 246 } 247 248 return 0; 249 } 250 251 static int xe_i2c_write(void *context, unsigned int reg, unsigned int val) 252 { 253 struct xe_i2c *i2c = context; 254 255 switch (reg) { 256 case DW_IC_CON: 257 case DW_IC_TAR: 258 case DW_IC_SAR: 259 /* Disable the controller. */ 260 xe_i2c_disable(i2c); 261 262 /* Write the register. */ 263 xe_mmio_write32(i2c->mmio, I2C_REG(reg), val); 264 265 /* Enable the controller. */ 266 xe_mmio_rmw32(i2c->mmio, I2C_REG(DW_IC_ENABLE), 0, DW_IC_ENABLE_ENABLE); 267 return 0; 268 case DW_IC_ENABLE: 269 i2c->ic_enable = val; 270 /* Other fields can be updated except the enable bit. */ 271 val |= DW_IC_ENABLE_ENABLE; 272 break; 273 case DW_IC_SMBUS_INTR_MASK: 274 /* Make sure the Alert is never masked. */ 275 val |= DW_IC_SMBUS_INTR_ALERT; 276 break; 277 default: 278 break; 279 } 280 281 xe_mmio_write32(i2c->mmio, I2C_REG(reg), val); 282 return 0; 283 } 284 285 static const struct regmap_config i2c_regmap_config = { 286 .reg_bits = 32, 287 .val_bits = 32, 288 .reg_read = xe_i2c_read, 289 .reg_write = xe_i2c_write, 290 .fast_io = true, 291 }; 292 293 void xe_i2c_pm_suspend(struct xe_device *xe) 294 { 295 struct xe_mmio *mmio = xe_root_tile_mmio(xe); 296 297 if (!xe_i2c_present(xe)) 298 return; 299 300 xe_mmio_rmw32(mmio, I2C_CONFIG_PMCSR, PCI_PM_CTRL_STATE_MASK, (__force u32)PCI_D3hot); 301 drm_dbg(&xe->drm, "pmcsr: 0x%08x\n", xe_mmio_read32(mmio, I2C_CONFIG_PMCSR)); 302 } 303 304 void xe_i2c_pm_resume(struct xe_device *xe, bool d3cold) 305 { 306 struct xe_mmio *mmio = xe_root_tile_mmio(xe); 307 308 if (!xe_i2c_present(xe)) 309 return; 310 311 if (d3cold) 312 xe_mmio_rmw32(mmio, I2C_CONFIG_CMD, 0, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 313 314 xe_mmio_rmw32(mmio, I2C_CONFIG_PMCSR, PCI_PM_CTRL_STATE_MASK, (__force u32)PCI_D0); 315 drm_dbg(&xe->drm, "pmcsr: 0x%08x\n", xe_mmio_read32(mmio, I2C_CONFIG_PMCSR)); 316 } 317 318 static void xe_i2c_remove(void *data) 319 { 320 struct xe_i2c *i2c = data; 321 unsigned int i; 322 323 xe_amc_exit(i2c); 324 325 for (i = 0; i < XE_I2C_MAX_CLIENTS; i++) { 326 i2c_unregister_device(i2c->client[i]); 327 i2c->client[i] = NULL; 328 } 329 330 bus_unregister_notifier(&i2c_bus_type, &i2c->bus_notifier); 331 xe_i2c_unregister_adapter(i2c); 332 } 333 334 /** 335 * xe_i2c_probe: Probe the I2C host adapter and the I2C clients attached to it 336 * @xe: xe device instance 337 * 338 * Register all the I2C devices described in the I2C Endpoint data structure. 339 * 340 * Return: 0 on success, error code on failure 341 */ 342 int xe_i2c_probe(struct xe_device *xe) 343 { 344 struct device *drm_dev = xe->drm.dev; 345 struct xe_i2c_endpoint ep; 346 struct regmap *regmap; 347 struct xe_i2c *i2c; 348 int ret; 349 350 if (!xe->info.has_i2c) 351 return 0; 352 353 xe_i2c_read_endpoint(xe_root_tile_mmio(xe), &ep); 354 if (ep.cookie != XE_I2C_EP_COOKIE_DEVICE) 355 return 0; 356 357 i2c = devm_kzalloc(drm_dev, sizeof(*i2c), GFP_KERNEL); 358 if (!i2c) 359 return -ENOMEM; 360 361 INIT_WORK(&i2c->work, xe_i2c_client_work); 362 i2c->mmio = xe_root_tile_mmio(xe); 363 i2c->drm_dev = drm_dev; 364 i2c->ep = ep; 365 xe->i2c = i2c; 366 367 /* PCI PM isn't aware of this device, bring it up and match it with SGUnit state. */ 368 xe_i2c_pm_resume(xe, true); 369 370 regmap = devm_regmap_init(drm_dev, NULL, i2c, &i2c_regmap_config); 371 if (IS_ERR(regmap)) 372 return PTR_ERR(regmap); 373 374 i2c->bus_notifier.notifier_call = xe_i2c_notifier; 375 ret = bus_register_notifier(&i2c_bus_type, &i2c->bus_notifier); 376 if (ret) 377 return ret; 378 379 ret = xe_i2c_register_adapter(i2c); 380 if (ret) { 381 bus_unregister_notifier(&i2c_bus_type, &i2c->bus_notifier); 382 return ret; 383 } 384 385 ret = xe_amc_init(i2c); 386 if (ret) { 387 xe_i2c_remove(i2c); 388 return ret; 389 } 390 391 xe_i2c_irq_postinstall(xe); 392 return devm_add_action_or_reset(drm_dev, xe_i2c_remove, i2c); 393 } 394