1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #include <linux/hwmon-sysfs.h> 7 #include <linux/hwmon.h> 8 #include <linux/types.h> 9 10 #include <drm/drm_managed.h> 11 #include "regs/xe_gt_regs.h" 12 #include "regs/xe_mchbar_regs.h" 13 #include "regs/xe_pcode_regs.h" 14 #include "xe_device.h" 15 #include "xe_gt.h" 16 #include "xe_hwmon.h" 17 #include "xe_mmio.h" 18 #include "xe_pcode.h" 19 #include "xe_pcode_api.h" 20 #include "xe_sriov.h" 21 #include "xe_pm.h" 22 23 enum xe_hwmon_reg { 24 REG_PKG_RAPL_LIMIT, 25 REG_PKG_POWER_SKU, 26 REG_PKG_POWER_SKU_UNIT, 27 REG_GT_PERF_STATUS, 28 REG_PKG_ENERGY_STATUS, 29 }; 30 31 enum xe_hwmon_reg_operation { 32 REG_READ32, 33 REG_RMW32, 34 REG_READ64, 35 }; 36 37 enum xe_hwmon_channel { 38 CHANNEL_CARD, 39 CHANNEL_PKG, 40 CHANNEL_MAX, 41 }; 42 43 /* 44 * SF_* - scale factors for particular quantities according to hwmon spec. 45 */ 46 #define SF_POWER 1000000 /* microwatts */ 47 #define SF_CURR 1000 /* milliamperes */ 48 #define SF_VOLTAGE 1000 /* millivolts */ 49 #define SF_ENERGY 1000000 /* microjoules */ 50 #define SF_TIME 1000 /* milliseconds */ 51 52 /** 53 * struct xe_hwmon_energy_info - to accumulate energy 54 */ 55 struct xe_hwmon_energy_info { 56 /** @reg_val_prev: previous energy reg val */ 57 u32 reg_val_prev; 58 /** @accum_energy: accumulated energy */ 59 long accum_energy; 60 }; 61 62 /** 63 * struct xe_hwmon - xe hwmon data structure 64 */ 65 struct xe_hwmon { 66 /** @hwmon_dev: hwmon device for xe */ 67 struct device *hwmon_dev; 68 /** @gt: primary gt */ 69 struct xe_gt *gt; 70 /** @hwmon_lock: lock for rw attributes*/ 71 struct mutex hwmon_lock; 72 /** @scl_shift_power: pkg power unit */ 73 int scl_shift_power; 74 /** @scl_shift_energy: pkg energy unit */ 75 int scl_shift_energy; 76 /** @scl_shift_time: pkg time unit */ 77 int scl_shift_time; 78 /** @ei: Energy info for energyN_input */ 79 struct xe_hwmon_energy_info ei[CHANNEL_MAX]; 80 }; 81 82 static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg, 83 int channel) 84 { 85 struct xe_device *xe = gt_to_xe(hwmon->gt); 86 87 switch (hwmon_reg) { 88 case REG_PKG_RAPL_LIMIT: 89 if (xe->info.platform == XE_BATTLEMAGE) { 90 if (channel == CHANNEL_PKG) 91 return BMG_PACKAGE_RAPL_LIMIT; 92 else 93 return BMG_PLATFORM_POWER_LIMIT; 94 } else if (xe->info.platform == XE_PVC && channel == CHANNEL_PKG) { 95 return PVC_GT0_PACKAGE_RAPL_LIMIT; 96 } else if ((xe->info.platform == XE_DG2) && (channel == CHANNEL_PKG)) { 97 return PCU_CR_PACKAGE_RAPL_LIMIT; 98 } 99 break; 100 case REG_PKG_POWER_SKU: 101 if (xe->info.platform == XE_BATTLEMAGE) 102 return BMG_PACKAGE_POWER_SKU; 103 else if (xe->info.platform == XE_PVC && channel == CHANNEL_PKG) 104 return PVC_GT0_PACKAGE_POWER_SKU; 105 else if ((xe->info.platform == XE_DG2) && (channel == CHANNEL_PKG)) 106 return PCU_CR_PACKAGE_POWER_SKU; 107 break; 108 case REG_PKG_POWER_SKU_UNIT: 109 if (xe->info.platform == XE_BATTLEMAGE) 110 return BMG_PACKAGE_POWER_SKU_UNIT; 111 else if (xe->info.platform == XE_PVC) 112 return PVC_GT0_PACKAGE_POWER_SKU_UNIT; 113 else if (xe->info.platform == XE_DG2) 114 return PCU_CR_PACKAGE_POWER_SKU_UNIT; 115 break; 116 case REG_GT_PERF_STATUS: 117 if (xe->info.platform == XE_DG2 && channel == CHANNEL_PKG) 118 return GT_PERF_STATUS; 119 break; 120 case REG_PKG_ENERGY_STATUS: 121 if (xe->info.platform == XE_BATTLEMAGE) { 122 if (channel == CHANNEL_PKG) 123 return BMG_PACKAGE_ENERGY_STATUS; 124 else 125 return BMG_PLATFORM_ENERGY_STATUS; 126 } else if (xe->info.platform == XE_PVC && channel == CHANNEL_PKG) { 127 return PVC_GT0_PLATFORM_ENERGY_STATUS; 128 } else if ((xe->info.platform == XE_DG2) && (channel == CHANNEL_PKG)) { 129 return PCU_CR_PACKAGE_ENERGY_STATUS; 130 } 131 break; 132 default: 133 drm_warn(&xe->drm, "Unknown xe hwmon reg id: %d\n", hwmon_reg); 134 break; 135 } 136 137 return XE_REG(0); 138 } 139 140 static void xe_hwmon_process_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg, 141 enum xe_hwmon_reg_operation operation, u64 *value, 142 u32 clr, u32 set, int channel) 143 { 144 struct xe_reg reg; 145 146 reg = xe_hwmon_get_reg(hwmon, hwmon_reg, channel); 147 148 if (!xe_reg_is_valid(reg)) 149 return; 150 151 switch (operation) { 152 case REG_READ32: 153 *value = xe_mmio_read32(hwmon->gt, reg); 154 break; 155 case REG_RMW32: 156 *value = xe_mmio_rmw32(hwmon->gt, reg, clr, set); 157 break; 158 case REG_READ64: 159 *value = xe_mmio_read64_2x32(hwmon->gt, reg); 160 break; 161 default: 162 drm_warn(>_to_xe(hwmon->gt)->drm, "Invalid xe hwmon reg operation: %d\n", 163 operation); 164 break; 165 } 166 } 167 168 #define PL1_DISABLE 0 169 170 /* 171 * HW allows arbitrary PL1 limits to be set but silently clamps these values to 172 * "typical but not guaranteed" min/max values in REG_PKG_POWER_SKU. Follow the 173 * same pattern for sysfs, allow arbitrary PL1 limits to be set but display 174 * clamped values when read. 175 */ 176 static void xe_hwmon_power_max_read(struct xe_hwmon *hwmon, int channel, long *value) 177 { 178 u64 reg_val, min, max; 179 180 mutex_lock(&hwmon->hwmon_lock); 181 182 xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_READ32, ®_val, 0, 0, channel); 183 /* Check if PL1 limit is disabled */ 184 if (!(reg_val & PKG_PWR_LIM_1_EN)) { 185 *value = PL1_DISABLE; 186 goto unlock; 187 } 188 189 reg_val = REG_FIELD_GET(PKG_PWR_LIM_1, reg_val); 190 *value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon->scl_shift_power); 191 192 xe_hwmon_process_reg(hwmon, REG_PKG_POWER_SKU, REG_READ64, ®_val, 0, 0, channel); 193 min = REG_FIELD_GET(PKG_MIN_PWR, reg_val); 194 min = mul_u64_u32_shr(min, SF_POWER, hwmon->scl_shift_power); 195 max = REG_FIELD_GET(PKG_MAX_PWR, reg_val); 196 max = mul_u64_u32_shr(max, SF_POWER, hwmon->scl_shift_power); 197 198 if (min && max) 199 *value = clamp_t(u64, *value, min, max); 200 unlock: 201 mutex_unlock(&hwmon->hwmon_lock); 202 } 203 204 static int xe_hwmon_power_max_write(struct xe_hwmon *hwmon, int channel, long value) 205 { 206 int ret = 0; 207 u64 reg_val; 208 209 mutex_lock(&hwmon->hwmon_lock); 210 211 /* Disable PL1 limit and verify, as limit cannot be disabled on all platforms */ 212 if (value == PL1_DISABLE) { 213 xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW32, ®_val, 214 PKG_PWR_LIM_1_EN, 0, channel); 215 xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_READ32, ®_val, 216 PKG_PWR_LIM_1_EN, 0, channel); 217 218 if (reg_val & PKG_PWR_LIM_1_EN) { 219 ret = -EOPNOTSUPP; 220 goto unlock; 221 } 222 } 223 224 /* Computation in 64-bits to avoid overflow. Round to nearest. */ 225 reg_val = DIV_ROUND_CLOSEST_ULL((u64)value << hwmon->scl_shift_power, SF_POWER); 226 reg_val = PKG_PWR_LIM_1_EN | REG_FIELD_PREP(PKG_PWR_LIM_1, reg_val); 227 228 xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW32, ®_val, 229 PKG_PWR_LIM_1_EN | PKG_PWR_LIM_1, reg_val, channel); 230 unlock: 231 mutex_unlock(&hwmon->hwmon_lock); 232 return ret; 233 } 234 235 static void xe_hwmon_power_rated_max_read(struct xe_hwmon *hwmon, int channel, long *value) 236 { 237 u64 reg_val; 238 239 xe_hwmon_process_reg(hwmon, REG_PKG_POWER_SKU, REG_READ32, ®_val, 0, 0, channel); 240 reg_val = REG_FIELD_GET(PKG_TDP, reg_val); 241 *value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon->scl_shift_power); 242 } 243 244 /* 245 * xe_hwmon_energy_get - Obtain energy value 246 * 247 * The underlying energy hardware register is 32-bits and is subject to 248 * overflow. How long before overflow? For example, with an example 249 * scaling bit shift of 14 bits (see register *PACKAGE_POWER_SKU_UNIT) and 250 * a power draw of 1000 watts, the 32-bit counter will overflow in 251 * approximately 4.36 minutes. 252 * 253 * Examples: 254 * 1 watt: (2^32 >> 14) / 1 W / (60 * 60 * 24) secs/day -> 3 days 255 * 1000 watts: (2^32 >> 14) / 1000 W / 60 secs/min -> 4.36 minutes 256 * 257 * The function significantly increases overflow duration (from 4.36 258 * minutes) by accumulating the energy register into a 'long' as allowed by 259 * the hwmon API. Using x86_64 128 bit arithmetic (see mul_u64_u32_shr()), 260 * a 'long' of 63 bits, SF_ENERGY of 1e6 (~20 bits) and 261 * hwmon->scl_shift_energy of 14 bits we have 57 (63 - 20 + 14) bits before 262 * energyN_input overflows. This at 1000 W is an overflow duration of 278 years. 263 */ 264 static void 265 xe_hwmon_energy_get(struct xe_hwmon *hwmon, int channel, long *energy) 266 { 267 struct xe_hwmon_energy_info *ei = &hwmon->ei[channel]; 268 u64 reg_val; 269 270 xe_hwmon_process_reg(hwmon, REG_PKG_ENERGY_STATUS, REG_READ32, 271 ®_val, 0, 0, channel); 272 273 if (reg_val >= ei->reg_val_prev) 274 ei->accum_energy += reg_val - ei->reg_val_prev; 275 else 276 ei->accum_energy += UINT_MAX - ei->reg_val_prev + reg_val; 277 278 ei->reg_val_prev = reg_val; 279 280 *energy = mul_u64_u32_shr(ei->accum_energy, SF_ENERGY, 281 hwmon->scl_shift_energy); 282 } 283 284 static ssize_t 285 xe_hwmon_power_max_interval_show(struct device *dev, struct device_attribute *attr, 286 char *buf) 287 { 288 struct xe_hwmon *hwmon = dev_get_drvdata(dev); 289 u32 x, y, x_w = 2; /* 2 bits */ 290 u64 r, tau4, out; 291 int sensor_index = to_sensor_dev_attr(attr)->index; 292 293 xe_pm_runtime_get(gt_to_xe(hwmon->gt)); 294 295 mutex_lock(&hwmon->hwmon_lock); 296 297 xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, 298 REG_READ32, &r, 0, 0, sensor_index); 299 300 mutex_unlock(&hwmon->hwmon_lock); 301 302 xe_pm_runtime_put(gt_to_xe(hwmon->gt)); 303 304 x = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_X, r); 305 y = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_Y, r); 306 307 /* 308 * tau = 1.x * power(2,y), x = bits(23:22), y = bits(21:17) 309 * = (4 | x) << (y - 2) 310 * 311 * Here (y - 2) ensures a 1.x fixed point representation of 1.x 312 * As x is 2 bits so 1.x can be 1.0, 1.25, 1.50, 1.75 313 * 314 * As y can be < 2, we compute tau4 = (4 | x) << y 315 * and then add 2 when doing the final right shift to account for units 316 */ 317 tau4 = (u64)((1 << x_w) | x) << y; 318 319 /* val in hwmon interface units (millisec) */ 320 out = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w); 321 322 return sysfs_emit(buf, "%llu\n", out); 323 } 324 325 static ssize_t 326 xe_hwmon_power_max_interval_store(struct device *dev, struct device_attribute *attr, 327 const char *buf, size_t count) 328 { 329 struct xe_hwmon *hwmon = dev_get_drvdata(dev); 330 u32 x, y, rxy, x_w = 2; /* 2 bits */ 331 u64 tau4, r, max_win; 332 unsigned long val; 333 int ret; 334 int sensor_index = to_sensor_dev_attr(attr)->index; 335 336 ret = kstrtoul(buf, 0, &val); 337 if (ret) 338 return ret; 339 340 /* 341 * Max HW supported tau in '1.x * power(2,y)' format, x = 0, y = 0x12. 342 * The hwmon->scl_shift_time default of 0xa results in a max tau of 256 seconds. 343 * 344 * The ideal scenario is for PKG_MAX_WIN to be read from the PKG_PWR_SKU register. 345 * However, it is observed that existing discrete GPUs does not provide correct 346 * PKG_MAX_WIN value, therefore a using default constant value. For future discrete GPUs 347 * this may get resolved, in which case PKG_MAX_WIN should be obtained from PKG_PWR_SKU. 348 */ 349 #define PKG_MAX_WIN_DEFAULT 0x12ull 350 351 /* 352 * val must be < max in hwmon interface units. The steps below are 353 * explained in xe_hwmon_power_max_interval_show() 354 */ 355 r = FIELD_PREP(PKG_MAX_WIN, PKG_MAX_WIN_DEFAULT); 356 x = REG_FIELD_GET(PKG_MAX_WIN_X, r); 357 y = REG_FIELD_GET(PKG_MAX_WIN_Y, r); 358 tau4 = (u64)((1 << x_w) | x) << y; 359 max_win = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w); 360 361 if (val > max_win) 362 return -EINVAL; 363 364 /* val in hw units */ 365 val = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_time, SF_TIME); 366 367 /* 368 * Convert val to 1.x * power(2,y) 369 * y = ilog2(val) 370 * x = (val - (1 << y)) >> (y - 2) 371 */ 372 if (!val) { 373 y = 0; 374 x = 0; 375 } else { 376 y = ilog2(val); 377 x = (val - (1ul << y)) << x_w >> y; 378 } 379 380 rxy = REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_X, x) | REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_Y, y); 381 382 xe_pm_runtime_get(gt_to_xe(hwmon->gt)); 383 384 mutex_lock(&hwmon->hwmon_lock); 385 386 xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW32, (u64 *)&r, 387 PKG_PWR_LIM_1_TIME, rxy, sensor_index); 388 389 mutex_unlock(&hwmon->hwmon_lock); 390 391 xe_pm_runtime_put(gt_to_xe(hwmon->gt)); 392 393 return count; 394 } 395 396 static SENSOR_DEVICE_ATTR(power1_max_interval, 0664, 397 xe_hwmon_power_max_interval_show, 398 xe_hwmon_power_max_interval_store, CHANNEL_CARD); 399 400 static SENSOR_DEVICE_ATTR(power2_max_interval, 0664, 401 xe_hwmon_power_max_interval_show, 402 xe_hwmon_power_max_interval_store, CHANNEL_PKG); 403 404 static struct attribute *hwmon_attributes[] = { 405 &sensor_dev_attr_power1_max_interval.dev_attr.attr, 406 &sensor_dev_attr_power2_max_interval.dev_attr.attr, 407 NULL 408 }; 409 410 static umode_t xe_hwmon_attributes_visible(struct kobject *kobj, 411 struct attribute *attr, int index) 412 { 413 struct device *dev = kobj_to_dev(kobj); 414 struct xe_hwmon *hwmon = dev_get_drvdata(dev); 415 int ret = 0; 416 417 xe_pm_runtime_get(gt_to_xe(hwmon->gt)); 418 419 ret = xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, index)) ? attr->mode : 0; 420 421 xe_pm_runtime_put(gt_to_xe(hwmon->gt)); 422 423 return ret; 424 } 425 426 static const struct attribute_group hwmon_attrgroup = { 427 .attrs = hwmon_attributes, 428 .is_visible = xe_hwmon_attributes_visible, 429 }; 430 431 static const struct attribute_group *hwmon_groups[] = { 432 &hwmon_attrgroup, 433 NULL 434 }; 435 436 static const struct hwmon_channel_info * const hwmon_info[] = { 437 HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_LABEL, 438 HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_CRIT | HWMON_P_LABEL), 439 HWMON_CHANNEL_INFO(curr, HWMON_C_LABEL, HWMON_C_CRIT | HWMON_C_LABEL), 440 HWMON_CHANNEL_INFO(in, HWMON_I_INPUT | HWMON_I_LABEL, HWMON_I_INPUT | HWMON_I_LABEL), 441 HWMON_CHANNEL_INFO(energy, HWMON_E_INPUT | HWMON_E_LABEL, HWMON_E_INPUT | HWMON_E_LABEL), 442 NULL 443 }; 444 445 /* I1 is exposed as power_crit or as curr_crit depending on bit 31 */ 446 static int xe_hwmon_pcode_read_i1(struct xe_gt *gt, u32 *uval) 447 { 448 /* Avoid Illegal Subcommand error */ 449 if (gt_to_xe(gt)->info.platform == XE_DG2) 450 return -ENXIO; 451 452 return xe_pcode_read(gt, PCODE_MBOX(PCODE_POWER_SETUP, 453 POWER_SETUP_SUBCOMMAND_READ_I1, 0), 454 uval, NULL); 455 } 456 457 static int xe_hwmon_pcode_write_i1(struct xe_gt *gt, u32 uval) 458 { 459 return xe_pcode_write(gt, PCODE_MBOX(PCODE_POWER_SETUP, 460 POWER_SETUP_SUBCOMMAND_WRITE_I1, 0), 461 uval); 462 } 463 464 static int xe_hwmon_power_curr_crit_read(struct xe_hwmon *hwmon, int channel, 465 long *value, u32 scale_factor) 466 { 467 int ret; 468 u32 uval; 469 470 mutex_lock(&hwmon->hwmon_lock); 471 472 ret = xe_hwmon_pcode_read_i1(hwmon->gt, &uval); 473 if (ret) 474 goto unlock; 475 476 *value = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval), 477 scale_factor, POWER_SETUP_I1_SHIFT); 478 unlock: 479 mutex_unlock(&hwmon->hwmon_lock); 480 return ret; 481 } 482 483 static int xe_hwmon_power_curr_crit_write(struct xe_hwmon *hwmon, int channel, 484 long value, u32 scale_factor) 485 { 486 int ret; 487 u32 uval; 488 489 mutex_lock(&hwmon->hwmon_lock); 490 491 uval = DIV_ROUND_CLOSEST_ULL(value << POWER_SETUP_I1_SHIFT, scale_factor); 492 ret = xe_hwmon_pcode_write_i1(hwmon->gt, uval); 493 494 mutex_unlock(&hwmon->hwmon_lock); 495 return ret; 496 } 497 498 static void xe_hwmon_get_voltage(struct xe_hwmon *hwmon, int channel, long *value) 499 { 500 u64 reg_val; 501 502 xe_hwmon_process_reg(hwmon, REG_GT_PERF_STATUS, 503 REG_READ32, ®_val, 0, 0, channel); 504 /* HW register value in units of 2.5 millivolt */ 505 *value = DIV_ROUND_CLOSEST(REG_FIELD_GET(VOLTAGE_MASK, reg_val) * 2500, SF_VOLTAGE); 506 } 507 508 static umode_t 509 xe_hwmon_power_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel) 510 { 511 u32 uval; 512 513 switch (attr) { 514 case hwmon_power_max: 515 return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, 516 channel)) ? 0664 : 0; 517 case hwmon_power_rated_max: 518 return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU, 519 channel)) ? 0444 : 0; 520 case hwmon_power_crit: 521 if (channel == CHANNEL_PKG) 522 return (xe_hwmon_pcode_read_i1(hwmon->gt, &uval) || 523 !(uval & POWER_SETUP_I1_WATTS)) ? 0 : 0644; 524 break; 525 case hwmon_power_label: 526 return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU_UNIT, 527 channel)) ? 0444 : 0; 528 default: 529 return 0; 530 } 531 return 0; 532 } 533 534 static int 535 xe_hwmon_power_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val) 536 { 537 switch (attr) { 538 case hwmon_power_max: 539 xe_hwmon_power_max_read(hwmon, channel, val); 540 return 0; 541 case hwmon_power_rated_max: 542 xe_hwmon_power_rated_max_read(hwmon, channel, val); 543 return 0; 544 case hwmon_power_crit: 545 return xe_hwmon_power_curr_crit_read(hwmon, channel, val, SF_POWER); 546 default: 547 return -EOPNOTSUPP; 548 } 549 } 550 551 static int 552 xe_hwmon_power_write(struct xe_hwmon *hwmon, u32 attr, int channel, long val) 553 { 554 switch (attr) { 555 case hwmon_power_max: 556 return xe_hwmon_power_max_write(hwmon, channel, val); 557 case hwmon_power_crit: 558 return xe_hwmon_power_curr_crit_write(hwmon, channel, val, SF_POWER); 559 default: 560 return -EOPNOTSUPP; 561 } 562 } 563 564 static umode_t 565 xe_hwmon_curr_is_visible(const struct xe_hwmon *hwmon, u32 attr, int channel) 566 { 567 u32 uval; 568 569 /* hwmon sysfs attribute of current available only for package */ 570 if (channel != CHANNEL_PKG) 571 return 0; 572 573 switch (attr) { 574 case hwmon_curr_crit: 575 return (xe_hwmon_pcode_read_i1(hwmon->gt, &uval) || 576 (uval & POWER_SETUP_I1_WATTS)) ? 0 : 0644; 577 case hwmon_curr_label: 578 return (xe_hwmon_pcode_read_i1(hwmon->gt, &uval) || 579 (uval & POWER_SETUP_I1_WATTS)) ? 0 : 0444; 580 break; 581 default: 582 return 0; 583 } 584 return 0; 585 } 586 587 static int 588 xe_hwmon_curr_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val) 589 { 590 switch (attr) { 591 case hwmon_curr_crit: 592 return xe_hwmon_power_curr_crit_read(hwmon, channel, val, SF_CURR); 593 default: 594 return -EOPNOTSUPP; 595 } 596 } 597 598 static int 599 xe_hwmon_curr_write(struct xe_hwmon *hwmon, u32 attr, int channel, long val) 600 { 601 switch (attr) { 602 case hwmon_curr_crit: 603 return xe_hwmon_power_curr_crit_write(hwmon, channel, val, SF_CURR); 604 default: 605 return -EOPNOTSUPP; 606 } 607 } 608 609 static umode_t 610 xe_hwmon_in_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel) 611 { 612 switch (attr) { 613 case hwmon_in_input: 614 case hwmon_in_label: 615 return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_GT_PERF_STATUS, 616 channel)) ? 0444 : 0; 617 default: 618 return 0; 619 } 620 } 621 622 static int 623 xe_hwmon_in_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val) 624 { 625 switch (attr) { 626 case hwmon_in_input: 627 xe_hwmon_get_voltage(hwmon, channel, val); 628 return 0; 629 default: 630 return -EOPNOTSUPP; 631 } 632 } 633 634 static umode_t 635 xe_hwmon_energy_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel) 636 { 637 switch (attr) { 638 case hwmon_energy_input: 639 case hwmon_energy_label: 640 return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_PKG_ENERGY_STATUS, 641 channel)) ? 0444 : 0; 642 default: 643 return 0; 644 } 645 } 646 647 static int 648 xe_hwmon_energy_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val) 649 { 650 switch (attr) { 651 case hwmon_energy_input: 652 xe_hwmon_energy_get(hwmon, channel, val); 653 return 0; 654 default: 655 return -EOPNOTSUPP; 656 } 657 } 658 659 static umode_t 660 xe_hwmon_is_visible(const void *drvdata, enum hwmon_sensor_types type, 661 u32 attr, int channel) 662 { 663 struct xe_hwmon *hwmon = (struct xe_hwmon *)drvdata; 664 int ret; 665 666 xe_pm_runtime_get(gt_to_xe(hwmon->gt)); 667 668 switch (type) { 669 case hwmon_power: 670 ret = xe_hwmon_power_is_visible(hwmon, attr, channel); 671 break; 672 case hwmon_curr: 673 ret = xe_hwmon_curr_is_visible(hwmon, attr, channel); 674 break; 675 case hwmon_in: 676 ret = xe_hwmon_in_is_visible(hwmon, attr, channel); 677 break; 678 case hwmon_energy: 679 ret = xe_hwmon_energy_is_visible(hwmon, attr, channel); 680 break; 681 default: 682 ret = 0; 683 break; 684 } 685 686 xe_pm_runtime_put(gt_to_xe(hwmon->gt)); 687 688 return ret; 689 } 690 691 static int 692 xe_hwmon_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, 693 int channel, long *val) 694 { 695 struct xe_hwmon *hwmon = dev_get_drvdata(dev); 696 int ret; 697 698 xe_pm_runtime_get(gt_to_xe(hwmon->gt)); 699 700 switch (type) { 701 case hwmon_power: 702 ret = xe_hwmon_power_read(hwmon, attr, channel, val); 703 break; 704 case hwmon_curr: 705 ret = xe_hwmon_curr_read(hwmon, attr, channel, val); 706 break; 707 case hwmon_in: 708 ret = xe_hwmon_in_read(hwmon, attr, channel, val); 709 break; 710 case hwmon_energy: 711 ret = xe_hwmon_energy_read(hwmon, attr, channel, val); 712 break; 713 default: 714 ret = -EOPNOTSUPP; 715 break; 716 } 717 718 xe_pm_runtime_put(gt_to_xe(hwmon->gt)); 719 720 return ret; 721 } 722 723 static int 724 xe_hwmon_write(struct device *dev, enum hwmon_sensor_types type, u32 attr, 725 int channel, long val) 726 { 727 struct xe_hwmon *hwmon = dev_get_drvdata(dev); 728 int ret; 729 730 xe_pm_runtime_get(gt_to_xe(hwmon->gt)); 731 732 switch (type) { 733 case hwmon_power: 734 ret = xe_hwmon_power_write(hwmon, attr, channel, val); 735 break; 736 case hwmon_curr: 737 ret = xe_hwmon_curr_write(hwmon, attr, channel, val); 738 break; 739 default: 740 ret = -EOPNOTSUPP; 741 break; 742 } 743 744 xe_pm_runtime_put(gt_to_xe(hwmon->gt)); 745 746 return ret; 747 } 748 749 static int xe_hwmon_read_label(struct device *dev, 750 enum hwmon_sensor_types type, 751 u32 attr, int channel, const char **str) 752 { 753 switch (type) { 754 case hwmon_power: 755 case hwmon_energy: 756 case hwmon_curr: 757 case hwmon_in: 758 if (channel == CHANNEL_CARD) 759 *str = "card"; 760 else if (channel == CHANNEL_PKG) 761 *str = "pkg"; 762 return 0; 763 default: 764 return -EOPNOTSUPP; 765 } 766 } 767 768 static const struct hwmon_ops hwmon_ops = { 769 .is_visible = xe_hwmon_is_visible, 770 .read = xe_hwmon_read, 771 .write = xe_hwmon_write, 772 .read_string = xe_hwmon_read_label, 773 }; 774 775 static const struct hwmon_chip_info hwmon_chip_info = { 776 .ops = &hwmon_ops, 777 .info = hwmon_info, 778 }; 779 780 static void 781 xe_hwmon_get_preregistration_info(struct xe_device *xe) 782 { 783 struct xe_hwmon *hwmon = xe->hwmon; 784 long energy; 785 u64 val_sku_unit = 0; 786 int channel; 787 788 /* 789 * The contents of register PKG_POWER_SKU_UNIT do not change, 790 * so read it once and store the shift values. 791 */ 792 if (xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU_UNIT, 0))) { 793 xe_hwmon_process_reg(hwmon, REG_PKG_POWER_SKU_UNIT, 794 REG_READ32, &val_sku_unit, 0, 0, 0); 795 hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit); 796 hwmon->scl_shift_energy = REG_FIELD_GET(PKG_ENERGY_UNIT, val_sku_unit); 797 hwmon->scl_shift_time = REG_FIELD_GET(PKG_TIME_UNIT, val_sku_unit); 798 } 799 800 /* 801 * Initialize 'struct xe_hwmon_energy_info', i.e. set fields to the 802 * first value of the energy register read 803 */ 804 for (channel = 0; channel < CHANNEL_MAX; channel++) 805 if (xe_hwmon_is_visible(hwmon, hwmon_energy, hwmon_energy_input, channel)) 806 xe_hwmon_energy_get(hwmon, channel, &energy); 807 } 808 809 static void xe_hwmon_mutex_destroy(void *arg) 810 { 811 struct xe_hwmon *hwmon = arg; 812 813 mutex_destroy(&hwmon->hwmon_lock); 814 } 815 816 void xe_hwmon_register(struct xe_device *xe) 817 { 818 struct device *dev = xe->drm.dev; 819 struct xe_hwmon *hwmon; 820 821 /* hwmon is available only for dGfx */ 822 if (!IS_DGFX(xe)) 823 return; 824 825 /* hwmon is not available on VFs */ 826 if (IS_SRIOV_VF(xe)) 827 return; 828 829 hwmon = devm_kzalloc(dev, sizeof(*hwmon), GFP_KERNEL); 830 if (!hwmon) 831 return; 832 833 xe->hwmon = hwmon; 834 835 mutex_init(&hwmon->hwmon_lock); 836 if (devm_add_action_or_reset(dev, xe_hwmon_mutex_destroy, hwmon)) 837 return; 838 839 /* primary GT to access device level properties */ 840 hwmon->gt = xe->tiles[0].primary_gt; 841 842 xe_hwmon_get_preregistration_info(xe); 843 844 drm_dbg(&xe->drm, "Register xe hwmon interface\n"); 845 846 /* hwmon_dev points to device hwmon<i> */ 847 hwmon->hwmon_dev = devm_hwmon_device_register_with_info(dev, "xe", hwmon, 848 &hwmon_chip_info, 849 hwmon_groups); 850 851 if (IS_ERR(hwmon->hwmon_dev)) { 852 drm_warn(&xe->drm, "Failed to register xe hwmon (%pe)\n", hwmon->hwmon_dev); 853 xe->hwmon = NULL; 854 return; 855 } 856 } 857 858