1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #include <linux/hwmon-sysfs.h> 7 #include <linux/hwmon.h> 8 #include <linux/jiffies.h> 9 #include <linux/types.h> 10 #include <linux/units.h> 11 12 #include <drm/drm_managed.h> 13 #include "regs/xe_gt_regs.h" 14 #include "regs/xe_mchbar_regs.h" 15 #include "regs/xe_pcode_regs.h" 16 #include "xe_device.h" 17 #include "xe_hwmon.h" 18 #include "xe_mmio.h" 19 #include "xe_pcode.h" 20 #include "xe_pcode_api.h" 21 #include "xe_sriov.h" 22 #include "xe_pm.h" 23 24 enum xe_hwmon_reg { 25 REG_TEMP, 26 REG_PKG_RAPL_LIMIT, 27 REG_PKG_POWER_SKU, 28 REG_PKG_POWER_SKU_UNIT, 29 REG_GT_PERF_STATUS, 30 REG_PKG_ENERGY_STATUS, 31 REG_FAN_SPEED, 32 }; 33 34 enum xe_hwmon_reg_operation { 35 REG_READ32, 36 REG_RMW32, 37 REG_READ64, 38 }; 39 40 enum xe_hwmon_channel { 41 CHANNEL_CARD, 42 CHANNEL_PKG, 43 CHANNEL_VRAM, 44 CHANNEL_MAX, 45 }; 46 47 enum xe_fan_channel { 48 FAN_1, 49 FAN_2, 50 FAN_3, 51 FAN_MAX, 52 }; 53 54 /* 55 * For platforms that support mailbox commands for power limits, REG_PKG_POWER_SKU_UNIT is 56 * not supported and below are SKU units to be used. 57 */ 58 #define PWR_UNIT 0x3 59 #define ENERGY_UNIT 0xe 60 #define TIME_UNIT 0xa 61 62 /* 63 * SF_* - scale factors for particular quantities according to hwmon spec. 64 */ 65 #define SF_POWER 1000000 /* microwatts */ 66 #define SF_CURR 1000 /* milliamperes */ 67 #define SF_VOLTAGE 1000 /* millivolts */ 68 #define SF_ENERGY 1000000 /* microjoules */ 69 #define SF_TIME 1000 /* milliseconds */ 70 71 /* 72 * PL*_HWMON_ATTR - mapping of hardware power limits to corresponding hwmon power attribute. 73 */ 74 #define PL1_HWMON_ATTR hwmon_power_max 75 76 #define PWR_ATTR_TO_STR(attr) (((attr) == hwmon_power_max) ? "PL1" : "Invalid") 77 78 /* 79 * Timeout for power limit write mailbox command. 80 */ 81 #define PL_WRITE_MBX_TIMEOUT_MS (1) 82 83 /** 84 * struct xe_hwmon_energy_info - to accumulate energy 85 */ 86 struct xe_hwmon_energy_info { 87 /** @reg_val_prev: previous energy reg val */ 88 u32 reg_val_prev; 89 /** @accum_energy: accumulated energy */ 90 long accum_energy; 91 }; 92 93 /** 94 * struct xe_hwmon_fan_info - to cache previous fan reading 95 */ 96 struct xe_hwmon_fan_info { 97 /** @reg_val_prev: previous fan reg val */ 98 u32 reg_val_prev; 99 /** @time_prev: previous timestamp */ 100 u64 time_prev; 101 }; 102 103 /** 104 * struct xe_hwmon - xe hwmon data structure 105 */ 106 struct xe_hwmon { 107 /** @hwmon_dev: hwmon device for xe */ 108 struct device *hwmon_dev; 109 /** @xe: Xe device */ 110 struct xe_device *xe; 111 /** @hwmon_lock: lock for rw attributes*/ 112 struct mutex hwmon_lock; 113 /** @scl_shift_power: pkg power unit */ 114 int scl_shift_power; 115 /** @scl_shift_energy: pkg energy unit */ 116 int scl_shift_energy; 117 /** @scl_shift_time: pkg time unit */ 118 int scl_shift_time; 119 /** @ei: Energy info for energyN_input */ 120 struct xe_hwmon_energy_info ei[CHANNEL_MAX]; 121 /** @fi: Fan info for fanN_input */ 122 struct xe_hwmon_fan_info fi[FAN_MAX]; 123 /** @boot_power_limit_read: is boot power limits read */ 124 bool boot_power_limit_read; 125 /** @pl1_on_boot: power limit PL1 on boot */ 126 u32 pl1_on_boot[CHANNEL_MAX]; 127 }; 128 129 static int xe_hwmon_pcode_read_power_limit(const struct xe_hwmon *hwmon, u32 attr, int channel, 130 u32 *uval) 131 { 132 struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe); 133 u32 val0 = 0, val1 = 0; 134 int ret = 0; 135 136 ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_POWER_SETUP, 137 (channel == CHANNEL_CARD) ? 138 READ_PSYSGPU_POWER_LIMIT : 139 READ_PACKAGE_POWER_LIMIT, 140 hwmon->boot_power_limit_read ? 141 READ_PL_FROM_PCODE : READ_PL_FROM_FW), 142 &val0, &val1); 143 144 if (ret) { 145 drm_dbg(&hwmon->xe->drm, "read failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n", 146 channel, val0, val1, ret); 147 *uval = 0; 148 return ret; 149 } 150 151 /* return the value only if limit is enabled */ 152 if (attr == PL1_HWMON_ATTR) 153 *uval = (val0 & PWR_LIM_EN) ? val0 : 0; 154 else if (attr == hwmon_power_label) 155 *uval = (val0 & PWR_LIM_EN) ? 1 : 0; 156 else 157 *uval = 0; 158 159 return ret; 160 } 161 162 static int xe_hwmon_pcode_rmw_power_limit(const struct xe_hwmon *hwmon, u32 attr, u8 channel, 163 u32 clr, u32 set) 164 { 165 struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe); 166 u32 val0, val1; 167 int ret = 0; 168 169 ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_POWER_SETUP, 170 (channel == CHANNEL_CARD) ? 171 READ_PSYSGPU_POWER_LIMIT : 172 READ_PACKAGE_POWER_LIMIT, 173 hwmon->boot_power_limit_read ? 174 READ_PL_FROM_PCODE : READ_PL_FROM_FW), 175 &val0, &val1); 176 177 if (ret) 178 drm_dbg(&hwmon->xe->drm, "read failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n", 179 channel, val0, val1, ret); 180 181 if (attr == PL1_HWMON_ATTR) 182 val0 = (val0 & ~clr) | set; 183 else 184 return -EIO; 185 186 ret = xe_pcode_write64_timeout(root_tile, PCODE_MBOX(PCODE_POWER_SETUP, 187 (channel == CHANNEL_CARD) ? 188 WRITE_PSYSGPU_POWER_LIMIT : 189 WRITE_PACKAGE_POWER_LIMIT, 0), 190 val0, val1, PL_WRITE_MBX_TIMEOUT_MS); 191 if (ret) 192 drm_dbg(&hwmon->xe->drm, "write failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n", 193 channel, val0, val1, ret); 194 return ret; 195 } 196 197 static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg, 198 int channel) 199 { 200 struct xe_device *xe = hwmon->xe; 201 202 switch (hwmon_reg) { 203 case REG_TEMP: 204 if (xe->info.platform == XE_BATTLEMAGE) { 205 if (channel == CHANNEL_PKG) 206 return BMG_PACKAGE_TEMPERATURE; 207 else if (channel == CHANNEL_VRAM) 208 return BMG_VRAM_TEMPERATURE; 209 } else if (xe->info.platform == XE_DG2) { 210 if (channel == CHANNEL_PKG) 211 return PCU_CR_PACKAGE_TEMPERATURE; 212 else if (channel == CHANNEL_VRAM) 213 return BMG_VRAM_TEMPERATURE; 214 } 215 break; 216 case REG_PKG_RAPL_LIMIT: 217 if (xe->info.platform == XE_PVC && channel == CHANNEL_PKG) 218 return PVC_GT0_PACKAGE_RAPL_LIMIT; 219 else if ((xe->info.platform == XE_DG2) && (channel == CHANNEL_PKG)) 220 return PCU_CR_PACKAGE_RAPL_LIMIT; 221 break; 222 case REG_PKG_POWER_SKU: 223 if (xe->info.platform == XE_PVC && channel == CHANNEL_PKG) 224 return PVC_GT0_PACKAGE_POWER_SKU; 225 else if ((xe->info.platform == XE_DG2) && (channel == CHANNEL_PKG)) 226 return PCU_CR_PACKAGE_POWER_SKU; 227 break; 228 case REG_PKG_POWER_SKU_UNIT: 229 if (xe->info.platform == XE_PVC) 230 return PVC_GT0_PACKAGE_POWER_SKU_UNIT; 231 else if (xe->info.platform == XE_DG2) 232 return PCU_CR_PACKAGE_POWER_SKU_UNIT; 233 break; 234 case REG_GT_PERF_STATUS: 235 if (xe->info.platform == XE_DG2 && channel == CHANNEL_PKG) 236 return GT_PERF_STATUS; 237 break; 238 case REG_PKG_ENERGY_STATUS: 239 if (xe->info.platform == XE_BATTLEMAGE) { 240 if (channel == CHANNEL_PKG) 241 return BMG_PACKAGE_ENERGY_STATUS; 242 else 243 return BMG_PLATFORM_ENERGY_STATUS; 244 } else if (xe->info.platform == XE_PVC && channel == CHANNEL_PKG) { 245 return PVC_GT0_PLATFORM_ENERGY_STATUS; 246 } else if ((xe->info.platform == XE_DG2) && (channel == CHANNEL_PKG)) { 247 return PCU_CR_PACKAGE_ENERGY_STATUS; 248 } 249 break; 250 case REG_FAN_SPEED: 251 if (channel == FAN_1) 252 return BMG_FAN_1_SPEED; 253 else if (channel == FAN_2) 254 return BMG_FAN_2_SPEED; 255 else if (channel == FAN_3) 256 return BMG_FAN_3_SPEED; 257 break; 258 default: 259 drm_warn(&xe->drm, "Unknown xe hwmon reg id: %d\n", hwmon_reg); 260 break; 261 } 262 263 return XE_REG(0); 264 } 265 266 #define PL_DISABLE 0 267 268 /* 269 * HW allows arbitrary PL1 limits to be set but silently clamps these values to 270 * "typical but not guaranteed" min/max values in REG_PKG_POWER_SKU. Follow the 271 * same pattern for sysfs, allow arbitrary PL1 limits to be set but display 272 * clamped values when read. 273 */ 274 static void xe_hwmon_power_max_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *value) 275 { 276 u64 reg_val, min, max; 277 struct xe_device *xe = hwmon->xe; 278 struct xe_reg rapl_limit, pkg_power_sku; 279 struct xe_mmio *mmio = xe_root_tile_mmio(xe); 280 281 mutex_lock(&hwmon->hwmon_lock); 282 283 if (hwmon->xe->info.has_mbx_power_limits) { 284 xe_hwmon_pcode_read_power_limit(hwmon, attr, channel, (u32 *)®_val); 285 } else { 286 rapl_limit = xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel); 287 pkg_power_sku = xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU, channel); 288 289 /* 290 * Valid check of REG_PKG_RAPL_LIMIT is already done in xe_hwmon_power_is_visible. 291 * So not checking it again here. 292 */ 293 if (!xe_reg_is_valid(pkg_power_sku)) { 294 drm_warn(&xe->drm, "pkg_power_sku invalid\n"); 295 *value = 0; 296 goto unlock; 297 } 298 reg_val = xe_mmio_read32(mmio, rapl_limit); 299 } 300 301 /* Check if PL limits are disabled. */ 302 if (!(reg_val & PWR_LIM_EN)) { 303 *value = PL_DISABLE; 304 drm_info(&hwmon->xe->drm, "%s disabled for channel %d, val 0x%016llx\n", 305 PWR_ATTR_TO_STR(attr), channel, reg_val); 306 goto unlock; 307 } 308 309 reg_val = REG_FIELD_GET(PWR_LIM_VAL, reg_val); 310 *value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon->scl_shift_power); 311 312 /* For platforms with mailbox power limit support clamping would be done by pcode. */ 313 if (!hwmon->xe->info.has_mbx_power_limits) { 314 reg_val = xe_mmio_read64_2x32(mmio, pkg_power_sku); 315 min = REG_FIELD_GET(PKG_MIN_PWR, reg_val); 316 max = REG_FIELD_GET(PKG_MAX_PWR, reg_val); 317 min = mul_u64_u32_shr(min, SF_POWER, hwmon->scl_shift_power); 318 max = mul_u64_u32_shr(max, SF_POWER, hwmon->scl_shift_power); 319 if (min && max) 320 *value = clamp_t(u64, *value, min, max); 321 } 322 unlock: 323 mutex_unlock(&hwmon->hwmon_lock); 324 } 325 326 static int xe_hwmon_power_max_write(struct xe_hwmon *hwmon, u32 attr, int channel, long value) 327 { 328 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 329 int ret = 0; 330 u32 reg_val; 331 struct xe_reg rapl_limit; 332 333 mutex_lock(&hwmon->hwmon_lock); 334 335 rapl_limit = xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel); 336 337 /* Disable Power Limit and verify, as limit cannot be disabled on all platforms. */ 338 if (value == PL_DISABLE) { 339 if (hwmon->xe->info.has_mbx_power_limits) { 340 drm_dbg(&hwmon->xe->drm, "disabling %s on channel %d\n", 341 PWR_ATTR_TO_STR(attr), channel); 342 xe_hwmon_pcode_rmw_power_limit(hwmon, attr, channel, PWR_LIM_EN, 0); 343 xe_hwmon_pcode_read_power_limit(hwmon, attr, channel, ®_val); 344 } else { 345 reg_val = xe_mmio_rmw32(mmio, rapl_limit, PWR_LIM_EN, 0); 346 reg_val = xe_mmio_read32(mmio, rapl_limit); 347 } 348 349 if (reg_val & PWR_LIM_EN) { 350 drm_warn(&hwmon->xe->drm, "Power limit disable is not supported!\n"); 351 ret = -EOPNOTSUPP; 352 } 353 goto unlock; 354 } 355 356 /* Computation in 64-bits to avoid overflow. Round to nearest. */ 357 reg_val = DIV_ROUND_CLOSEST_ULL((u64)value << hwmon->scl_shift_power, SF_POWER); 358 reg_val = PWR_LIM_EN | REG_FIELD_PREP(PWR_LIM_VAL, reg_val); 359 360 /* 361 * Clamp power limit to card-firmware default as maximum, as an additional protection to 362 * pcode clamp. 363 */ 364 if (hwmon->xe->info.has_mbx_power_limits) { 365 if (reg_val > REG_FIELD_GET(PWR_LIM_VAL, hwmon->pl1_on_boot[channel])) { 366 reg_val = REG_FIELD_GET(PWR_LIM_VAL, hwmon->pl1_on_boot[channel]); 367 drm_dbg(&hwmon->xe->drm, "Clamping power limit to firmware default 0x%x\n", 368 reg_val); 369 } 370 } 371 372 if (hwmon->xe->info.has_mbx_power_limits) 373 ret = xe_hwmon_pcode_rmw_power_limit(hwmon, attr, channel, PWR_LIM, reg_val); 374 else 375 reg_val = xe_mmio_rmw32(mmio, rapl_limit, PWR_LIM, reg_val); 376 unlock: 377 mutex_unlock(&hwmon->hwmon_lock); 378 return ret; 379 } 380 381 static void xe_hwmon_power_rated_max_read(struct xe_hwmon *hwmon, u32 attr, int channel, 382 long *value) 383 { 384 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 385 u32 reg_val; 386 387 if (hwmon->xe->info.has_mbx_power_limits) { 388 /* PL1 is rated max if supported. */ 389 xe_hwmon_pcode_read_power_limit(hwmon, PL1_HWMON_ATTR, channel, ®_val); 390 } else { 391 /* 392 * This sysfs file won't be visible if REG_PKG_POWER_SKU is invalid, so valid check 393 * for this register can be skipped. 394 * See xe_hwmon_power_is_visible. 395 */ 396 struct xe_reg reg = xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU, channel); 397 398 reg_val = xe_mmio_read32(mmio, reg); 399 } 400 401 reg_val = REG_FIELD_GET(PKG_TDP, reg_val); 402 *value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon->scl_shift_power); 403 } 404 405 /* 406 * xe_hwmon_energy_get - Obtain energy value 407 * 408 * The underlying energy hardware register is 32-bits and is subject to 409 * overflow. How long before overflow? For example, with an example 410 * scaling bit shift of 14 bits (see register *PACKAGE_POWER_SKU_UNIT) and 411 * a power draw of 1000 watts, the 32-bit counter will overflow in 412 * approximately 4.36 minutes. 413 * 414 * Examples: 415 * 1 watt: (2^32 >> 14) / 1 W / (60 * 60 * 24) secs/day -> 3 days 416 * 1000 watts: (2^32 >> 14) / 1000 W / 60 secs/min -> 4.36 minutes 417 * 418 * The function significantly increases overflow duration (from 4.36 419 * minutes) by accumulating the energy register into a 'long' as allowed by 420 * the hwmon API. Using x86_64 128 bit arithmetic (see mul_u64_u32_shr()), 421 * a 'long' of 63 bits, SF_ENERGY of 1e6 (~20 bits) and 422 * hwmon->scl_shift_energy of 14 bits we have 57 (63 - 20 + 14) bits before 423 * energyN_input overflows. This at 1000 W is an overflow duration of 278 years. 424 */ 425 static void 426 xe_hwmon_energy_get(struct xe_hwmon *hwmon, int channel, long *energy) 427 { 428 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 429 struct xe_hwmon_energy_info *ei = &hwmon->ei[channel]; 430 u64 reg_val; 431 432 reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_PKG_ENERGY_STATUS, 433 channel)); 434 435 if (reg_val >= ei->reg_val_prev) 436 ei->accum_energy += reg_val - ei->reg_val_prev; 437 else 438 ei->accum_energy += UINT_MAX - ei->reg_val_prev + reg_val; 439 440 ei->reg_val_prev = reg_val; 441 442 *energy = mul_u64_u32_shr(ei->accum_energy, SF_ENERGY, 443 hwmon->scl_shift_energy); 444 } 445 446 static ssize_t 447 xe_hwmon_power_max_interval_show(struct device *dev, struct device_attribute *attr, 448 char *buf) 449 { 450 struct xe_hwmon *hwmon = dev_get_drvdata(dev); 451 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 452 u32 x, y, x_w = 2; /* 2 bits */ 453 u64 r, tau4, out; 454 int channel = to_sensor_dev_attr(attr)->index; 455 u32 power_attr = PL1_HWMON_ATTR; 456 int ret = 0; 457 458 xe_pm_runtime_get(hwmon->xe); 459 460 mutex_lock(&hwmon->hwmon_lock); 461 462 if (hwmon->xe->info.has_mbx_power_limits) { 463 ret = xe_hwmon_pcode_read_power_limit(hwmon, power_attr, channel, (u32 *)&r); 464 if (ret) { 465 drm_err(&hwmon->xe->drm, 466 "power interval read fail, ch %d, attr %d, r 0%llx, ret %d\n", 467 channel, power_attr, r, ret); 468 r = 0; 469 } 470 } else { 471 r = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel)); 472 } 473 474 mutex_unlock(&hwmon->hwmon_lock); 475 476 xe_pm_runtime_put(hwmon->xe); 477 478 x = REG_FIELD_GET(PWR_LIM_TIME_X, r); 479 y = REG_FIELD_GET(PWR_LIM_TIME_Y, r); 480 481 /* 482 * tau = (1 + (x / 4)) * power(2,y), x = bits(23:22), y = bits(21:17) 483 * = (4 | x) << (y - 2) 484 * 485 * Here (y - 2) ensures a 1.x fixed point representation of 1.x 486 * As x is 2 bits so 1.x can be 1.0, 1.25, 1.50, 1.75 487 * 488 * As y can be < 2, we compute tau4 = (4 | x) << y 489 * and then add 2 when doing the final right shift to account for units 490 */ 491 tau4 = (u64)((1 << x_w) | x) << y; 492 493 /* val in hwmon interface units (millisec) */ 494 out = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w); 495 496 return sysfs_emit(buf, "%llu\n", out); 497 } 498 499 static ssize_t 500 xe_hwmon_power_max_interval_store(struct device *dev, struct device_attribute *attr, 501 const char *buf, size_t count) 502 { 503 struct xe_hwmon *hwmon = dev_get_drvdata(dev); 504 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 505 u32 x, y, rxy, x_w = 2; /* 2 bits */ 506 u64 tau4, r, max_win; 507 unsigned long val; 508 int ret; 509 int channel = to_sensor_dev_attr(attr)->index; 510 u32 power_attr = PL1_HWMON_ATTR; 511 512 ret = kstrtoul(buf, 0, &val); 513 if (ret) 514 return ret; 515 516 /* 517 * Max HW supported tau in '(1 + (x / 4)) * power(2,y)' format, x = 0, y = 0x12. 518 * The hwmon->scl_shift_time default of 0xa results in a max tau of 256 seconds. 519 * 520 * The ideal scenario is for PKG_MAX_WIN to be read from the PKG_PWR_SKU register. 521 * However, it is observed that existing discrete GPUs does not provide correct 522 * PKG_MAX_WIN value, therefore a using default constant value. For future discrete GPUs 523 * this may get resolved, in which case PKG_MAX_WIN should be obtained from PKG_PWR_SKU. 524 */ 525 #define PKG_MAX_WIN_DEFAULT 0x12ull 526 527 /* 528 * val must be < max in hwmon interface units. The steps below are 529 * explained in xe_hwmon_power_max_interval_show() 530 */ 531 r = FIELD_PREP(PKG_MAX_WIN, PKG_MAX_WIN_DEFAULT); 532 x = REG_FIELD_GET(PKG_MAX_WIN_X, r); 533 y = REG_FIELD_GET(PKG_MAX_WIN_Y, r); 534 tau4 = (u64)((1 << x_w) | x) << y; 535 max_win = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w); 536 537 if (val > max_win) { 538 drm_warn(&hwmon->xe->drm, "power_interval invalid val 0x%lx\n", val); 539 return -EINVAL; 540 } 541 542 /* val in hw units */ 543 val = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_time, SF_TIME) + 1; 544 545 /* 546 * Convert val to 1.x * power(2,y) 547 * y = ilog2(val) 548 * x = (val - (1 << y)) >> (y - 2) 549 */ 550 if (!val) { 551 y = 0; 552 x = 0; 553 } else { 554 y = ilog2(val); 555 x = (val - (1ul << y)) << x_w >> y; 556 } 557 558 rxy = REG_FIELD_PREP(PWR_LIM_TIME_X, x) | 559 REG_FIELD_PREP(PWR_LIM_TIME_Y, y); 560 561 xe_pm_runtime_get(hwmon->xe); 562 563 mutex_lock(&hwmon->hwmon_lock); 564 565 if (hwmon->xe->info.has_mbx_power_limits) 566 xe_hwmon_pcode_rmw_power_limit(hwmon, power_attr, channel, PWR_LIM_TIME, rxy); 567 else 568 r = xe_mmio_rmw32(mmio, xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel), 569 PWR_LIM_TIME, rxy); 570 571 mutex_unlock(&hwmon->hwmon_lock); 572 573 xe_pm_runtime_put(hwmon->xe); 574 575 return count; 576 } 577 578 /* PSYS PL1 */ 579 static SENSOR_DEVICE_ATTR(power1_max_interval, 0664, 580 xe_hwmon_power_max_interval_show, 581 xe_hwmon_power_max_interval_store, CHANNEL_CARD); 582 583 static SENSOR_DEVICE_ATTR(power2_max_interval, 0664, 584 xe_hwmon_power_max_interval_show, 585 xe_hwmon_power_max_interval_store, CHANNEL_PKG); 586 587 static struct attribute *hwmon_attributes[] = { 588 &sensor_dev_attr_power1_max_interval.dev_attr.attr, 589 &sensor_dev_attr_power2_max_interval.dev_attr.attr, 590 NULL 591 }; 592 593 static umode_t xe_hwmon_attributes_visible(struct kobject *kobj, 594 struct attribute *attr, int index) 595 { 596 struct device *dev = kobj_to_dev(kobj); 597 struct xe_hwmon *hwmon = dev_get_drvdata(dev); 598 int ret = 0; 599 int channel = index ? CHANNEL_PKG : CHANNEL_CARD; 600 u32 power_attr = PL1_HWMON_ATTR; 601 u32 uval; 602 603 xe_pm_runtime_get(hwmon->xe); 604 605 if (hwmon->xe->info.has_mbx_power_limits) { 606 xe_hwmon_pcode_read_power_limit(hwmon, power_attr, channel, &uval); 607 ret = (uval & PWR_LIM_EN) ? attr->mode : 0; 608 } else { 609 ret = xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, 610 channel)) ? attr->mode : 0; 611 } 612 613 xe_pm_runtime_put(hwmon->xe); 614 615 return ret; 616 } 617 618 static const struct attribute_group hwmon_attrgroup = { 619 .attrs = hwmon_attributes, 620 .is_visible = xe_hwmon_attributes_visible, 621 }; 622 623 static const struct attribute_group *hwmon_groups[] = { 624 &hwmon_attrgroup, 625 NULL 626 }; 627 628 static const struct hwmon_channel_info * const hwmon_info[] = { 629 HWMON_CHANNEL_INFO(temp, HWMON_T_LABEL, HWMON_T_INPUT | HWMON_T_LABEL, 630 HWMON_T_INPUT | HWMON_T_LABEL), 631 HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_LABEL | HWMON_P_CRIT, 632 HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_LABEL), 633 HWMON_CHANNEL_INFO(curr, HWMON_C_LABEL, HWMON_C_CRIT | HWMON_C_LABEL), 634 HWMON_CHANNEL_INFO(in, HWMON_I_INPUT | HWMON_I_LABEL, HWMON_I_INPUT | HWMON_I_LABEL), 635 HWMON_CHANNEL_INFO(energy, HWMON_E_INPUT | HWMON_E_LABEL, HWMON_E_INPUT | HWMON_E_LABEL), 636 HWMON_CHANNEL_INFO(fan, HWMON_F_INPUT, HWMON_F_INPUT, HWMON_F_INPUT), 637 NULL 638 }; 639 640 /* I1 is exposed as power_crit or as curr_crit depending on bit 31 */ 641 static int xe_hwmon_pcode_read_i1(const struct xe_hwmon *hwmon, u32 *uval) 642 { 643 struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe); 644 645 /* Avoid Illegal Subcommand error */ 646 if (hwmon->xe->info.platform == XE_DG2) 647 return -ENXIO; 648 649 return xe_pcode_read(root_tile, PCODE_MBOX(PCODE_POWER_SETUP, 650 POWER_SETUP_SUBCOMMAND_READ_I1, 0), 651 uval, NULL); 652 } 653 654 static int xe_hwmon_pcode_write_i1(const struct xe_hwmon *hwmon, u32 uval) 655 { 656 struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe); 657 658 return xe_pcode_write(root_tile, PCODE_MBOX(PCODE_POWER_SETUP, 659 POWER_SETUP_SUBCOMMAND_WRITE_I1, 0), 660 (uval & POWER_SETUP_I1_DATA_MASK)); 661 } 662 663 static int xe_hwmon_pcode_read_fan_control(const struct xe_hwmon *hwmon, u32 subcmd, u32 *uval) 664 { 665 struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe); 666 667 /* Platforms that don't return correct value */ 668 if (hwmon->xe->info.platform == XE_DG2 && subcmd == FSC_READ_NUM_FANS) { 669 *uval = 2; 670 return 0; 671 } 672 673 return xe_pcode_read(root_tile, PCODE_MBOX(FAN_SPEED_CONTROL, subcmd, 0), uval, NULL); 674 } 675 676 static int xe_hwmon_power_curr_crit_read(struct xe_hwmon *hwmon, int channel, 677 long *value, u32 scale_factor) 678 { 679 int ret; 680 u32 uval; 681 682 mutex_lock(&hwmon->hwmon_lock); 683 684 ret = xe_hwmon_pcode_read_i1(hwmon, &uval); 685 if (ret) 686 goto unlock; 687 688 *value = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval), 689 scale_factor, POWER_SETUP_I1_SHIFT); 690 unlock: 691 mutex_unlock(&hwmon->hwmon_lock); 692 return ret; 693 } 694 695 static int xe_hwmon_power_curr_crit_write(struct xe_hwmon *hwmon, int channel, 696 long value, u32 scale_factor) 697 { 698 int ret; 699 u32 uval; 700 701 mutex_lock(&hwmon->hwmon_lock); 702 703 uval = DIV_ROUND_CLOSEST_ULL(value << POWER_SETUP_I1_SHIFT, scale_factor); 704 ret = xe_hwmon_pcode_write_i1(hwmon, uval); 705 706 mutex_unlock(&hwmon->hwmon_lock); 707 return ret; 708 } 709 710 static void xe_hwmon_get_voltage(struct xe_hwmon *hwmon, int channel, long *value) 711 { 712 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 713 u64 reg_val; 714 715 reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_GT_PERF_STATUS, channel)); 716 /* HW register value in units of 2.5 millivolt */ 717 *value = DIV_ROUND_CLOSEST(REG_FIELD_GET(VOLTAGE_MASK, reg_val) * 2500, SF_VOLTAGE); 718 } 719 720 static umode_t 721 xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel) 722 { 723 switch (attr) { 724 case hwmon_temp_input: 725 case hwmon_temp_label: 726 return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_TEMP, channel)) ? 0444 : 0; 727 default: 728 return 0; 729 } 730 } 731 732 static int 733 xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val) 734 { 735 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 736 u64 reg_val; 737 738 switch (attr) { 739 case hwmon_temp_input: 740 reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_TEMP, channel)); 741 742 /* HW register value is in degrees Celsius, convert to millidegrees. */ 743 *val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE; 744 return 0; 745 default: 746 return -EOPNOTSUPP; 747 } 748 } 749 750 static umode_t 751 xe_hwmon_power_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel) 752 { 753 u32 uval; 754 755 switch (attr) { 756 case hwmon_power_max: 757 if (hwmon->xe->info.has_mbx_power_limits) { 758 xe_hwmon_pcode_read_power_limit(hwmon, attr, channel, &uval); 759 return (uval) ? 0664 : 0; 760 } else { 761 return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, 762 channel)) ? 0664 : 0; 763 } 764 case hwmon_power_rated_max: 765 if (hwmon->xe->info.has_mbx_power_limits) 766 return 0; 767 else 768 return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU, 769 channel)) ? 0444 : 0; 770 case hwmon_power_crit: 771 case hwmon_power_label: 772 if (channel == CHANNEL_CARD) { 773 xe_hwmon_pcode_read_i1(hwmon, &uval); 774 return (uval & POWER_SETUP_I1_WATTS) ? (attr == hwmon_power_label) ? 775 0444 : 0644 : 0; 776 } 777 break; 778 default: 779 return 0; 780 } 781 return 0; 782 } 783 784 static int 785 xe_hwmon_power_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val) 786 { 787 switch (attr) { 788 case hwmon_power_max: 789 xe_hwmon_power_max_read(hwmon, attr, channel, val); 790 return 0; 791 case hwmon_power_rated_max: 792 xe_hwmon_power_rated_max_read(hwmon, attr, channel, val); 793 return 0; 794 case hwmon_power_crit: 795 return xe_hwmon_power_curr_crit_read(hwmon, channel, val, SF_POWER); 796 default: 797 return -EOPNOTSUPP; 798 } 799 } 800 801 static int 802 xe_hwmon_power_write(struct xe_hwmon *hwmon, u32 attr, int channel, long val) 803 { 804 switch (attr) { 805 case hwmon_power_max: 806 return xe_hwmon_power_max_write(hwmon, attr, channel, val); 807 case hwmon_power_crit: 808 return xe_hwmon_power_curr_crit_write(hwmon, channel, val, SF_POWER); 809 default: 810 return -EOPNOTSUPP; 811 } 812 } 813 814 static umode_t 815 xe_hwmon_curr_is_visible(const struct xe_hwmon *hwmon, u32 attr, int channel) 816 { 817 u32 uval; 818 819 /* hwmon sysfs attribute of current available only for package */ 820 if (channel != CHANNEL_PKG) 821 return 0; 822 823 switch (attr) { 824 case hwmon_curr_crit: 825 return (xe_hwmon_pcode_read_i1(hwmon, &uval) || 826 (uval & POWER_SETUP_I1_WATTS)) ? 0 : 0644; 827 case hwmon_curr_label: 828 return (xe_hwmon_pcode_read_i1(hwmon, &uval) || 829 (uval & POWER_SETUP_I1_WATTS)) ? 0 : 0444; 830 break; 831 default: 832 return 0; 833 } 834 return 0; 835 } 836 837 static int 838 xe_hwmon_curr_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val) 839 { 840 switch (attr) { 841 case hwmon_curr_crit: 842 return xe_hwmon_power_curr_crit_read(hwmon, channel, val, SF_CURR); 843 default: 844 return -EOPNOTSUPP; 845 } 846 } 847 848 static int 849 xe_hwmon_curr_write(struct xe_hwmon *hwmon, u32 attr, int channel, long val) 850 { 851 switch (attr) { 852 case hwmon_curr_crit: 853 return xe_hwmon_power_curr_crit_write(hwmon, channel, val, SF_CURR); 854 default: 855 return -EOPNOTSUPP; 856 } 857 } 858 859 static umode_t 860 xe_hwmon_in_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel) 861 { 862 switch (attr) { 863 case hwmon_in_input: 864 case hwmon_in_label: 865 return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_GT_PERF_STATUS, 866 channel)) ? 0444 : 0; 867 default: 868 return 0; 869 } 870 } 871 872 static int 873 xe_hwmon_in_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val) 874 { 875 switch (attr) { 876 case hwmon_in_input: 877 xe_hwmon_get_voltage(hwmon, channel, val); 878 return 0; 879 default: 880 return -EOPNOTSUPP; 881 } 882 } 883 884 static umode_t 885 xe_hwmon_energy_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel) 886 { 887 switch (attr) { 888 case hwmon_energy_input: 889 case hwmon_energy_label: 890 return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_PKG_ENERGY_STATUS, 891 channel)) ? 0444 : 0; 892 default: 893 return 0; 894 } 895 } 896 897 static int 898 xe_hwmon_energy_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val) 899 { 900 switch (attr) { 901 case hwmon_energy_input: 902 xe_hwmon_energy_get(hwmon, channel, val); 903 return 0; 904 default: 905 return -EOPNOTSUPP; 906 } 907 } 908 909 static umode_t 910 xe_hwmon_fan_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel) 911 { 912 u32 uval; 913 914 if (!hwmon->xe->info.has_fan_control) 915 return 0; 916 917 switch (attr) { 918 case hwmon_fan_input: 919 if (xe_hwmon_pcode_read_fan_control(hwmon, FSC_READ_NUM_FANS, &uval)) 920 return 0; 921 922 return channel < uval ? 0444 : 0; 923 default: 924 return 0; 925 } 926 } 927 928 static int 929 xe_hwmon_fan_input_read(struct xe_hwmon *hwmon, int channel, long *val) 930 { 931 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 932 struct xe_hwmon_fan_info *fi = &hwmon->fi[channel]; 933 u64 rotations, time_now, time; 934 u32 reg_val; 935 int ret = 0; 936 937 mutex_lock(&hwmon->hwmon_lock); 938 939 reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_FAN_SPEED, channel)); 940 time_now = get_jiffies_64(); 941 942 /* 943 * HW register value is accumulated count of pulses from PWM fan with the scale 944 * of 2 pulses per rotation. 945 */ 946 rotations = (reg_val - fi->reg_val_prev) / 2; 947 948 time = jiffies_delta_to_msecs(time_now - fi->time_prev); 949 if (unlikely(!time)) { 950 ret = -EAGAIN; 951 goto unlock; 952 } 953 954 /* 955 * Calculate fan speed in RPM by time averaging two subsequent readings in minutes. 956 * RPM = number of rotations * msecs per minute / time in msecs 957 */ 958 *val = DIV_ROUND_UP_ULL(rotations * (MSEC_PER_SEC * 60), time); 959 960 fi->reg_val_prev = reg_val; 961 fi->time_prev = time_now; 962 unlock: 963 mutex_unlock(&hwmon->hwmon_lock); 964 return ret; 965 } 966 967 static int 968 xe_hwmon_fan_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val) 969 { 970 switch (attr) { 971 case hwmon_fan_input: 972 return xe_hwmon_fan_input_read(hwmon, channel, val); 973 default: 974 return -EOPNOTSUPP; 975 } 976 } 977 978 static umode_t 979 xe_hwmon_is_visible(const void *drvdata, enum hwmon_sensor_types type, 980 u32 attr, int channel) 981 { 982 struct xe_hwmon *hwmon = (struct xe_hwmon *)drvdata; 983 int ret; 984 985 xe_pm_runtime_get(hwmon->xe); 986 987 switch (type) { 988 case hwmon_temp: 989 ret = xe_hwmon_temp_is_visible(hwmon, attr, channel); 990 break; 991 case hwmon_power: 992 ret = xe_hwmon_power_is_visible(hwmon, attr, channel); 993 break; 994 case hwmon_curr: 995 ret = xe_hwmon_curr_is_visible(hwmon, attr, channel); 996 break; 997 case hwmon_in: 998 ret = xe_hwmon_in_is_visible(hwmon, attr, channel); 999 break; 1000 case hwmon_energy: 1001 ret = xe_hwmon_energy_is_visible(hwmon, attr, channel); 1002 break; 1003 case hwmon_fan: 1004 ret = xe_hwmon_fan_is_visible(hwmon, attr, channel); 1005 break; 1006 default: 1007 ret = 0; 1008 break; 1009 } 1010 1011 xe_pm_runtime_put(hwmon->xe); 1012 1013 return ret; 1014 } 1015 1016 static int 1017 xe_hwmon_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, 1018 int channel, long *val) 1019 { 1020 struct xe_hwmon *hwmon = dev_get_drvdata(dev); 1021 int ret; 1022 1023 xe_pm_runtime_get(hwmon->xe); 1024 1025 switch (type) { 1026 case hwmon_temp: 1027 ret = xe_hwmon_temp_read(hwmon, attr, channel, val); 1028 break; 1029 case hwmon_power: 1030 ret = xe_hwmon_power_read(hwmon, attr, channel, val); 1031 break; 1032 case hwmon_curr: 1033 ret = xe_hwmon_curr_read(hwmon, attr, channel, val); 1034 break; 1035 case hwmon_in: 1036 ret = xe_hwmon_in_read(hwmon, attr, channel, val); 1037 break; 1038 case hwmon_energy: 1039 ret = xe_hwmon_energy_read(hwmon, attr, channel, val); 1040 break; 1041 case hwmon_fan: 1042 ret = xe_hwmon_fan_read(hwmon, attr, channel, val); 1043 break; 1044 default: 1045 ret = -EOPNOTSUPP; 1046 break; 1047 } 1048 1049 xe_pm_runtime_put(hwmon->xe); 1050 1051 return ret; 1052 } 1053 1054 static int 1055 xe_hwmon_write(struct device *dev, enum hwmon_sensor_types type, u32 attr, 1056 int channel, long val) 1057 { 1058 struct xe_hwmon *hwmon = dev_get_drvdata(dev); 1059 int ret; 1060 1061 xe_pm_runtime_get(hwmon->xe); 1062 1063 switch (type) { 1064 case hwmon_power: 1065 ret = xe_hwmon_power_write(hwmon, attr, channel, val); 1066 break; 1067 case hwmon_curr: 1068 ret = xe_hwmon_curr_write(hwmon, attr, channel, val); 1069 break; 1070 default: 1071 ret = -EOPNOTSUPP; 1072 break; 1073 } 1074 1075 xe_pm_runtime_put(hwmon->xe); 1076 1077 return ret; 1078 } 1079 1080 static int xe_hwmon_read_label(struct device *dev, 1081 enum hwmon_sensor_types type, 1082 u32 attr, int channel, const char **str) 1083 { 1084 switch (type) { 1085 case hwmon_temp: 1086 if (channel == CHANNEL_PKG) 1087 *str = "pkg"; 1088 else if (channel == CHANNEL_VRAM) 1089 *str = "vram"; 1090 return 0; 1091 case hwmon_power: 1092 case hwmon_energy: 1093 case hwmon_curr: 1094 case hwmon_in: 1095 if (channel == CHANNEL_CARD) 1096 *str = "card"; 1097 else if (channel == CHANNEL_PKG) 1098 *str = "pkg"; 1099 return 0; 1100 default: 1101 return -EOPNOTSUPP; 1102 } 1103 } 1104 1105 static const struct hwmon_ops hwmon_ops = { 1106 .is_visible = xe_hwmon_is_visible, 1107 .read = xe_hwmon_read, 1108 .write = xe_hwmon_write, 1109 .read_string = xe_hwmon_read_label, 1110 }; 1111 1112 static const struct hwmon_chip_info hwmon_chip_info = { 1113 .ops = &hwmon_ops, 1114 .info = hwmon_info, 1115 }; 1116 1117 static void 1118 xe_hwmon_get_preregistration_info(struct xe_hwmon *hwmon) 1119 { 1120 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 1121 long energy, fan_speed; 1122 u64 val_sku_unit = 0; 1123 int channel; 1124 struct xe_reg pkg_power_sku_unit; 1125 1126 if (hwmon->xe->info.has_mbx_power_limits) { 1127 /* Check if card firmware support mailbox power limits commands. */ 1128 if (xe_hwmon_pcode_read_power_limit(hwmon, PL1_HWMON_ATTR, CHANNEL_CARD, 1129 &hwmon->pl1_on_boot[CHANNEL_CARD]) | 1130 xe_hwmon_pcode_read_power_limit(hwmon, PL1_HWMON_ATTR, CHANNEL_PKG, 1131 &hwmon->pl1_on_boot[CHANNEL_PKG])) { 1132 drm_warn(&hwmon->xe->drm, 1133 "Failed to read power limits, check card firmware !\n"); 1134 } else { 1135 drm_info(&hwmon->xe->drm, "Using mailbox commands for power limits\n"); 1136 /* Write default limits to read from pcode from now on. */ 1137 xe_hwmon_pcode_rmw_power_limit(hwmon, PL1_HWMON_ATTR, 1138 CHANNEL_CARD, PWR_LIM | PWR_LIM_TIME, 1139 hwmon->pl1_on_boot[CHANNEL_CARD]); 1140 xe_hwmon_pcode_rmw_power_limit(hwmon, PL1_HWMON_ATTR, 1141 CHANNEL_PKG, PWR_LIM | PWR_LIM_TIME, 1142 hwmon->pl1_on_boot[CHANNEL_PKG]); 1143 hwmon->scl_shift_power = PWR_UNIT; 1144 hwmon->scl_shift_energy = ENERGY_UNIT; 1145 hwmon->scl_shift_time = TIME_UNIT; 1146 hwmon->boot_power_limit_read = true; 1147 } 1148 } else { 1149 drm_info(&hwmon->xe->drm, "Using register for power limits\n"); 1150 /* 1151 * The contents of register PKG_POWER_SKU_UNIT do not change, 1152 * so read it once and store the shift values. 1153 */ 1154 pkg_power_sku_unit = xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU_UNIT, 0); 1155 if (xe_reg_is_valid(pkg_power_sku_unit)) { 1156 val_sku_unit = xe_mmio_read32(mmio, pkg_power_sku_unit); 1157 hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit); 1158 hwmon->scl_shift_energy = REG_FIELD_GET(PKG_ENERGY_UNIT, val_sku_unit); 1159 hwmon->scl_shift_time = REG_FIELD_GET(PKG_TIME_UNIT, val_sku_unit); 1160 } 1161 } 1162 /* 1163 * Initialize 'struct xe_hwmon_energy_info', i.e. set fields to the 1164 * first value of the energy register read 1165 */ 1166 for (channel = 0; channel < CHANNEL_MAX; channel++) 1167 if (xe_hwmon_is_visible(hwmon, hwmon_energy, hwmon_energy_input, channel)) 1168 xe_hwmon_energy_get(hwmon, channel, &energy); 1169 1170 /* Initialize 'struct xe_hwmon_fan_info' with initial fan register reading. */ 1171 for (channel = 0; channel < FAN_MAX; channel++) 1172 if (xe_hwmon_is_visible(hwmon, hwmon_fan, hwmon_fan_input, channel)) 1173 xe_hwmon_fan_input_read(hwmon, channel, &fan_speed); 1174 } 1175 1176 static void xe_hwmon_mutex_destroy(void *arg) 1177 { 1178 struct xe_hwmon *hwmon = arg; 1179 1180 mutex_destroy(&hwmon->hwmon_lock); 1181 } 1182 1183 int xe_hwmon_register(struct xe_device *xe) 1184 { 1185 struct device *dev = xe->drm.dev; 1186 struct xe_hwmon *hwmon; 1187 int ret; 1188 1189 /* hwmon is available only for dGfx */ 1190 if (!IS_DGFX(xe)) 1191 return 0; 1192 1193 /* hwmon is not available on VFs */ 1194 if (IS_SRIOV_VF(xe)) 1195 return 0; 1196 1197 hwmon = devm_kzalloc(dev, sizeof(*hwmon), GFP_KERNEL); 1198 if (!hwmon) 1199 return -ENOMEM; 1200 1201 mutex_init(&hwmon->hwmon_lock); 1202 ret = devm_add_action_or_reset(dev, xe_hwmon_mutex_destroy, hwmon); 1203 if (ret) 1204 return ret; 1205 1206 /* There's only one instance of hwmon per device */ 1207 hwmon->xe = xe; 1208 xe->hwmon = hwmon; 1209 1210 xe_hwmon_get_preregistration_info(hwmon); 1211 1212 drm_dbg(&xe->drm, "Register xe hwmon interface\n"); 1213 1214 /* hwmon_dev points to device hwmon<i> */ 1215 hwmon->hwmon_dev = devm_hwmon_device_register_with_info(dev, "xe", hwmon, 1216 &hwmon_chip_info, 1217 hwmon_groups); 1218 if (IS_ERR(hwmon->hwmon_dev)) { 1219 drm_err(&xe->drm, "Failed to register xe hwmon (%pe)\n", hwmon->hwmon_dev); 1220 xe->hwmon = NULL; 1221 return PTR_ERR(hwmon->hwmon_dev); 1222 } 1223 1224 return 0; 1225 } 1226 1227