1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #include <linux/hwmon-sysfs.h> 7 #include <linux/hwmon.h> 8 #include <linux/jiffies.h> 9 #include <linux/types.h> 10 #include <linux/units.h> 11 12 #include <drm/drm_managed.h> 13 #include "regs/xe_gt_regs.h" 14 #include "regs/xe_mchbar_regs.h" 15 #include "regs/xe_pcode_regs.h" 16 #include "xe_device.h" 17 #include "xe_hwmon.h" 18 #include "xe_mmio.h" 19 #include "xe_pcode.h" 20 #include "xe_pcode_api.h" 21 #include "xe_sriov.h" 22 #include "xe_pm.h" 23 #include "xe_vsec.h" 24 #include "regs/xe_pmt.h" 25 26 enum xe_hwmon_reg { 27 REG_TEMP, 28 REG_PKG_RAPL_LIMIT, 29 REG_PKG_POWER_SKU, 30 REG_PKG_POWER_SKU_UNIT, 31 REG_GT_PERF_STATUS, 32 REG_PKG_ENERGY_STATUS, 33 REG_FAN_SPEED, 34 }; 35 36 enum xe_hwmon_reg_operation { 37 REG_READ32, 38 REG_RMW32, 39 REG_READ64, 40 }; 41 42 #define MAX_VRAM_CHANNELS (16) 43 44 enum xe_hwmon_channel { 45 CHANNEL_CARD, 46 CHANNEL_PKG, 47 CHANNEL_VRAM, 48 CHANNEL_MCTRL, 49 CHANNEL_PCIE, 50 CHANNEL_VRAM_N, 51 CHANNEL_VRAM_N_MAX = CHANNEL_VRAM_N + MAX_VRAM_CHANNELS - 1, 52 CHANNEL_MAX, 53 }; 54 55 enum xe_fan_channel { 56 FAN_1, 57 FAN_2, 58 FAN_3, 59 FAN_MAX, 60 }; 61 62 enum xe_temp_limit { 63 TEMP_LIMIT_PKG_SHUTDOWN, 64 TEMP_LIMIT_PKG_CRIT, 65 TEMP_LIMIT_MEM_SHUTDOWN, 66 TEMP_LIMIT_PKG_MAX, 67 TEMP_LIMIT_MEM_CRIT, 68 TEMP_LIMIT_MAX 69 }; 70 71 /* Attribute index for powerX_xxx_interval sysfs entries */ 72 enum sensor_attr_power { 73 SENSOR_INDEX_PSYS_PL1, 74 SENSOR_INDEX_PKG_PL1, 75 SENSOR_INDEX_PSYS_PL2, 76 SENSOR_INDEX_PKG_PL2, 77 }; 78 79 /* 80 * For platforms that support mailbox commands for power limits, REG_PKG_POWER_SKU_UNIT is 81 * not supported and below are SKU units to be used. 82 */ 83 #define PWR_UNIT 0x3 84 #define ENERGY_UNIT 0xe 85 #define TIME_UNIT 0xa 86 87 /* 88 * SF_* - scale factors for particular quantities according to hwmon spec. 89 */ 90 #define SF_POWER 1000000 /* microwatts */ 91 #define SF_CURR 1000 /* milliamperes */ 92 #define SF_VOLTAGE 1000 /* millivolts */ 93 #define SF_ENERGY 1000000 /* microjoules */ 94 #define SF_TIME 1000 /* milliseconds */ 95 96 /* 97 * PL*_HWMON_ATTR - mapping of hardware power limits to corresponding hwmon power attribute. 98 */ 99 #define PL1_HWMON_ATTR hwmon_power_max 100 #define PL2_HWMON_ATTR hwmon_power_cap 101 102 #define PWR_ATTR_TO_STR(attr) (((attr) == hwmon_power_max) ? "PL1" : "PL2") 103 104 /* 105 * Timeout for power limit write mailbox command. 106 */ 107 #define PL_WRITE_MBX_TIMEOUT_MS (1) 108 109 /* Index of memory controller in READ_THERMAL_DATA output */ 110 #define TEMP_INDEX_MCTRL 2 111 112 /* Maximum characters in hwmon label name */ 113 #define MAX_LABEL_SIZE 16 114 115 /** 116 * struct xe_hwmon_energy_info - to accumulate energy 117 */ 118 struct xe_hwmon_energy_info { 119 /** @reg_val_prev: previous energy reg val */ 120 u32 reg_val_prev; 121 /** @accum_energy: accumulated energy */ 122 long accum_energy; 123 }; 124 125 /** 126 * struct xe_hwmon_fan_info - to cache previous fan reading 127 */ 128 struct xe_hwmon_fan_info { 129 /** @reg_val_prev: previous fan reg val */ 130 u32 reg_val_prev; 131 /** @time_prev: previous timestamp */ 132 u64 time_prev; 133 }; 134 135 /** 136 * struct xe_hwmon_thermal_info - to store temperature data 137 */ 138 struct xe_hwmon_thermal_info { 139 union { 140 /** @limit: temperatures limits */ 141 u8 limit[TEMP_LIMIT_MAX]; 142 /** @data: temperature limits in dwords */ 143 u32 data[DIV_ROUND_UP(TEMP_LIMIT_MAX, sizeof(u32))]; 144 }; 145 /** @count: no of temperature sensors available for the platform */ 146 u8 count; 147 /** @value: signed value from each sensor */ 148 s8 value[U8_MAX]; 149 /** @vram_label: vram label names */ 150 char vram_label[MAX_VRAM_CHANNELS][MAX_LABEL_SIZE]; 151 }; 152 153 /** 154 * struct xe_hwmon - xe hwmon data structure 155 */ 156 struct xe_hwmon { 157 /** @hwmon_dev: hwmon device for xe */ 158 struct device *hwmon_dev; 159 /** @xe: Xe device */ 160 struct xe_device *xe; 161 /** @hwmon_lock: lock for rw attributes*/ 162 struct mutex hwmon_lock; 163 /** @scl_shift_power: pkg power unit */ 164 int scl_shift_power; 165 /** @scl_shift_energy: pkg energy unit */ 166 int scl_shift_energy; 167 /** @scl_shift_time: pkg time unit */ 168 int scl_shift_time; 169 /** @ei: Energy info for energyN_input */ 170 struct xe_hwmon_energy_info ei[CHANNEL_MAX]; 171 /** @fi: Fan info for fanN_input */ 172 struct xe_hwmon_fan_info fi[FAN_MAX]; 173 /** @boot_power_limit_read: is boot power limits read */ 174 bool boot_power_limit_read; 175 /** @pl1_on_boot: power limit PL1 on boot */ 176 u32 pl1_on_boot[CHANNEL_MAX]; 177 /** @pl2_on_boot: power limit PL2 on boot */ 178 u32 pl2_on_boot[CHANNEL_MAX]; 179 /** @temp: Temperature info */ 180 struct xe_hwmon_thermal_info temp; 181 }; 182 183 static inline int prepare_power_limit_param2(const struct xe_hwmon *hwmon) 184 { 185 if (hwmon->boot_power_limit_read) { 186 if (hwmon->xe->info.platform >= XE_CRESCENTISLAND) 187 return READ_PL_ACCEPTED; 188 else 189 return READ_PL_FROM_PCODE; 190 } else { 191 return READ_PL_FROM_FW; 192 } 193 } 194 195 static int xe_hwmon_pcode_read_power_limit(const struct xe_hwmon *hwmon, u32 attr, int channel, 196 u32 *uval) 197 { 198 struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe); 199 u32 val0 = 0, val1 = 0; 200 int ret = 0; 201 202 ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_POWER_SETUP, 203 (channel == CHANNEL_CARD) ? 204 READ_PSYSGPU_POWER_LIMIT : 205 READ_PACKAGE_POWER_LIMIT, 206 prepare_power_limit_param2(hwmon)), &val0, &val1); 207 208 if (ret) { 209 drm_dbg(&hwmon->xe->drm, "read failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n", 210 channel, val0, val1, ret); 211 *uval = 0; 212 return ret; 213 } 214 215 /* return the value only if limit is enabled */ 216 if (attr == PL1_HWMON_ATTR) 217 *uval = (val0 & PWR_LIM_EN) ? val0 : 0; 218 else if (attr == PL2_HWMON_ATTR) 219 *uval = (val1 & PWR_LIM_EN) ? val1 : 0; 220 else if (attr == hwmon_power_label) 221 *uval = (val0 & PWR_LIM_EN) ? 1 : (val1 & PWR_LIM_EN) ? 1 : 0; 222 else 223 *uval = 0; 224 225 return ret; 226 } 227 228 static int xe_hwmon_pcode_rmw_power_limit(const struct xe_hwmon *hwmon, u32 attr, u8 channel, 229 u32 clr, u32 set) 230 { 231 struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe); 232 u32 val0 = 0, val1 = 0; 233 int ret = 0; 234 235 ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_POWER_SETUP, 236 (channel == CHANNEL_CARD) ? 237 READ_PSYSGPU_POWER_LIMIT : 238 READ_PACKAGE_POWER_LIMIT, 239 prepare_power_limit_param2(hwmon)), &val0, &val1); 240 if (ret) 241 drm_dbg(&hwmon->xe->drm, "read failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n", 242 channel, val0, val1, ret); 243 244 if (attr == PL1_HWMON_ATTR) 245 val0 = (val0 & ~clr) | set; 246 else if (attr == PL2_HWMON_ATTR) 247 val1 = (val1 & ~clr) | set; 248 else 249 return -EIO; 250 251 ret = xe_pcode_write64_timeout(root_tile, PCODE_MBOX(PCODE_POWER_SETUP, 252 (channel == CHANNEL_CARD) ? 253 WRITE_PSYSGPU_POWER_LIMIT : 254 WRITE_PACKAGE_POWER_LIMIT, 0), 255 val0, val1, PL_WRITE_MBX_TIMEOUT_MS); 256 if (ret) 257 drm_dbg(&hwmon->xe->drm, "write failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n", 258 channel, val0, val1, ret); 259 return ret; 260 } 261 262 static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg, 263 int channel) 264 { 265 struct xe_device *xe = hwmon->xe; 266 267 switch (hwmon_reg) { 268 case REG_TEMP: 269 if (xe->info.platform == XE_BATTLEMAGE) { 270 if (channel == CHANNEL_PKG) 271 return BMG_PACKAGE_TEMPERATURE; 272 else if (channel == CHANNEL_VRAM) 273 return BMG_VRAM_TEMPERATURE; 274 else if (in_range(channel, CHANNEL_VRAM_N, MAX_VRAM_CHANNELS)) 275 return BMG_VRAM_TEMPERATURE_N(channel - CHANNEL_VRAM_N); 276 } else if (xe->info.platform == XE_DG2) { 277 if (channel == CHANNEL_PKG) 278 return PCU_CR_PACKAGE_TEMPERATURE; 279 else if (channel == CHANNEL_VRAM) 280 return BMG_VRAM_TEMPERATURE; 281 } 282 break; 283 case REG_PKG_RAPL_LIMIT: 284 if (xe->info.platform == XE_PVC && channel == CHANNEL_PKG) 285 return PVC_GT0_PACKAGE_RAPL_LIMIT; 286 else if ((xe->info.platform == XE_DG2) && (channel == CHANNEL_PKG)) 287 return PCU_CR_PACKAGE_RAPL_LIMIT; 288 break; 289 case REG_PKG_POWER_SKU: 290 if (xe->info.platform == XE_PVC && channel == CHANNEL_PKG) 291 return PVC_GT0_PACKAGE_POWER_SKU; 292 else if ((xe->info.platform == XE_DG2) && (channel == CHANNEL_PKG)) 293 return PCU_CR_PACKAGE_POWER_SKU; 294 break; 295 case REG_PKG_POWER_SKU_UNIT: 296 if (xe->info.platform == XE_PVC) 297 return PVC_GT0_PACKAGE_POWER_SKU_UNIT; 298 else if (xe->info.platform == XE_DG2) 299 return PCU_CR_PACKAGE_POWER_SKU_UNIT; 300 break; 301 case REG_GT_PERF_STATUS: 302 if (xe->info.platform == XE_DG2 && channel == CHANNEL_PKG) 303 return GT_PERF_STATUS; 304 break; 305 case REG_PKG_ENERGY_STATUS: 306 if (xe->info.platform == XE_CRESCENTISLAND) { 307 if (channel == CHANNEL_CARD) 308 return CRI_PLATFORM_ENERGY_STATUS; 309 else if (channel == CHANNEL_PKG) 310 return CRI_PACKAGE_ENERGY_STATUS; 311 } else if (xe->info.platform == XE_PVC && channel == CHANNEL_PKG) { 312 return PVC_GT0_PLATFORM_ENERGY_STATUS; 313 } else if ((xe->info.platform == XE_DG2) && (channel == CHANNEL_PKG)) { 314 return PCU_CR_PACKAGE_ENERGY_STATUS; 315 } 316 break; 317 case REG_FAN_SPEED: 318 if (channel == FAN_1) 319 return BMG_FAN_1_SPEED; 320 else if (channel == FAN_2) 321 return BMG_FAN_2_SPEED; 322 else if (channel == FAN_3) 323 return BMG_FAN_3_SPEED; 324 break; 325 default: 326 drm_warn(&xe->drm, "Unknown xe hwmon reg id: %d\n", hwmon_reg); 327 break; 328 } 329 330 return XE_REG(0); 331 } 332 333 #define PL_DISABLE 0 334 335 /* 336 * HW allows arbitrary PL1 limits to be set but silently clamps these values to 337 * "typical but not guaranteed" min/max values in REG_PKG_POWER_SKU. Follow the 338 * same pattern for sysfs, allow arbitrary PL1 limits to be set but display 339 * clamped values when read. 340 */ 341 static void xe_hwmon_power_max_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *value) 342 { 343 u32 reg_val = 0; 344 struct xe_device *xe = hwmon->xe; 345 struct xe_reg rapl_limit, pkg_power_sku; 346 struct xe_mmio *mmio = xe_root_tile_mmio(xe); 347 348 mutex_lock(&hwmon->hwmon_lock); 349 350 if (hwmon->xe->info.has_mbx_power_limits) { 351 xe_hwmon_pcode_read_power_limit(hwmon, attr, channel, ®_val); 352 } else { 353 rapl_limit = xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel); 354 pkg_power_sku = xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU, channel); 355 reg_val = xe_mmio_read32(mmio, rapl_limit); 356 } 357 358 /* Check if PL limits are disabled. */ 359 if (!(reg_val & PWR_LIM_EN)) { 360 *value = PL_DISABLE; 361 drm_info(&hwmon->xe->drm, "%s disabled for channel %d, val 0x%08x\n", 362 PWR_ATTR_TO_STR(attr), channel, reg_val); 363 goto unlock; 364 } 365 366 reg_val = REG_FIELD_GET(PWR_LIM_VAL, reg_val); 367 *value = mul_u32_u32(reg_val, SF_POWER) >> hwmon->scl_shift_power; 368 369 /* For platforms with mailbox power limit support clamping would be done by pcode. */ 370 if (!hwmon->xe->info.has_mbx_power_limits) { 371 u64 pkg_pwr, min, max; 372 373 pkg_pwr = xe_mmio_read64_2x32(mmio, pkg_power_sku); 374 min = REG_FIELD_GET(PKG_MIN_PWR, pkg_pwr); 375 max = REG_FIELD_GET(PKG_MAX_PWR, pkg_pwr); 376 min = mul_u64_u32_shr(min, SF_POWER, hwmon->scl_shift_power); 377 max = mul_u64_u32_shr(max, SF_POWER, hwmon->scl_shift_power); 378 if (min && max) 379 *value = clamp_t(u64, *value, min, max); 380 } 381 unlock: 382 mutex_unlock(&hwmon->hwmon_lock); 383 } 384 385 static int xe_hwmon_power_max_write(struct xe_hwmon *hwmon, u32 attr, int channel, long value) 386 { 387 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 388 int ret = 0; 389 u32 reg_val, max; 390 struct xe_reg rapl_limit; 391 u64 max_supp_power_limit = 0; 392 393 mutex_lock(&hwmon->hwmon_lock); 394 395 rapl_limit = xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel); 396 397 /* Disable Power Limit and verify, as limit cannot be disabled on all platforms. */ 398 if (value == PL_DISABLE) { 399 if (hwmon->xe->info.has_mbx_power_limits) { 400 drm_dbg(&hwmon->xe->drm, "disabling %s on channel %d\n", 401 PWR_ATTR_TO_STR(attr), channel); 402 xe_hwmon_pcode_rmw_power_limit(hwmon, attr, channel, PWR_LIM_EN, 0); 403 xe_hwmon_pcode_read_power_limit(hwmon, attr, channel, ®_val); 404 } else { 405 reg_val = xe_mmio_rmw32(mmio, rapl_limit, PWR_LIM_EN, 0); 406 reg_val = xe_mmio_read32(mmio, rapl_limit); 407 } 408 409 if (reg_val & PWR_LIM_EN) { 410 drm_warn(&hwmon->xe->drm, "Power limit disable is not supported!\n"); 411 ret = -EOPNOTSUPP; 412 } 413 goto unlock; 414 } 415 416 /* 417 * If the sysfs value exceeds the maximum pcode supported power limit value, clamp it to 418 * the supported maximum (U12.3 format). 419 * This is to avoid truncation during reg_val calculation below and ensure the valid 420 * power limit is sent for pcode which would clamp it to card-supported value. 421 */ 422 max_supp_power_limit = ((PWR_LIM_VAL) >> hwmon->scl_shift_power) * SF_POWER; 423 if (value > max_supp_power_limit) { 424 value = max_supp_power_limit; 425 drm_info(&hwmon->xe->drm, 426 "Power limit clamped as selected %s exceeds channel %d limit\n", 427 PWR_ATTR_TO_STR(attr), channel); 428 } 429 430 /* Computation in 64-bits to avoid overflow. Round to nearest. */ 431 reg_val = DIV_ROUND_CLOSEST_ULL((u64)value << hwmon->scl_shift_power, SF_POWER); 432 433 /* 434 * Clamp power limit to GPU firmware default as maximum, as an additional protection to 435 * pcode clamp. 436 */ 437 if (hwmon->xe->info.has_mbx_power_limits) { 438 max = (attr == PL1_HWMON_ATTR) ? 439 hwmon->pl1_on_boot[channel] : hwmon->pl2_on_boot[channel]; 440 max = REG_FIELD_PREP(PWR_LIM_VAL, max); 441 if (reg_val > max) { 442 reg_val = max; 443 drm_dbg(&hwmon->xe->drm, 444 "Clamping power limit to GPU firmware default 0x%x\n", 445 reg_val); 446 } 447 } 448 449 reg_val = PWR_LIM_EN | REG_FIELD_PREP(PWR_LIM_VAL, reg_val); 450 451 if (hwmon->xe->info.has_mbx_power_limits) 452 ret = xe_hwmon_pcode_rmw_power_limit(hwmon, attr, channel, PWR_LIM, reg_val); 453 else 454 reg_val = xe_mmio_rmw32(mmio, rapl_limit, PWR_LIM, reg_val); 455 unlock: 456 mutex_unlock(&hwmon->hwmon_lock); 457 return ret; 458 } 459 460 static void xe_hwmon_power_rated_max_read(struct xe_hwmon *hwmon, u32 attr, int channel, 461 long *value) 462 { 463 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 464 u32 reg_val; 465 466 if (hwmon->xe->info.has_mbx_power_limits) { 467 /* PL1 is rated max if supported. */ 468 xe_hwmon_pcode_read_power_limit(hwmon, PL1_HWMON_ATTR, channel, ®_val); 469 } else { 470 /* 471 * This sysfs file won't be visible if REG_PKG_POWER_SKU is invalid, so valid check 472 * for this register can be skipped. 473 * See xe_hwmon_power_is_visible. 474 */ 475 struct xe_reg reg = xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU, channel); 476 477 reg_val = xe_mmio_read32(mmio, reg); 478 } 479 480 reg_val = REG_FIELD_GET(PKG_TDP, reg_val); 481 *value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon->scl_shift_power); 482 } 483 484 /* 485 * xe_hwmon_energy_get - Obtain energy value 486 * 487 * The underlying energy hardware register is 32-bits and is subject to 488 * overflow. How long before overflow? For example, with an example 489 * scaling bit shift of 14 bits (see register *PACKAGE_POWER_SKU_UNIT) and 490 * a power draw of 1000 watts, the 32-bit counter will overflow in 491 * approximately 4.36 minutes. 492 * 493 * Examples: 494 * 1 watt: (2^32 >> 14) / 1 W / (60 * 60 * 24) secs/day -> 3 days 495 * 1000 watts: (2^32 >> 14) / 1000 W / 60 secs/min -> 4.36 minutes 496 * 497 * The function significantly increases overflow duration (from 4.36 498 * minutes) by accumulating the energy register into a 'long' as allowed by 499 * the hwmon API. Using x86_64 128 bit arithmetic (see mul_u64_u32_shr()), 500 * a 'long' of 63 bits, SF_ENERGY of 1e6 (~20 bits) and 501 * hwmon->scl_shift_energy of 14 bits we have 57 (63 - 20 + 14) bits before 502 * energyN_input overflows. This at 1000 W is an overflow duration of 278 years. 503 */ 504 static void 505 xe_hwmon_energy_get(struct xe_hwmon *hwmon, int channel, long *energy) 506 { 507 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 508 struct xe_hwmon_energy_info *ei = &hwmon->ei[channel]; 509 u32 reg_val; 510 int ret = 0; 511 512 /* Energy is supported only for card and pkg */ 513 if (channel > CHANNEL_PKG) { 514 *energy = 0; 515 return; 516 } 517 518 if (hwmon->xe->info.platform == XE_BATTLEMAGE) { 519 u64 pmt_val; 520 521 ret = xe_pmt_telem_read(hwmon->xe->drm.dev, 522 xe_mmio_read32(mmio, PUNIT_TELEMETRY_GUID), 523 &pmt_val, BMG_ENERGY_STATUS_PMT_OFFSET, sizeof(pmt_val)); 524 if (ret != sizeof(pmt_val)) { 525 drm_warn(&hwmon->xe->drm, "energy read from pmt failed, ret %d\n", ret); 526 *energy = 0; 527 return; 528 } 529 530 if (channel == CHANNEL_PKG) 531 reg_val = REG_FIELD_GET64(ENERGY_PKG, pmt_val); 532 else 533 reg_val = REG_FIELD_GET64(ENERGY_CARD, pmt_val); 534 } else { 535 reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_PKG_ENERGY_STATUS, 536 channel)); 537 } 538 539 ei->accum_energy += reg_val - ei->reg_val_prev; 540 ei->reg_val_prev = reg_val; 541 542 *energy = mul_u64_u32_shr(ei->accum_energy, SF_ENERGY, 543 hwmon->scl_shift_energy); 544 } 545 546 static ssize_t 547 xe_hwmon_power_max_interval_show(struct device *dev, struct device_attribute *attr, 548 char *buf) 549 { 550 struct xe_hwmon *hwmon = dev_get_drvdata(dev); 551 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 552 u32 reg_val, x, y, x_w = 2; /* 2 bits */ 553 u64 tau4, out; 554 int channel = (to_sensor_dev_attr(attr)->index % 2) ? CHANNEL_PKG : CHANNEL_CARD; 555 u32 power_attr = (to_sensor_dev_attr(attr)->index > 1) ? PL2_HWMON_ATTR : PL1_HWMON_ATTR; 556 557 int ret = 0; 558 559 guard(xe_pm_runtime)(hwmon->xe); 560 561 mutex_lock(&hwmon->hwmon_lock); 562 563 if (hwmon->xe->info.has_mbx_power_limits) { 564 ret = xe_hwmon_pcode_read_power_limit(hwmon, power_attr, channel, ®_val); 565 if (ret) { 566 drm_err(&hwmon->xe->drm, 567 "power interval read fail, ch %d, attr %d, val 0x%08x, ret %d\n", 568 channel, power_attr, reg_val, ret); 569 reg_val = 0; 570 } 571 } else { 572 reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, 573 channel)); 574 } 575 576 mutex_unlock(&hwmon->hwmon_lock); 577 578 x = REG_FIELD_GET(PWR_LIM_TIME_X, reg_val); 579 y = REG_FIELD_GET(PWR_LIM_TIME_Y, reg_val); 580 581 /* 582 * tau = (1 + (x / 4)) * power(2,y), x = bits(23:22), y = bits(21:17) 583 * = (4 | x) << (y - 2) 584 * 585 * Here (y - 2) ensures a 1.x fixed point representation of 1.x 586 * As x is 2 bits so 1.x can be 1.0, 1.25, 1.50, 1.75 587 * 588 * As y can be < 2, we compute tau4 = (4 | x) << y 589 * and then add 2 when doing the final right shift to account for units 590 */ 591 tau4 = (u64)((1 << x_w) | x) << y; 592 593 /* val in hwmon interface units (millisec) */ 594 out = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w); 595 596 return sysfs_emit(buf, "%llu\n", out); 597 } 598 599 static ssize_t 600 xe_hwmon_power_max_interval_store(struct device *dev, struct device_attribute *attr, 601 const char *buf, size_t count) 602 { 603 struct xe_hwmon *hwmon = dev_get_drvdata(dev); 604 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 605 u32 x, y, rxy, x_w = 2; /* 2 bits */ 606 u64 tau4, r, max_win; 607 unsigned long val; 608 int channel = (to_sensor_dev_attr(attr)->index % 2) ? CHANNEL_PKG : CHANNEL_CARD; 609 u32 power_attr = (to_sensor_dev_attr(attr)->index > 1) ? PL2_HWMON_ATTR : PL1_HWMON_ATTR; 610 int ret; 611 612 ret = kstrtoul(buf, 0, &val); 613 if (ret) 614 return ret; 615 616 /* 617 * Max HW supported tau in '(1 + (x / 4)) * power(2,y)' format, x = 0, y = 0x12. 618 * The hwmon->scl_shift_time default of 0xa results in a max tau of 256 seconds. 619 * 620 * The ideal scenario is for PKG_MAX_WIN to be read from the PKG_PWR_SKU register. 621 * However, it is observed that existing discrete GPUs does not provide correct 622 * PKG_MAX_WIN value, therefore a using default constant value. For future discrete GPUs 623 * this may get resolved, in which case PKG_MAX_WIN should be obtained from PKG_PWR_SKU. 624 */ 625 #define PKG_MAX_WIN_DEFAULT 0x12ull 626 627 /* 628 * val must be < max in hwmon interface units. The steps below are 629 * explained in xe_hwmon_power_max_interval_show() 630 */ 631 r = FIELD_PREP(PKG_MAX_WIN, PKG_MAX_WIN_DEFAULT); 632 x = REG_FIELD_GET(PKG_MAX_WIN_X, r); 633 y = REG_FIELD_GET(PKG_MAX_WIN_Y, r); 634 tau4 = (u64)((1 << x_w) | x) << y; 635 max_win = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w); 636 637 if (val > max_win) 638 return -EINVAL; 639 640 /* val in hw units */ 641 val = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_time, SF_TIME) + 1; 642 643 /* 644 * Convert val to 1.x * power(2,y) 645 * y = ilog2(val) 646 * x = (val - (1 << y)) >> (y - 2) 647 */ 648 if (!val) { 649 y = 0; 650 x = 0; 651 } else { 652 y = ilog2(val); 653 x = (val - (1ul << y)) << x_w >> y; 654 } 655 656 rxy = REG_FIELD_PREP(PWR_LIM_TIME_X, x) | 657 REG_FIELD_PREP(PWR_LIM_TIME_Y, y); 658 659 guard(xe_pm_runtime)(hwmon->xe); 660 661 mutex_lock(&hwmon->hwmon_lock); 662 663 if (hwmon->xe->info.has_mbx_power_limits) 664 xe_hwmon_pcode_rmw_power_limit(hwmon, power_attr, channel, PWR_LIM_TIME, rxy); 665 else 666 r = xe_mmio_rmw32(mmio, xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel), 667 PWR_LIM_TIME, rxy); 668 669 mutex_unlock(&hwmon->hwmon_lock); 670 671 return count; 672 } 673 674 /* PSYS PL1 */ 675 static SENSOR_DEVICE_ATTR(power1_max_interval, 0664, 676 xe_hwmon_power_max_interval_show, 677 xe_hwmon_power_max_interval_store, SENSOR_INDEX_PSYS_PL1); 678 /* PKG PL1 */ 679 static SENSOR_DEVICE_ATTR(power2_max_interval, 0664, 680 xe_hwmon_power_max_interval_show, 681 xe_hwmon_power_max_interval_store, SENSOR_INDEX_PKG_PL1); 682 /* PSYS PL2 */ 683 static SENSOR_DEVICE_ATTR(power1_cap_interval, 0664, 684 xe_hwmon_power_max_interval_show, 685 xe_hwmon_power_max_interval_store, SENSOR_INDEX_PSYS_PL2); 686 /* PKG PL2 */ 687 static SENSOR_DEVICE_ATTR(power2_cap_interval, 0664, 688 xe_hwmon_power_max_interval_show, 689 xe_hwmon_power_max_interval_store, SENSOR_INDEX_PKG_PL2); 690 691 static struct attribute *hwmon_attributes[] = { 692 &sensor_dev_attr_power1_max_interval.dev_attr.attr, 693 &sensor_dev_attr_power2_max_interval.dev_attr.attr, 694 &sensor_dev_attr_power1_cap_interval.dev_attr.attr, 695 &sensor_dev_attr_power2_cap_interval.dev_attr.attr, 696 NULL 697 }; 698 699 static umode_t xe_hwmon_attributes_visible(struct kobject *kobj, 700 struct attribute *attr, int index) 701 { 702 struct device *dev = kobj_to_dev(kobj); 703 struct xe_hwmon *hwmon = dev_get_drvdata(dev); 704 int ret = 0; 705 int channel = (index % 2) ? CHANNEL_PKG : CHANNEL_CARD; 706 u32 power_attr = (index > 1) ? PL2_HWMON_ATTR : PL1_HWMON_ATTR; 707 u32 uval = 0; 708 struct xe_reg rapl_limit; 709 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 710 711 if (hwmon->xe->info.has_mbx_power_limits) { 712 xe_hwmon_pcode_read_power_limit(hwmon, power_attr, channel, &uval); 713 } else if (power_attr != PL2_HWMON_ATTR) { 714 rapl_limit = xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel); 715 if (xe_reg_is_valid(rapl_limit)) 716 uval = xe_mmio_read32(mmio, rapl_limit); 717 } 718 ret = (uval & PWR_LIM_EN) ? attr->mode : 0; 719 720 return ret; 721 } 722 723 static const struct attribute_group hwmon_attrgroup = { 724 .attrs = hwmon_attributes, 725 .is_visible = xe_hwmon_attributes_visible, 726 }; 727 728 static const struct attribute_group *hwmon_groups[] = { 729 &hwmon_attrgroup, 730 NULL 731 }; 732 733 static const struct hwmon_channel_info * const hwmon_info[] = { 734 HWMON_CHANNEL_INFO(temp, 735 HWMON_T_LABEL, 736 HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL | 737 HWMON_T_MAX, 738 HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL, 739 HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL, 740 HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL, 741 HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL, 742 HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL, 743 HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL, 744 HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL, 745 HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL, 746 HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL, 747 HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL, 748 HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL, 749 HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL, 750 HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL, 751 HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL, 752 HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL, 753 HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL, 754 HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL, 755 HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL, 756 HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL), 757 HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_LABEL | HWMON_P_CRIT | 758 HWMON_P_CAP, 759 HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_LABEL | HWMON_P_CAP), 760 HWMON_CHANNEL_INFO(curr, HWMON_C_LABEL, HWMON_C_CRIT | HWMON_C_LABEL), 761 HWMON_CHANNEL_INFO(in, HWMON_I_INPUT | HWMON_I_LABEL, HWMON_I_INPUT | HWMON_I_LABEL), 762 HWMON_CHANNEL_INFO(energy, HWMON_E_INPUT | HWMON_E_LABEL, HWMON_E_INPUT | HWMON_E_LABEL), 763 HWMON_CHANNEL_INFO(fan, HWMON_F_INPUT, HWMON_F_INPUT, HWMON_F_INPUT), 764 NULL 765 }; 766 767 static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon) 768 { 769 struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe); 770 u32 config = 0; 771 int ret; 772 773 ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_LIMITS, 0), 774 &hwmon->temp.data[0], &hwmon->temp.data[1]); 775 if (ret) 776 return ret; 777 778 drm_dbg(&hwmon->xe->drm, "thermal info read val 0x%x val1 0x%x\n", 779 hwmon->temp.data[0], hwmon->temp.data[1]); 780 781 ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_CONFIG, 0), 782 &config, NULL); 783 if (ret) 784 return ret; 785 786 drm_dbg(&hwmon->xe->drm, "thermal config count 0x%x\n", config); 787 hwmon->temp.count = REG_FIELD_GET(TEMP_MASK, config); 788 789 return ret; 790 } 791 792 static int get_mc_temp(struct xe_hwmon *hwmon, long *val) 793 { 794 struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe); 795 u32 *dword = (u32 *)hwmon->temp.value; 796 s32 average = 0; 797 int ret, i; 798 799 for (i = 0; i < DIV_ROUND_UP(TEMP_LIMIT_MAX, sizeof(u32)); i++) { 800 ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA, i), 801 (dword + i), NULL); 802 if (ret) 803 return ret; 804 drm_dbg(&hwmon->xe->drm, "thermal data for group %d val 0x%x\n", i, dword[i]); 805 } 806 807 for (i = TEMP_INDEX_MCTRL; i < hwmon->temp.count - 1; i++) 808 average += hwmon->temp.value[i]; 809 810 average /= (hwmon->temp.count - TEMP_INDEX_MCTRL - 1); 811 *val = average * MILLIDEGREE_PER_DEGREE; 812 return 0; 813 } 814 815 static int get_pcie_temp(struct xe_hwmon *hwmon, long *val) 816 { 817 struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe); 818 u32 data = 0; 819 int ret; 820 821 ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA, 822 PCIE_SENSOR_GROUP_ID), &data, NULL); 823 if (ret) 824 return ret; 825 826 /* Sensor offset is different for G21 */ 827 if (hwmon->xe->info.subplatform != XE_SUBPLATFORM_BATTLEMAGE_G21) 828 data = REG_FIELD_GET(PCIE_SENSOR_MASK, data); 829 830 data = REG_FIELD_GET(TEMP_MASK, data); 831 *val = (s8)data * MILLIDEGREE_PER_DEGREE; 832 833 return 0; 834 } 835 836 /* I1 is exposed as power_crit or as curr_crit depending on bit 31 */ 837 static int xe_hwmon_pcode_read_i1(const struct xe_hwmon *hwmon, u32 *uval) 838 { 839 struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe); 840 841 /* Avoid Illegal Subcommand error */ 842 if (hwmon->xe->info.platform == XE_DG2) 843 return -ENXIO; 844 845 return xe_pcode_read(root_tile, PCODE_MBOX(PCODE_POWER_SETUP, 846 POWER_SETUP_SUBCOMMAND_READ_I1, 0), 847 uval, NULL); 848 } 849 850 static int xe_hwmon_pcode_write_i1(const struct xe_hwmon *hwmon, u32 uval) 851 { 852 struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe); 853 854 return xe_pcode_write(root_tile, PCODE_MBOX(PCODE_POWER_SETUP, 855 POWER_SETUP_SUBCOMMAND_WRITE_I1, 0), 856 (uval & POWER_SETUP_I1_DATA_MASK)); 857 } 858 859 static int xe_hwmon_pcode_read_fan_control(const struct xe_hwmon *hwmon, u32 subcmd, u32 *uval) 860 { 861 struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe); 862 863 /* Platforms that don't return correct value */ 864 if (hwmon->xe->info.platform == XE_DG2 && subcmd == FSC_READ_NUM_FANS) { 865 *uval = 2; 866 return 0; 867 } 868 869 return xe_pcode_read(root_tile, PCODE_MBOX(FAN_SPEED_CONTROL, subcmd, 0), uval, NULL); 870 } 871 872 static int xe_hwmon_power_curr_crit_read(struct xe_hwmon *hwmon, int channel, 873 long *value, u32 scale_factor) 874 { 875 int ret; 876 u32 uval = 0; 877 878 mutex_lock(&hwmon->hwmon_lock); 879 880 ret = xe_hwmon_pcode_read_i1(hwmon, &uval); 881 if (ret) 882 goto unlock; 883 884 *value = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval), 885 scale_factor, POWER_SETUP_I1_SHIFT); 886 unlock: 887 mutex_unlock(&hwmon->hwmon_lock); 888 return ret; 889 } 890 891 static int xe_hwmon_power_curr_crit_write(struct xe_hwmon *hwmon, int channel, 892 long value, u32 scale_factor) 893 { 894 int ret; 895 u32 uval; 896 u64 max_crit_power_curr = 0; 897 898 mutex_lock(&hwmon->hwmon_lock); 899 900 /* 901 * If the sysfs value exceeds the pcode mailbox cmd POWER_SETUP_SUBCOMMAND_WRITE_I1 902 * max supported value, clamp it to the command's max (U10.6 format). 903 * This is to avoid truncation during uval calculation below and ensure the valid power 904 * limit is sent for pcode which would clamp it to card-supported value. 905 */ 906 max_crit_power_curr = (POWER_SETUP_I1_DATA_MASK >> POWER_SETUP_I1_SHIFT) * scale_factor; 907 if (value > max_crit_power_curr) { 908 value = max_crit_power_curr; 909 drm_info(&hwmon->xe->drm, 910 "Power limit clamped as selected exceeds channel %d limit\n", 911 channel); 912 } 913 uval = DIV_ROUND_CLOSEST_ULL(value << POWER_SETUP_I1_SHIFT, scale_factor); 914 ret = xe_hwmon_pcode_write_i1(hwmon, uval); 915 916 mutex_unlock(&hwmon->hwmon_lock); 917 return ret; 918 } 919 920 static void xe_hwmon_get_voltage(struct xe_hwmon *hwmon, int channel, long *value) 921 { 922 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 923 u64 reg_val; 924 925 reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_GT_PERF_STATUS, channel)); 926 /* HW register value in units of 2.5 millivolt */ 927 *value = DIV_ROUND_CLOSEST(REG_FIELD_GET(VOLTAGE_MASK, reg_val) * 2500, SF_VOLTAGE); 928 } 929 930 static inline bool is_vram_ch_available(struct xe_hwmon *hwmon, int channel) 931 { 932 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 933 int vram_id = channel - CHANNEL_VRAM_N; 934 struct xe_reg vram_reg; 935 936 vram_reg = xe_hwmon_get_reg(hwmon, REG_TEMP, channel); 937 if (!xe_reg_is_valid(vram_reg) || !xe_mmio_read32(mmio, vram_reg)) 938 return false; 939 940 /* Create label only for available vram channel */ 941 sprintf(hwmon->temp.vram_label[vram_id], "vram_ch_%d", vram_id); 942 return true; 943 } 944 945 static umode_t 946 xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel) 947 { 948 switch (attr) { 949 case hwmon_temp_emergency: 950 switch (channel) { 951 case CHANNEL_PKG: 952 return hwmon->temp.limit[TEMP_LIMIT_PKG_SHUTDOWN] ? 0444 : 0; 953 case CHANNEL_VRAM: 954 return hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] ? 0444 : 0; 955 case CHANNEL_MCTRL: 956 case CHANNEL_PCIE: 957 return hwmon->temp.count ? 0444 : 0; 958 case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX: 959 return (is_vram_ch_available(hwmon, channel) && 960 hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN]) ? 0444 : 0; 961 default: 962 return 0; 963 } 964 case hwmon_temp_crit: 965 switch (channel) { 966 case CHANNEL_PKG: 967 return hwmon->temp.limit[TEMP_LIMIT_PKG_CRIT] ? 0444 : 0; 968 case CHANNEL_VRAM: 969 return hwmon->temp.limit[TEMP_LIMIT_MEM_CRIT] ? 0444 : 0; 970 case CHANNEL_MCTRL: 971 case CHANNEL_PCIE: 972 return hwmon->temp.count ? 0444 : 0; 973 case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX: 974 return (is_vram_ch_available(hwmon, channel) && 975 hwmon->temp.limit[TEMP_LIMIT_MEM_CRIT]) ? 0444 : 0; 976 default: 977 return 0; 978 } 979 case hwmon_temp_max: 980 switch (channel) { 981 case CHANNEL_PKG: 982 return hwmon->temp.limit[TEMP_LIMIT_PKG_MAX] ? 0444 : 0; 983 default: 984 return 0; 985 } 986 case hwmon_temp_input: 987 case hwmon_temp_label: 988 switch (channel) { 989 case CHANNEL_PKG: 990 case CHANNEL_VRAM: 991 return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_TEMP, 992 channel)) ? 0444 : 0; 993 case CHANNEL_MCTRL: 994 case CHANNEL_PCIE: 995 return hwmon->temp.count ? 0444 : 0; 996 case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX: 997 return is_vram_ch_available(hwmon, channel) ? 0444 : 0; 998 default: 999 return 0; 1000 } 1001 default: 1002 return 0; 1003 } 1004 } 1005 1006 static int 1007 xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val) 1008 { 1009 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 1010 u64 reg_val; 1011 1012 switch (attr) { 1013 case hwmon_temp_input: 1014 switch (channel) { 1015 case CHANNEL_PKG: 1016 case CHANNEL_VRAM: 1017 reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_TEMP, channel)); 1018 1019 /* HW register value is in degrees Celsius, convert to millidegrees. */ 1020 *val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE; 1021 return 0; 1022 case CHANNEL_MCTRL: 1023 return get_mc_temp(hwmon, val); 1024 case CHANNEL_PCIE: 1025 return get_pcie_temp(hwmon, val); 1026 case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX: 1027 reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_TEMP, channel)); 1028 /* 1029 * This temperature format is 24 bit [31:8] signed integer and 8 bit 1030 * [7:0] fraction. 1031 */ 1032 *val = (s32)(REG_FIELD_GET(TEMP_MASK_VRAM_N, reg_val)) * 1033 (REG_FIELD_GET(TEMP_SIGN_MASK, reg_val) ? -1 : 1) * 1034 MILLIDEGREE_PER_DEGREE; 1035 return 0; 1036 default: 1037 return -EOPNOTSUPP; 1038 } 1039 case hwmon_temp_emergency: 1040 switch (channel) { 1041 case CHANNEL_PKG: 1042 case CHANNEL_MCTRL: 1043 case CHANNEL_PCIE: 1044 *val = hwmon->temp.limit[TEMP_LIMIT_PKG_SHUTDOWN] * MILLIDEGREE_PER_DEGREE; 1045 return 0; 1046 case CHANNEL_VRAM: 1047 case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX: 1048 *val = hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] * MILLIDEGREE_PER_DEGREE; 1049 return 0; 1050 default: 1051 return -EOPNOTSUPP; 1052 } 1053 case hwmon_temp_crit: 1054 switch (channel) { 1055 case CHANNEL_PKG: 1056 case CHANNEL_MCTRL: 1057 case CHANNEL_PCIE: 1058 *val = hwmon->temp.limit[TEMP_LIMIT_PKG_CRIT] * MILLIDEGREE_PER_DEGREE; 1059 return 0; 1060 case CHANNEL_VRAM: 1061 case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX: 1062 *val = hwmon->temp.limit[TEMP_LIMIT_MEM_CRIT] * MILLIDEGREE_PER_DEGREE; 1063 return 0; 1064 default: 1065 return -EOPNOTSUPP; 1066 } 1067 case hwmon_temp_max: 1068 switch (channel) { 1069 case CHANNEL_PKG: 1070 *val = hwmon->temp.limit[TEMP_LIMIT_PKG_MAX] * MILLIDEGREE_PER_DEGREE; 1071 return 0; 1072 default: 1073 return -EOPNOTSUPP; 1074 } 1075 default: 1076 return -EOPNOTSUPP; 1077 } 1078 } 1079 1080 static umode_t 1081 xe_hwmon_power_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel) 1082 { 1083 u32 uval = 0; 1084 struct xe_reg reg; 1085 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 1086 1087 switch (attr) { 1088 case hwmon_power_max: 1089 case hwmon_power_cap: 1090 if (hwmon->xe->info.has_mbx_power_limits) { 1091 xe_hwmon_pcode_read_power_limit(hwmon, attr, channel, &uval); 1092 } else if (attr != PL2_HWMON_ATTR) { 1093 reg = xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel); 1094 if (xe_reg_is_valid(reg)) 1095 uval = xe_mmio_read32(mmio, reg); 1096 } 1097 if (uval & PWR_LIM_EN) { 1098 drm_info(&hwmon->xe->drm, "%s is supported on channel %d\n", 1099 PWR_ATTR_TO_STR(attr), channel); 1100 return 0664; 1101 } 1102 drm_dbg(&hwmon->xe->drm, "%s is unsupported on channel %d\n", 1103 PWR_ATTR_TO_STR(attr), channel); 1104 return 0; 1105 case hwmon_power_rated_max: 1106 if (hwmon->xe->info.has_mbx_power_limits) { 1107 return 0; 1108 } else { 1109 reg = xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU, channel); 1110 if (xe_reg_is_valid(reg)) 1111 uval = xe_mmio_read32(mmio, reg); 1112 return uval ? 0444 : 0; 1113 } 1114 case hwmon_power_crit: 1115 if (channel == CHANNEL_CARD) { 1116 xe_hwmon_pcode_read_i1(hwmon, &uval); 1117 return (uval & POWER_SETUP_I1_WATTS) ? 0644 : 0; 1118 } 1119 break; 1120 case hwmon_power_label: 1121 if (hwmon->xe->info.has_mbx_power_limits) { 1122 xe_hwmon_pcode_read_power_limit(hwmon, attr, channel, &uval); 1123 } else { 1124 reg = xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU, channel); 1125 if (xe_reg_is_valid(reg)) 1126 uval = xe_mmio_read32(mmio, reg); 1127 1128 if (!uval) { 1129 reg = xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel); 1130 if (xe_reg_is_valid(reg)) 1131 uval = xe_mmio_read32(mmio, reg); 1132 } 1133 } 1134 if ((!(uval & PWR_LIM_EN)) && channel == CHANNEL_CARD) { 1135 xe_hwmon_pcode_read_i1(hwmon, &uval); 1136 return (uval & POWER_SETUP_I1_WATTS) ? 0444 : 0; 1137 } 1138 return (uval) ? 0444 : 0; 1139 default: 1140 return 0; 1141 } 1142 return 0; 1143 } 1144 1145 static int 1146 xe_hwmon_power_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val) 1147 { 1148 switch (attr) { 1149 case hwmon_power_max: 1150 case hwmon_power_cap: 1151 xe_hwmon_power_max_read(hwmon, attr, channel, val); 1152 return 0; 1153 case hwmon_power_rated_max: 1154 xe_hwmon_power_rated_max_read(hwmon, attr, channel, val); 1155 return 0; 1156 case hwmon_power_crit: 1157 return xe_hwmon_power_curr_crit_read(hwmon, channel, val, SF_POWER); 1158 default: 1159 return -EOPNOTSUPP; 1160 } 1161 } 1162 1163 static int 1164 xe_hwmon_power_write(struct xe_hwmon *hwmon, u32 attr, int channel, long val) 1165 { 1166 switch (attr) { 1167 case hwmon_power_cap: 1168 case hwmon_power_max: 1169 return xe_hwmon_power_max_write(hwmon, attr, channel, val); 1170 case hwmon_power_crit: 1171 return xe_hwmon_power_curr_crit_write(hwmon, channel, val, SF_POWER); 1172 default: 1173 return -EOPNOTSUPP; 1174 } 1175 } 1176 1177 static umode_t 1178 xe_hwmon_curr_is_visible(const struct xe_hwmon *hwmon, u32 attr, int channel) 1179 { 1180 u32 uval = 0; 1181 1182 /* hwmon sysfs attribute of current available only for package */ 1183 if (channel != CHANNEL_PKG) 1184 return 0; 1185 1186 switch (attr) { 1187 case hwmon_curr_crit: 1188 return (xe_hwmon_pcode_read_i1(hwmon, &uval) || 1189 (uval & POWER_SETUP_I1_WATTS)) ? 0 : 0644; 1190 case hwmon_curr_label: 1191 return (xe_hwmon_pcode_read_i1(hwmon, &uval) || 1192 (uval & POWER_SETUP_I1_WATTS)) ? 0 : 0444; 1193 break; 1194 default: 1195 return 0; 1196 } 1197 return 0; 1198 } 1199 1200 static int 1201 xe_hwmon_curr_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val) 1202 { 1203 switch (attr) { 1204 case hwmon_curr_crit: 1205 return xe_hwmon_power_curr_crit_read(hwmon, channel, val, SF_CURR); 1206 default: 1207 return -EOPNOTSUPP; 1208 } 1209 } 1210 1211 static int 1212 xe_hwmon_curr_write(struct xe_hwmon *hwmon, u32 attr, int channel, long val) 1213 { 1214 switch (attr) { 1215 case hwmon_curr_crit: 1216 return xe_hwmon_power_curr_crit_write(hwmon, channel, val, SF_CURR); 1217 default: 1218 return -EOPNOTSUPP; 1219 } 1220 } 1221 1222 static umode_t 1223 xe_hwmon_in_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel) 1224 { 1225 switch (attr) { 1226 case hwmon_in_input: 1227 case hwmon_in_label: 1228 return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_GT_PERF_STATUS, 1229 channel)) ? 0444 : 0; 1230 default: 1231 return 0; 1232 } 1233 } 1234 1235 static int 1236 xe_hwmon_in_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val) 1237 { 1238 switch (attr) { 1239 case hwmon_in_input: 1240 xe_hwmon_get_voltage(hwmon, channel, val); 1241 return 0; 1242 default: 1243 return -EOPNOTSUPP; 1244 } 1245 } 1246 1247 static umode_t 1248 xe_hwmon_energy_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel) 1249 { 1250 long energy = 0; 1251 1252 switch (attr) { 1253 case hwmon_energy_input: 1254 case hwmon_energy_label: 1255 if (hwmon->xe->info.platform == XE_BATTLEMAGE) { 1256 xe_hwmon_energy_get(hwmon, channel, &energy); 1257 return energy ? 0444 : 0; 1258 } else { 1259 return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_PKG_ENERGY_STATUS, 1260 channel)) ? 0444 : 0; 1261 } 1262 default: 1263 return 0; 1264 } 1265 } 1266 1267 static int 1268 xe_hwmon_energy_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val) 1269 { 1270 switch (attr) { 1271 case hwmon_energy_input: 1272 xe_hwmon_energy_get(hwmon, channel, val); 1273 return 0; 1274 default: 1275 return -EOPNOTSUPP; 1276 } 1277 } 1278 1279 static umode_t 1280 xe_hwmon_fan_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel) 1281 { 1282 u32 uval = 0; 1283 1284 if (!hwmon->xe->info.has_fan_control) 1285 return 0; 1286 1287 switch (attr) { 1288 case hwmon_fan_input: 1289 if (xe_hwmon_pcode_read_fan_control(hwmon, FSC_READ_NUM_FANS, &uval)) 1290 return 0; 1291 1292 return channel < uval ? 0444 : 0; 1293 default: 1294 return 0; 1295 } 1296 } 1297 1298 static int 1299 xe_hwmon_fan_input_read(struct xe_hwmon *hwmon, int channel, long *val) 1300 { 1301 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 1302 struct xe_hwmon_fan_info *fi = &hwmon->fi[channel]; 1303 u64 rotations, time_now, time; 1304 u32 reg_val; 1305 int ret = 0; 1306 1307 mutex_lock(&hwmon->hwmon_lock); 1308 1309 reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_FAN_SPEED, channel)); 1310 time_now = get_jiffies_64(); 1311 1312 /* 1313 * HW register value is accumulated count of pulses from PWM fan with the scale 1314 * of 2 pulses per rotation. 1315 */ 1316 rotations = (reg_val - fi->reg_val_prev) / 2; 1317 1318 time = jiffies_delta_to_msecs(time_now - fi->time_prev); 1319 if (unlikely(!time)) { 1320 ret = -EAGAIN; 1321 goto unlock; 1322 } 1323 1324 /* 1325 * Calculate fan speed in RPM by time averaging two subsequent readings in minutes. 1326 * RPM = number of rotations * msecs per minute / time in msecs 1327 */ 1328 *val = DIV_ROUND_UP_ULL(rotations * (MSEC_PER_SEC * 60), time); 1329 1330 fi->reg_val_prev = reg_val; 1331 fi->time_prev = time_now; 1332 unlock: 1333 mutex_unlock(&hwmon->hwmon_lock); 1334 return ret; 1335 } 1336 1337 static int 1338 xe_hwmon_fan_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val) 1339 { 1340 switch (attr) { 1341 case hwmon_fan_input: 1342 return xe_hwmon_fan_input_read(hwmon, channel, val); 1343 default: 1344 return -EOPNOTSUPP; 1345 } 1346 } 1347 1348 static umode_t 1349 xe_hwmon_is_visible(const void *drvdata, enum hwmon_sensor_types type, 1350 u32 attr, int channel) 1351 { 1352 struct xe_hwmon *hwmon = (struct xe_hwmon *)drvdata; 1353 int ret; 1354 1355 switch (type) { 1356 case hwmon_temp: 1357 ret = xe_hwmon_temp_is_visible(hwmon, attr, channel); 1358 break; 1359 case hwmon_power: 1360 ret = xe_hwmon_power_is_visible(hwmon, attr, channel); 1361 break; 1362 case hwmon_curr: 1363 ret = xe_hwmon_curr_is_visible(hwmon, attr, channel); 1364 break; 1365 case hwmon_in: 1366 ret = xe_hwmon_in_is_visible(hwmon, attr, channel); 1367 break; 1368 case hwmon_energy: 1369 ret = xe_hwmon_energy_is_visible(hwmon, attr, channel); 1370 break; 1371 case hwmon_fan: 1372 ret = xe_hwmon_fan_is_visible(hwmon, attr, channel); 1373 break; 1374 default: 1375 ret = 0; 1376 break; 1377 } 1378 1379 return ret; 1380 } 1381 1382 static int 1383 xe_hwmon_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, 1384 int channel, long *val) 1385 { 1386 struct xe_hwmon *hwmon = dev_get_drvdata(dev); 1387 1388 guard(xe_pm_runtime)(hwmon->xe); 1389 1390 switch (type) { 1391 case hwmon_temp: 1392 return xe_hwmon_temp_read(hwmon, attr, channel, val); 1393 case hwmon_power: 1394 return xe_hwmon_power_read(hwmon, attr, channel, val); 1395 case hwmon_curr: 1396 return xe_hwmon_curr_read(hwmon, attr, channel, val); 1397 case hwmon_in: 1398 return xe_hwmon_in_read(hwmon, attr, channel, val); 1399 case hwmon_energy: 1400 return xe_hwmon_energy_read(hwmon, attr, channel, val); 1401 case hwmon_fan: 1402 return xe_hwmon_fan_read(hwmon, attr, channel, val); 1403 default: 1404 return -EOPNOTSUPP; 1405 } 1406 } 1407 1408 static int 1409 xe_hwmon_write(struct device *dev, enum hwmon_sensor_types type, u32 attr, 1410 int channel, long val) 1411 { 1412 struct xe_hwmon *hwmon = dev_get_drvdata(dev); 1413 1414 guard(xe_pm_runtime)(hwmon->xe); 1415 1416 switch (type) { 1417 case hwmon_power: 1418 return xe_hwmon_power_write(hwmon, attr, channel, val); 1419 case hwmon_curr: 1420 return xe_hwmon_curr_write(hwmon, attr, channel, val); 1421 default: 1422 return -EOPNOTSUPP; 1423 } 1424 } 1425 1426 static int xe_hwmon_read_label(struct device *dev, 1427 enum hwmon_sensor_types type, 1428 u32 attr, int channel, const char **str) 1429 { 1430 struct xe_hwmon *hwmon = dev_get_drvdata(dev); 1431 1432 switch (type) { 1433 case hwmon_temp: 1434 if (channel == CHANNEL_PKG) 1435 *str = "pkg"; 1436 else if (channel == CHANNEL_VRAM) 1437 *str = "vram"; 1438 else if (channel == CHANNEL_MCTRL) 1439 *str = "mctrl"; 1440 else if (channel == CHANNEL_PCIE) 1441 *str = "pcie"; 1442 else if (in_range(channel, CHANNEL_VRAM_N, MAX_VRAM_CHANNELS)) 1443 *str = hwmon->temp.vram_label[channel - CHANNEL_VRAM_N]; 1444 return 0; 1445 case hwmon_power: 1446 case hwmon_energy: 1447 case hwmon_curr: 1448 case hwmon_in: 1449 if (channel == CHANNEL_CARD) 1450 *str = "card"; 1451 else if (channel == CHANNEL_PKG) 1452 *str = "pkg"; 1453 return 0; 1454 default: 1455 return -EOPNOTSUPP; 1456 } 1457 } 1458 1459 static const struct hwmon_ops hwmon_ops = { 1460 .is_visible = xe_hwmon_is_visible, 1461 .read = xe_hwmon_read, 1462 .write = xe_hwmon_write, 1463 .read_string = xe_hwmon_read_label, 1464 }; 1465 1466 static const struct hwmon_chip_info hwmon_chip_info = { 1467 .ops = &hwmon_ops, 1468 .info = hwmon_info, 1469 }; 1470 1471 static void 1472 xe_hwmon_get_preregistration_info(struct xe_hwmon *hwmon) 1473 { 1474 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 1475 long energy, fan_speed; 1476 u64 val_sku_unit = 0; 1477 int channel; 1478 struct xe_reg pkg_power_sku_unit; 1479 1480 if (hwmon->xe->info.has_mbx_power_limits) { 1481 /* Check if GPU firmware support mailbox power limits commands. */ 1482 if (xe_hwmon_pcode_read_power_limit(hwmon, PL1_HWMON_ATTR, CHANNEL_CARD, 1483 &hwmon->pl1_on_boot[CHANNEL_CARD]) | 1484 xe_hwmon_pcode_read_power_limit(hwmon, PL1_HWMON_ATTR, CHANNEL_PKG, 1485 &hwmon->pl1_on_boot[CHANNEL_PKG]) | 1486 xe_hwmon_pcode_read_power_limit(hwmon, PL2_HWMON_ATTR, CHANNEL_CARD, 1487 &hwmon->pl2_on_boot[CHANNEL_CARD]) | 1488 xe_hwmon_pcode_read_power_limit(hwmon, PL2_HWMON_ATTR, CHANNEL_PKG, 1489 &hwmon->pl2_on_boot[CHANNEL_PKG])) { 1490 drm_warn(&hwmon->xe->drm, 1491 "Failed to read power limits, check GPU firmware !\n"); 1492 } else { 1493 drm_info(&hwmon->xe->drm, "Using mailbox commands for power limits\n"); 1494 /* Write default limits to read from pcode from now on. */ 1495 xe_hwmon_pcode_rmw_power_limit(hwmon, PL1_HWMON_ATTR, 1496 CHANNEL_CARD, PWR_LIM | PWR_LIM_TIME, 1497 hwmon->pl1_on_boot[CHANNEL_CARD]); 1498 xe_hwmon_pcode_rmw_power_limit(hwmon, PL1_HWMON_ATTR, 1499 CHANNEL_PKG, PWR_LIM | PWR_LIM_TIME, 1500 hwmon->pl1_on_boot[CHANNEL_PKG]); 1501 xe_hwmon_pcode_rmw_power_limit(hwmon, PL2_HWMON_ATTR, 1502 CHANNEL_CARD, PWR_LIM | PWR_LIM_TIME, 1503 hwmon->pl2_on_boot[CHANNEL_CARD]); 1504 xe_hwmon_pcode_rmw_power_limit(hwmon, PL2_HWMON_ATTR, 1505 CHANNEL_PKG, PWR_LIM | PWR_LIM_TIME, 1506 hwmon->pl2_on_boot[CHANNEL_PKG]); 1507 hwmon->scl_shift_power = PWR_UNIT; 1508 hwmon->scl_shift_energy = ENERGY_UNIT; 1509 hwmon->scl_shift_time = TIME_UNIT; 1510 hwmon->boot_power_limit_read = true; 1511 } 1512 } else { 1513 drm_info(&hwmon->xe->drm, "Using register for power limits\n"); 1514 /* 1515 * The contents of register PKG_POWER_SKU_UNIT do not change, 1516 * so read it once and store the shift values. 1517 */ 1518 pkg_power_sku_unit = xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU_UNIT, 0); 1519 if (xe_reg_is_valid(pkg_power_sku_unit)) { 1520 val_sku_unit = xe_mmio_read32(mmio, pkg_power_sku_unit); 1521 hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit); 1522 hwmon->scl_shift_energy = REG_FIELD_GET(PKG_ENERGY_UNIT, val_sku_unit); 1523 hwmon->scl_shift_time = REG_FIELD_GET(PKG_TIME_UNIT, val_sku_unit); 1524 } 1525 } 1526 /* 1527 * Initialize 'struct xe_hwmon_energy_info', i.e. set fields to the 1528 * first value of the energy register read 1529 */ 1530 for (channel = 0; channel < CHANNEL_MAX; channel++) 1531 if (xe_hwmon_is_visible(hwmon, hwmon_energy, hwmon_energy_input, channel)) 1532 xe_hwmon_energy_get(hwmon, channel, &energy); 1533 1534 /* Initialize 'struct xe_hwmon_fan_info' with initial fan register reading. */ 1535 for (channel = 0; channel < FAN_MAX; channel++) 1536 if (xe_hwmon_is_visible(hwmon, hwmon_fan, hwmon_fan_input, channel)) 1537 xe_hwmon_fan_input_read(hwmon, channel, &fan_speed); 1538 1539 if (hwmon->xe->info.has_mbx_thermal_info && xe_hwmon_pcode_read_thermal_info(hwmon)) 1540 drm_warn(&hwmon->xe->drm, "Thermal mailbox not supported by card firmware\n"); 1541 } 1542 1543 int xe_hwmon_register(struct xe_device *xe) 1544 { 1545 struct device *dev = xe->drm.dev; 1546 struct xe_hwmon *hwmon; 1547 int ret; 1548 1549 /* hwmon is available only for dGfx */ 1550 if (!IS_DGFX(xe)) 1551 return 0; 1552 1553 /* hwmon is not available on VFs */ 1554 if (IS_SRIOV_VF(xe)) 1555 return 0; 1556 1557 hwmon = devm_kzalloc(dev, sizeof(*hwmon), GFP_KERNEL); 1558 if (!hwmon) 1559 return -ENOMEM; 1560 1561 ret = devm_mutex_init(dev, &hwmon->hwmon_lock); 1562 if (ret) 1563 return ret; 1564 1565 /* There's only one instance of hwmon per device */ 1566 hwmon->xe = xe; 1567 xe->hwmon = hwmon; 1568 1569 xe_hwmon_get_preregistration_info(hwmon); 1570 1571 drm_dbg(&xe->drm, "Register xe hwmon interface\n"); 1572 1573 /* hwmon_dev points to device hwmon<i> */ 1574 hwmon->hwmon_dev = devm_hwmon_device_register_with_info(dev, "xe", hwmon, 1575 &hwmon_chip_info, 1576 hwmon_groups); 1577 if (IS_ERR(hwmon->hwmon_dev)) { 1578 drm_err(&xe->drm, "Failed to register xe hwmon (%pe)\n", hwmon->hwmon_dev); 1579 xe->hwmon = NULL; 1580 return PTR_ERR(hwmon->hwmon_dev); 1581 } 1582 1583 return 0; 1584 } 1585 MODULE_IMPORT_NS("INTEL_PMT_TELEMETRY"); 1586